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-rw-r--r--include/ACEX1K.h6
-rw-r--r--include/SA-1100.h3394
-rw-r--r--include/ahci.h10
-rw-r--r--include/armcoremodule.h10
-rw-r--r--include/asm-arm/arch-arm720t/netarm_mem_module.h18
-rw-r--r--include/asm-arm/arch-arm720t/netarm_ser_module.h32
-rw-r--r--include/asm-arm/arch-arm720t/s3c4510b.h10
-rw-r--r--include/asm-arm/arch-at91rm9200/AT91RM9200.h382
-rw-r--r--include/asm-arm/arch-at91sam9/at91_pmc.h5
-rw-r--r--include/asm-arm/arch-at91sam9/at91cap9.h14
-rw-r--r--include/asm-arm/arch-at91sam9/at91sam9261.h105
-rw-r--r--include/asm-arm/arch-at91sam9/at91sam9261_matrix.h64
-rw-r--r--include/asm-arm/arch-at91sam9/at91sam9263.h127
-rw-r--r--include/asm-arm/arch-at91sam9/at91sam9263_matrix.h129
-rw-r--r--include/asm-arm/arch-at91sam9/at91sam9rl.h115
-rw-r--r--include/asm-arm/arch-at91sam9/at91sam9rl_matrix.h96
-rw-r--r--include/asm-arm/arch-at91sam9/clk.h6
-rw-r--r--include/asm-arm/arch-at91sam9/gpio.h4
-rw-r--r--include/asm-arm/arch-at91sam9/hardware.h20
-rw-r--r--include/asm-arm/arch-ixp/ixp425.h76
-rw-r--r--include/asm-arm/arch-omap24xx/clocks.h12
-rw-r--r--include/asm-arm/arch-pxa/bitfield.h44
-rw-r--r--include/asm-arm/arch-pxa/mmc.h107
-rw-r--r--include/asm-arm/arch-s3c24x0/memory.h8
-rw-r--r--include/asm-arm/arch-sa1100/bitfield.h44
-rw-r--r--include/asm-arm/global_data.h2
-rw-r--r--include/asm-arm/u-boot.h2
-rw-r--r--include/asm-avr32/arch-at32ap700x/chip-features.h1
-rw-r--r--include/asm-avr32/arch-at32ap700x/clk.h10
-rw-r--r--include/asm-avr32/arch-at32ap700x/gpio.h4
-rw-r--r--include/asm-avr32/arch-at32ap700x/hmatrix.h61
-rw-r--r--include/asm-avr32/arch-at32ap700x/hmatrix2.h232
-rw-r--r--include/asm-avr32/arch-at32ap700x/memory-map.h20
-rw-r--r--include/asm-avr32/arch-at32ap700x/mmc.h6
-rw-r--r--include/asm-avr32/global_data.h2
-rw-r--r--include/asm-avr32/hmatrix-common.h131
-rw-r--r--include/asm-avr32/sdram.h27
-rw-r--r--include/asm-avr32/sections.h7
-rw-r--r--include/asm-avr32/u-boot.h11
-rw-r--r--include/asm-blackfin/cplb.h4
-rw-r--r--include/asm-blackfin/global_data.h2
-rw-r--r--include/asm-blackfin/shared_resources.h2
-rw-r--r--include/asm-i386/global_data.h2
-rw-r--r--include/asm-i386/ic/sc520.h390
-rw-r--r--include/asm-m68k/global_data.h2
-rw-r--r--include/asm-m68k/m5249.h2
-rw-r--r--include/asm-m68k/m5282.h18
-rw-r--r--include/asm-microblaze/asm.h4
-rw-r--r--include/asm-microblaze/global_data.h2
-rw-r--r--include/asm-mips/au1x00.h2
-rw-r--r--include/asm-mips/cacheops.h2
-rw-r--r--include/asm-mips/errno.h143
-rw-r--r--include/asm-mips/global_data.h2
-rw-r--r--include/asm-mips/mipsregs.h1433
-rw-r--r--include/asm-nios/global_data.h2
-rw-r--r--include/asm-nios/io.h6
-rw-r--r--include/asm-nios2/global_data.h2
-rw-r--r--include/asm-ppc/4xx_pci.h2
-rw-r--r--include/asm-ppc/5xx_immap.h36
-rw-r--r--include/asm-ppc/bitops.h2
-rw-r--r--include/asm-ppc/e300.h122
-rw-r--r--include/asm-ppc/global_data.h2
-rw-r--r--include/asm-ppc/immap_85xx.h60
-rw-r--r--include/asm-ppc/immap_86xx.h6
-rw-r--r--include/asm-ppc/mmu.h11
-rw-r--r--include/asm-ppc/ppc4xx-intvec.h6
-rw-r--r--include/asm-ppc/ptrace.h2
-rw-r--r--include/asm-ppc/sigcontext.h2
-rw-r--r--include/asm-ppc/u-boot.h12
-rw-r--r--include/asm-sh/cpu_sh7750.h212
-rw-r--r--include/asm-sh/global_data.h2
-rw-r--r--include/asm-sh/ptrace.h2
-rw-r--r--include/asm-sh/system.h32
-rw-r--r--include/asm-sparc/global_data.h3
-rw-r--r--include/atmel_lcdc.h177
-rw-r--r--include/bcm5221.h2
-rw-r--r--include/bedbug/ppc.h2
-rw-r--r--include/bedbug/tables.h604
-rw-r--r--include/clps7111.h2
-rw-r--r--include/command.h2
-rw-r--r--include/common.h11
-rw-r--r--include/commproc.h26
-rw-r--r--include/config_cmd_all.h6
-rw-r--r--include/config_cmd_default.h2
-rw-r--r--include/configs/A3000.h22
-rw-r--r--include/configs/ADNPESC1.h6
-rw-r--r--include/configs/ADNPESC1_base_32.h4
-rw-r--r--include/configs/AMX860.h2
-rw-r--r--include/configs/APC405.h2
-rw-r--r--include/configs/AR405.h2
-rw-r--r--include/configs/ATUM8548.h6
-rw-r--r--include/configs/Adder.h10
-rw-r--r--include/configs/Alaska8220.h2
-rw-r--r--include/configs/B2.h2
-rw-r--r--include/configs/BC3450.h2
-rw-r--r--include/configs/CCM.h2
-rw-r--r--include/configs/CPCI750.h2
-rw-r--r--include/configs/CPU86.h6
-rw-r--r--include/configs/CRAYL1.h12
-rw-r--r--include/configs/CU824.h2
-rw-r--r--include/configs/DK1C20.h6
-rw-r--r--include/configs/DK1S10.h6
-rw-r--r--include/configs/DK1S10_mtx_ldk_20.h2
-rw-r--r--include/configs/DU440.h6
-rw-r--r--include/configs/EB+MCF-EV123.h10
-rw-r--r--include/configs/EP88x.h8
-rw-r--r--include/configs/ERIC.h2
-rw-r--r--include/configs/ETX094.h2
-rw-r--r--include/configs/EVB64260.h10
-rw-r--r--include/configs/EXBITGEN.h2
-rw-r--r--include/configs/FADS823.h8
-rw-r--r--include/configs/GEN860T.h86
-rw-r--r--include/configs/GENIETV.h20
-rw-r--r--include/configs/GTH.h4
-rw-r--r--include/configs/HH405.h2
-rw-r--r--include/configs/IAD210.h14
-rw-r--r--include/configs/ICU862.h8
-rw-r--r--include/configs/IPHASE4539.h2
-rw-r--r--include/configs/ISPAN.h2
-rw-r--r--include/configs/IVML24.h8
-rw-r--r--include/configs/IVMS8.h8
-rw-r--r--include/configs/IceCube.h6
-rw-r--r--include/configs/M5235EVB.h2
-rw-r--r--include/configs/M5271EVB.h2
-rw-r--r--include/configs/M5272C3.h2
-rw-r--r--include/configs/M5282EVB.h8
-rw-r--r--include/configs/M5329EVB.h2
-rw-r--r--include/configs/M5373EVB.h2
-rw-r--r--include/configs/M5475EVB.h2
-rw-r--r--include/configs/M5485EVB.h2
-rw-r--r--include/configs/MIP405.h16
-rw-r--r--include/configs/MOUSSE.h16
-rw-r--r--include/configs/MPC8313ERDB.h40
-rw-r--r--include/configs/MPC8315ERDB.h1
-rw-r--r--include/configs/MPC8323ERDB.h1
-rw-r--r--include/configs/MPC832XEMDS.h4
-rw-r--r--include/configs/MPC8349EMDS.h5
-rw-r--r--include/configs/MPC8349ITX.h27
-rw-r--r--include/configs/MPC8360EMDS.h2
-rw-r--r--include/configs/MPC8360ERDK.h10
-rw-r--r--include/configs/MPC837XEMDS.h1
-rw-r--r--include/configs/MPC837XERDB.h2
-rw-r--r--include/configs/MPC8540ADS.h22
-rw-r--r--include/configs/MPC8540EVAL.h38
-rw-r--r--include/configs/MPC8541CDS.h24
-rw-r--r--include/configs/MPC8555CDS.h24
-rw-r--r--include/configs/MPC8560ADS.h30
-rw-r--r--include/configs/MPC8568MDS.h34
-rw-r--r--include/configs/MPC8610HPCD.h3
-rw-r--r--include/configs/MPC8641HPCN.h253
-rw-r--r--include/configs/MPC86xADS.h2
-rw-r--r--include/configs/MUSENKI.h2
-rw-r--r--include/configs/MVBLUE.h44
-rw-r--r--include/configs/MVS1.h31
-rw-r--r--include/configs/NC650.h10
-rw-r--r--include/configs/NETPHONE.h26
-rw-r--r--include/configs/NETTA.h32
-rw-r--r--include/configs/NETTA2.h30
-rw-r--r--include/configs/NETVIA.h8
-rw-r--r--include/configs/NSCU.h4
-rw-r--r--include/configs/NX823.h2
-rw-r--r--include/configs/P3G4.h6
-rw-r--r--include/configs/PATI.h42
-rw-r--r--include/configs/PCI5441.h14
-rw-r--r--include/configs/PIP405.h4
-rw-r--r--include/configs/PM520.h4
-rw-r--r--include/configs/PM826.h6
-rw-r--r--include/configs/PM856.h22
-rw-r--r--include/configs/PN62.h14
-rw-r--r--include/configs/QS823.h4
-rw-r--r--include/configs/QS850.h4
-rw-r--r--include/configs/R360MPI.h6
-rw-r--r--include/configs/RBC823.h6
-rw-r--r--include/configs/RPXClassic.h8
-rw-r--r--include/configs/RPXlite.h10
-rw-r--r--include/configs/RRvision.h2
-rw-r--r--include/configs/Rattler.h14
-rw-r--r--include/configs/SBC8540.h2
-rw-r--r--include/configs/SCM.h8
-rw-r--r--include/configs/SL8245.h4
-rw-r--r--include/configs/SM850.h6
-rw-r--r--include/configs/SXNI855T.h4
-rw-r--r--include/configs/TB5200.h2
-rw-r--r--include/configs/TOP5200.h4
-rw-r--r--include/configs/TOP860.h10
-rw-r--r--include/configs/TQM5200.h2
-rw-r--r--include/configs/TQM834x.h6
-rw-r--r--include/configs/Total5200.h4
-rw-r--r--include/configs/VCMA9.h12
-rw-r--r--include/configs/VoVPN-GW.h2
-rw-r--r--include/configs/W7OLMC.h8
-rw-r--r--include/configs/W7OLMG.h8
-rw-r--r--include/configs/Yukon8220.h2
-rw-r--r--include/configs/ZPC1900.h14
-rw-r--r--include/configs/ads5121.h57
-rw-r--r--include/configs/adsvix.h2
-rw-r--r--include/configs/aev.h2
-rw-r--r--[-rwxr-xr-x]include/configs/apollon.h2
-rw-r--r--include/configs/armadillo.h6
-rw-r--r--include/configs/at91cap9adk.h37
-rw-r--r--include/configs/at91sam9260ek.h25
-rw-r--r--include/configs/at91sam9261ek.h202
-rw-r--r--include/configs/at91sam9263ek.h206
-rw-r--r--include/configs/at91sam9rlek.h175
-rw-r--r--include/configs/atc.h8
-rw-r--r--include/configs/atngw100.h26
-rw-r--r--include/configs/atstk1002.h19
-rw-r--r--include/configs/atstk1003.h15
-rw-r--r--include/configs/atstk1004.h16
-rw-r--r--include/configs/atstk1006.h203
-rw-r--r--include/configs/barco.h14
-rw-r--r--include/configs/bf533-stamp.h8
-rw-r--r--include/configs/bf537-stamp.h14
-rw-r--r--include/configs/bf561-ezkit.h17
-rw-r--r--include/configs/bubinga.h2
-rw-r--r--include/configs/c2mon.h6
-rw-r--r--include/configs/canmb.h6
-rw-r--r--include/configs/cerf250.h36
-rw-r--r--include/configs/cm5200.h2
-rw-r--r--include/configs/cmi_mpc5xx.h46
-rw-r--r--include/configs/cobra5272.h4
-rw-r--r--include/configs/cpci5200.h2
-rw-r--r--include/configs/csb226.h2
-rw-r--r--include/configs/csb272.h4
-rw-r--r--include/configs/csb472.h4
-rw-r--r--include/configs/davinci_dvevm.h6
-rw-r--r--include/configs/davinci_schmoogie.h2
-rw-r--r--include/configs/davinci_sonata.h6
-rw-r--r--include/configs/dnp1110.h2
-rw-r--r--include/configs/ep7312.h6
-rw-r--r--include/configs/ep8248.h14
-rw-r--r--include/configs/ep8260.h20
-rw-r--r--include/configs/ep82xxm.h16
-rw-r--r--include/configs/evb4510.h2
-rw-r--r--include/configs/gr_cpci_ax2000.h2
-rw-r--r--include/configs/gr_ep2s60.h4
-rw-r--r--include/configs/gr_xc3s_1500.h2
-rw-r--r--include/configs/grsim.h2
-rw-r--r--include/configs/grsim_leon2.h2
-rw-r--r--include/configs/hcu4.h4
-rw-r--r--include/configs/hcu5.h20
-rw-r--r--include/configs/hermes.h10
-rw-r--r--include/configs/hmi1001.h2
-rw-r--r--include/configs/idmr.h2
-rw-r--r--include/configs/impa7.h4
-rw-r--r--include/configs/imx31_litekit.h3
-rw-r--r--include/configs/inka4x0.h2
-rw-r--r--include/configs/innokom.h10
-rw-r--r--include/configs/integratorcp.h6
-rw-r--r--include/configs/ixdp425.h6
-rw-r--r--include/configs/ixdpg425.h6
-rw-r--r--include/configs/jupiter.h4
-rw-r--r--include/configs/kilauea.h2
-rw-r--r--include/configs/korat.h6
-rw-r--r--include/configs/lart.h2
-rw-r--r--include/configs/linkstation.h26
-rw-r--r--include/configs/logodl.h2
-rw-r--r--include/configs/lwmon5.h6
-rw-r--r--include/configs/makalu.h2
-rw-r--r--include/configs/mcc200.h2
-rw-r--r--include/configs/mcu25.h10
-rw-r--r--include/configs/mecp5200.h4
-rw-r--r--include/configs/mgcoge.h14
-rw-r--r--include/configs/modnet50.h3
-rw-r--r--include/configs/motionpro.h1
-rw-r--r--include/configs/mpc7448hpc2.h2
-rw-r--r--include/configs/ms7720se.h2
-rw-r--r--include/configs/ms7722se.h8
-rw-r--r--include/configs/ms7750se.h8
-rw-r--r--include/configs/munices.h1
-rw-r--r--include/configs/mx31ads.h3
-rw-r--r--include/configs/netstar.h8
-rw-r--r--include/configs/ns9750dev.h4
-rw-r--r--include/configs/o2dnt.h2
-rw-r--r--include/configs/p3mx.h5
-rw-r--r--include/configs/pcu_e.h4
-rw-r--r--include/configs/pdnb3.h4
-rw-r--r--include/configs/pf5200.h1
-rw-r--r--include/configs/ppmc8260.h2
-rw-r--r--include/configs/quad100hd.h298
-rw-r--r--include/configs/r7780mp.h2
-rw-r--r--include/configs/rmu.h8
-rw-r--r--include/configs/rsdproto.h14
-rw-r--r--include/configs/sacsng.h2
-rw-r--r--include/configs/sbc2410x.h6
-rw-r--r--include/configs/sbc8260.h2
-rw-r--r--include/configs/sbc8349.h2
-rw-r--r--include/configs/sbc8548.h2
-rw-r--r--include/configs/sbc8641d.h24
-rw-r--r--include/configs/sc520_cdp.h2
-rw-r--r--include/configs/sc520_spunk.h8
-rw-r--r--include/configs/sequoia.h6
-rw-r--r--include/configs/shannon.h2
-rw-r--r--include/configs/smdk2400.h8
-rw-r--r--include/configs/smdk2410.h2
-rw-r--r--include/configs/smmaco4.h2
-rw-r--r--include/configs/socrates.h423
-rw-r--r--include/configs/sorcery.h12
-rw-r--r--include/configs/spieval.h2
-rw-r--r--include/configs/stxgp3.h60
-rw-r--r--include/configs/stxssa.h16
-rw-r--r--include/configs/stxxtc.h18
-rw-r--r--include/configs/svm_sc8xx.h10
-rw-r--r--include/configs/taihu.h2
-rw-r--r--include/configs/trab.h6
-rw-r--r--include/configs/trizepsiv.h6
-rw-r--r--include/configs/uc100.h2
-rw-r--r--include/configs/uc101.h2
-rw-r--r--include/configs/utx8245.h6
-rw-r--r--include/configs/v37.h10
-rw-r--r--include/configs/v38b.h2
-rw-r--r--include/configs/versatile.h2
-rw-r--r--include/configs/wepep250.h6
-rw-r--r--include/configs/xaeniax.h2
-rw-r--r--include/configs/xupv2p.h10
-rw-r--r--include/div64.h8
-rw-r--r--include/dm9161.h4
-rw-r--r--include/elf.h8
-rw-r--r--include/fat.h2
-rw-r--r--include/flash.h4
-rw-r--r--include/fpga.h42
-rw-r--r--include/galileo/gt64260R.h2012
-rw-r--r--include/i2c.h8
-rw-r--r--include/lcd.h30
-rw-r--r--include/libfdt.h22
-rw-r--r--include/linux/mtd/bbm.h4
-rw-r--r--include/linux/mtd/doc2000.h70
-rw-r--r--include/linux/mtd/mtd-abi.h4
-rw-r--r--include/linux/mtd/mtd.h4
-rw-r--r--include/linux/mtd/nand.h4
-rw-r--r--include/linux/mtd/nand_legacy.h10
-rw-r--r--include/linux/mtd/nftl.h6
-rw-r--r--include/lists.h4
-rw-r--r--include/logbuff.h3
-rw-r--r--include/lxt971a.h128
-rw-r--r--include/mpc106.h12
-rw-r--r--include/net.h18
-rw-r--r--include/nios2-epcs.h2
-rw-r--r--include/nios2-io.h6
-rw-r--r--include/ns7520_eth.h8
-rw-r--r--include/ns9750_bbus.h22
-rw-r--r--include/ns9750_eth.h268
-rw-r--r--include/ns9750_mem.h46
-rw-r--r--include/ns9750_ser.h26
-rw-r--r--include/ns9750_sys.h38
-rw-r--r--include/onenand_uboot.h5
-rw-r--r--include/pc_keyb.h12
-rw-r--r--include/post.h4
-rw-r--r--include/ppc405.h1726
-rw-r--r--include/ppc440.h2
-rw-r--r--include/ppc4xx_enet.h4
-rw-r--r--include/rtc.h2
-rw-r--r--include/s_record.h6
-rw-r--r--include/scsi.h6
-rw-r--r--include/sed13806.h2
-rw-r--r--include/spartan2.h16
-rw-r--r--include/spartan3.h22
-rw-r--r--include/spi.h150
-rw-r--r--include/spi_flash.h70
-rw-r--r--include/sym53c8xx.h8
-rw-r--r--include/usbdcore_mpc8xx.h2
-rw-r--r--include/video_easylogo.h2
-rw-r--r--include/video_logo.h6
-rw-r--r--include/virtex2.h6
-rw-r--r--include/xilinx.h68
365 files changed, 10562 insertions, 6892 deletions
diff --git a/include/ACEX1K.h b/include/ACEX1K.h
index f249d64..354e0f0 100644
--- a/include/ACEX1K.h
+++ b/include/ACEX1K.h
@@ -73,10 +73,12 @@ typedef struct {
* Filesize of an *.rbf file is 166965 Bytes
*/
#if 0
-#define Altera_EP1K100_SIZE 1337000/8 /* 167125 Bytes */
+#define Altera_EP1K100_SIZE 1337000/8 /* 167125 Bytes */
#endif
-#define Altera_EP1K100_SIZE (166965*8)
+#define Altera_EP1K100_SIZE (166965*8)
+#define Altera_EP2C8_SIZE 247942
+#define Altera_EP2C20_SIZE 586562
#define Altera_EP2C35_SIZE 883905
/* Descriptor Macros
diff --git a/include/SA-1100.h b/include/SA-1100.h
index 9985783..7589df2 100644
--- a/include/SA-1100.h
+++ b/include/SA-1100.h
@@ -1,20 +1,20 @@
/*
- * FILE SA-1100.h
+ * FILE SA-1100.h
*
- * Version 1.2
- * Author Copyright (c) Marc A. Viredaz, 1998
- * DEC Western Research Laboratory, Palo Alto, CA
- * Date January 1998 (April 1997)
- * System StrongARM SA-1100
+ * Version 1.2
+ * Author Copyright (c) Marc A. Viredaz, 1998
+ * DEC Western Research Laboratory, Palo Alto, CA
+ * Date January 1998 (April 1997)
+ * System StrongARM SA-1100
* Language C or ARM Assembly
- * Purpose Definition of constants related to the StrongARM
- * SA-1100 microprocessor (Advanced RISC Machine (ARM)
- * architecture version 4). This file is based on the
- * StrongARM SA-1100 data sheet version 2.2.
+ * Purpose Definition of constants related to the StrongARM
+ * SA-1100 microprocessor (Advanced RISC Machine (ARM)
+ * architecture version 4). This file is based on the
+ * StrongARM SA-1100 data sheet version 2.2.
*
- * Language-specific definitions are selected by the
- * macro "LANGUAGE", which should be defined as either
- * "C" (default) or "Assembly".
+ * Language-specific definitions are selected by the
+ * macro "LANGUAGE", which should be defined as either
+ * "C" (default) or "Assembly".
*/
@@ -32,17 +32,17 @@
#include <asm/arch-sa1100/bitfield.h>
-#define C 0
+#define C 0
#define Assembly 1
#if LANGUAGE == C
-typedef unsigned short Word16 ;
-typedef unsigned int Word32 ;
-typedef Word32 Word ;
-typedef Word Quad [4] ;
-typedef void *Address ;
-typedef void (*ExcpHndlr) (void) ;
+typedef unsigned short Word16 ;
+typedef unsigned int Word32 ;
+typedef Word32 Word ;
+typedef Word Quad [4] ;
+typedef void *Address ;
+typedef void (*ExcpHndlr) (void) ;
#endif /* LANGUAGE == C */
@@ -50,65 +50,65 @@ typedef void (*ExcpHndlr) (void) ;
* Memory
*/
-#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */
+#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */
#define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */
-#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */
- /* [byte] */
-#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */
- /* [byte] */
-#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */
- /* [byte] */
-#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */
- /* [byte] */
-
-#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */
-#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */
-#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */
-#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */
-#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */
+#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */
+ /* [byte] */
+#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */
+ /* [byte] */
+#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */
+ /* [byte] */
+#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */
+ /* [byte] */
+
+#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */
+#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */
+#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */
+#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */
+#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */
#define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */
-#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \
+#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \
(0x00000000 + (Nb)*StMemBnkSp)
-#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */
-#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */
-#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */
-#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */
+#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */
+#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */
+#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */
+#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */
#if LANGUAGE == C
-typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
-#define StMemBnk /* Static Memory Bank [0..3] */ \
+typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
+#define StMemBnk /* Static Memory Bank [0..3] */ \
((StMemBnkType *) io_p2v (_StMemBnk (0)))
-#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */
-#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */
-#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */
-#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */
+#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */
+#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */
+#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */
+#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */
#endif /* LANGUAGE == C */
-#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \
+#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \
(0xC0000000 + (Nb)*DRAMBnkSp)
-#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */
-#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */
-#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */
-#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */
+#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */
+#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */
+#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */
+#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */
#if LANGUAGE == C
-typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
-#define DRAMBnk /* DRAM Bank [0..3] */ \
+typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
+#define DRAMBnk /* DRAM Bank [0..3] */ \
((DRAMBnkType *) io_p2v (_DRAMBnk (0)))
-#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */
-#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */
-#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */
-#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */
+#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */
+#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */
+#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */
+#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */
#endif /* LANGUAGE == C */
-#define _ZeroMem 0xE0000000 /* Zero Memory bank */
+#define _ZeroMem 0xE0000000 /* Zero Memory bank */
#if LANGUAGE == C
-typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
-#define ZeroMem /* Zero Memory bank */ \
+typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
+#define ZeroMem /* Zero Memory bank */ \
(*((ZeroMemType *) io_p2v (_ZeroMem)))
#endif /* LANGUAGE == C */
@@ -118,60 +118,60 @@ typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
*/
#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
-#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
-#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
+#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
+#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
-#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
+#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
-#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
-#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
+#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
+#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
-#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
-#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
+#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
+#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
-#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
+#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
(0x20000000 + (Nb)*PCMCIASp)
-#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
-#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
+#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
+#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
-#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
+#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
-#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
-#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
-#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
-#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
+#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
+#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
+#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
+#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
-#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
-#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
-#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
-#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
+#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
+#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
+#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
+#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
#if LANGUAGE == C
-typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
+typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
-#define PCMCIA0 /* PCMCIA 0 */ \
+#define PCMCIA0 /* PCMCIA 0 */ \
(*((PCMCIAType *) io_p2v (_PCMCIA0)))
-#define PCMCIA0IO /* PCMCIA 0 I/O */ \
+#define PCMCIA0IO /* PCMCIA 0 I/O */ \
(*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO)))
-#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \
+#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \
(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr)))
-#define PCMCIA0Mem /* PCMCIA 0 Memory */ \
+#define PCMCIA0Mem /* PCMCIA 0 Memory */ \
(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem)))
-#define PCMCIA1 /* PCMCIA 1 */ \
+#define PCMCIA1 /* PCMCIA 1 */ \
(*((PCMCIAType *) io_p2v (_PCMCIA1)))
-#define PCMCIA1IO /* PCMCIA 1 I/O */ \
+#define PCMCIA1IO /* PCMCIA 1 I/O */ \
(*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO)))
-#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \
+#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \
(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr)))
-#define PCMCIA1Mem /* PCMCIA 1 Memory */ \
+#define PCMCIA1Mem /* PCMCIA 1 Memory */ \
(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem)))
#endif /* LANGUAGE == C */
@@ -181,254 +181,254 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
* Universal Serial Bus (USB) Device Controller (UDC) control registers
*
* Registers
- * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Control Register (read/write).
- * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Address Register (read/write).
+ * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
+ * Controller (UDC) Control Register (read/write).
+ * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
+ * Controller (UDC) Address Register (read/write).
* Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Output Maximum Packet size register
- * (read/write).
+ * Controller (UDC) Output Maximum Packet size register
+ * (read/write).
* Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Input Maximum Packet size register
- * (read/write).
+ * Controller (UDC) Input Maximum Packet size register
+ * (read/write).
* Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Control/Status register end-point 0
- * (read/write).
+ * Controller (UDC) Control/Status register end-point 0
+ * (read/write).
* Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Control/Status register end-point 1
- * (output, read/write).
+ * Controller (UDC) Control/Status register end-point 1
+ * (output, read/write).
* Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Control/Status register end-point 2
- * (input, read/write).
- * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Data register end-point 0
- * (read/write).
- * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Write Count register end-point 0
- * (read).
- * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Data Register (read/write).
- * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device
- * Controller (UDC) Status Register (read/write).
+ * Controller (UDC) Control/Status register end-point 2
+ * (input, read/write).
+ * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device
+ * Controller (UDC) Data register end-point 0
+ * (read/write).
+ * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device
+ * Controller (UDC) Write Count register end-point 0
+ * (read).
+ * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device
+ * Controller (UDC) Data Register (read/write).
+ * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device
+ * Controller (UDC) Status Register (read/write).
*/
#define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */
#define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */
#define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */
- /* Packet size reg. */
+ /* Packet size reg. */
#define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */
- /* Packet size reg. */
+ /* Packet size reg. */
#define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */
- /* reg. end-point 0 */
+ /* reg. end-point 0 */
#define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */
- /* reg. end-point 1 (output) */
+ /* reg. end-point 1 (output) */
#define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */
- /* reg. end-point 2 (input) */
-#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */
- /* end-point 0 */
-#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */
- /* reg. end-point 0 */
-#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */
-#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */
+ /* reg. end-point 2 (input) */
+#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */
+ /* end-point 0 */
+#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */
+ /* reg. end-point 0 */
+#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */
+#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */
#if LANGUAGE == C
-#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \
+#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \
(*((volatile Word *) io_p2v (_Ser0UDCCR)))
-#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \
+#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \
(*((volatile Word *) io_p2v (_Ser0UDCAR)))
-#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \
- /* Packet size reg. */ \
+#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \
+ /* Packet size reg. */ \
(*((volatile Word *) io_p2v (_Ser0UDCOMP)))
-#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \
- /* Packet size reg. */ \
+#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \
+ /* Packet size reg. */ \
(*((volatile Word *) io_p2v (_Ser0UDCIMP)))
-#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \
- /* reg. end-point 0 */ \
+#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \
+ /* reg. end-point 0 */ \
(*((volatile Word *) io_p2v (_Ser0UDCCS0)))
-#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \
- /* reg. end-point 1 (output) */ \
+#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \
+ /* reg. end-point 1 (output) */ \
(*((volatile Word *) io_p2v (_Ser0UDCCS1)))
-#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \
- /* reg. end-point 2 (input) */ \
+#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \
+ /* reg. end-point 2 (input) */ \
(*((volatile Word *) io_p2v (_Ser0UDCCS2)))
-#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \
- /* end-point 0 */ \
+#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \
+ /* end-point 0 */ \
(*((volatile Word *) io_p2v (_Ser0UDCD0)))
-#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \
- /* reg. end-point 0 */ \
+#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \
+ /* reg. end-point 0 */ \
(*((volatile Word *) io_p2v (_Ser0UDCWC)))
-#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \
+#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser0UDCDR)))
-#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \
+#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \
(*((volatile Word *) io_p2v (_Ser0UDCSR)))
#endif /* LANGUAGE == C */
-#define UDCCR_UDD 0x00000001 /* UDC Disable */
-#define UDCCR_UDA 0x00000002 /* UDC Active (read) */
+#define UDCCR_UDD 0x00000001 /* UDC Disable */
+#define UDCCR_UDA 0x00000002 /* UDC Active (read) */
#define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */
-#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
- /* (disable) */
-#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */
- /* (disable) */
-#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */
- /* (disable) */
+#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
+ /* (disable) */
+#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */
+ /* (disable) */
+#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */
+ /* (disable) */
#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */
- /* (disable) */
+ /* (disable) */
#define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */
#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */
-#define UDCAR_ADD Fld (7, 0) /* function ADDress */
+#define UDCAR_ADD Fld (7, 0) /* function ADDress */
#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
- /* [byte] */
-#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \
- /* [1..256 byte] */ \
+ /* [byte] */
+#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \
+ /* [1..256 byte] */ \
(((Size) - 1) << FShft (UDCOMP_OUTMAXP))
#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
- /* [byte] */
-#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \
- /* [1..256 byte] */ \
+ /* [byte] */
+#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \
+ /* [1..256 byte] */ \
(((Size) - 1) << FShft (UDCIMP_INMAXP))
-#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
-#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */
-#define UDCCS0_SST 0x00000004 /* Sent STall */
-#define UDCCS0_FST 0x00000008 /* Force STall */
-#define UDCCS0_DE 0x00000010 /* Data End */
-#define UDCCS0_SE 0x00000020 /* Setup End (read) */
+#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
+#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */
+#define UDCCS0_SST 0x00000004 /* Sent STall */
+#define UDCCS0_FST 0x00000008 /* Force STall */
+#define UDCCS0_DE 0x00000010 /* Data End */
+#define UDCCS0_SE 0x00000020 /* Setup End (read) */
#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */
- /* (write) */
-#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */
+ /* (write) */
+#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */
#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
- /* Service request (read) */
-#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */
-#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
-#define UDCCS1_SST 0x00000008 /* Sent STall */
-#define UDCCS1_FST 0x00000010 /* Force STall */
+ /* Service request (read) */
+#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */
+#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
+#define UDCCS1_SST 0x00000008 /* Sent STall */
+#define UDCCS1_FST 0x00000010 /* Force STall */
#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
- /* Service request (read) */
-#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */
+ /* Service request (read) */
+#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */
#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
-#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
-#define UDCCS2_SST 0x00000010 /* Sent STall */
-#define UDCCS2_FST 0x00000020 /* Force STall */
+#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
+#define UDCCS2_SST 0x00000010 /* Sent STall */
+#define UDCCS2_FST 0x00000020 /* Force STall */
-#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
+#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
-#define UDCWC_WC Fld (4, 0) /* Write Count */
+#define UDCWC_WC Fld (4, 0) /* Write Count */
-#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
+#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
-#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */
-#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */
-#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */
-#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */
-#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */
+#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */
+#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */
+#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */
+#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */
+#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */
/*
* Universal Asynchronous Receiver/Transmitter (UART) control registers
*
* Registers
- * Ser1UTCR0 Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 0
- * (read/write).
- * Ser1UTCR1 Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 1
- * (read/write).
- * Ser1UTCR2 Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 2
- * (read/write).
- * Ser1UTCR3 Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 3
- * (read/write).
- * Ser1UTDR Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Data Register
- * (read/write).
- * Ser1UTSR0 Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Status Register 0
- * (read/write).
- * Ser1UTSR1 Serial port 1 Universal Asynchronous
- * Receiver/Transmitter (UART) Status Register 1 (read).
+ * Ser1UTCR0 Serial port 1 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 0
+ * (read/write).
+ * Ser1UTCR1 Serial port 1 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 1
+ * (read/write).
+ * Ser1UTCR2 Serial port 1 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 2
+ * (read/write).
+ * Ser1UTCR3 Serial port 1 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 3
+ * (read/write).
+ * Ser1UTDR Serial port 1 Universal Asynchronous
+ * Receiver/Transmitter (UART) Data Register
+ * (read/write).
+ * Ser1UTSR0 Serial port 1 Universal Asynchronous
+ * Receiver/Transmitter (UART) Status Register 0
+ * (read/write).
+ * Ser1UTSR1 Serial port 1 Universal Asynchronous
+ * Receiver/Transmitter (UART) Status Register 1 (read).
*
- * Ser2UTCR0 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 0
- * (read/write).
- * Ser2UTCR1 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 1
- * (read/write).
- * Ser2UTCR2 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 2
- * (read/write).
- * Ser2UTCR3 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 3
- * (read/write).
- * Ser2UTCR4 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 4
- * (read/write).
- * Ser2UTDR Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Data Register
- * (read/write).
- * Ser2UTSR0 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Status Register 0
- * (read/write).
- * Ser2UTSR1 Serial port 2 Universal Asynchronous
- * Receiver/Transmitter (UART) Status Register 1 (read).
+ * Ser2UTCR0 Serial port 2 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 0
+ * (read/write).
+ * Ser2UTCR1 Serial port 2 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 1
+ * (read/write).
+ * Ser2UTCR2 Serial port 2 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 2
+ * (read/write).
+ * Ser2UTCR3 Serial port 2 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 3
+ * (read/write).
+ * Ser2UTCR4 Serial port 2 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 4
+ * (read/write).
+ * Ser2UTDR Serial port 2 Universal Asynchronous
+ * Receiver/Transmitter (UART) Data Register
+ * (read/write).
+ * Ser2UTSR0 Serial port 2 Universal Asynchronous
+ * Receiver/Transmitter (UART) Status Register 0
+ * (read/write).
+ * Ser2UTSR1 Serial port 2 Universal Asynchronous
+ * Receiver/Transmitter (UART) Status Register 1 (read).
*
- * Ser3UTCR0 Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 0
- * (read/write).
- * Ser3UTCR1 Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 1
- * (read/write).
- * Ser3UTCR2 Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 2
- * (read/write).
- * Ser3UTCR3 Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Control Register 3
- * (read/write).
- * Ser3UTDR Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Data Register
- * (read/write).
- * Ser3UTSR0 Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Status Register 0
- * (read/write).
- * Ser3UTSR1 Serial port 3 Universal Asynchronous
- * Receiver/Transmitter (UART) Status Register 1 (read).
+ * Ser3UTCR0 Serial port 3 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 0
+ * (read/write).
+ * Ser3UTCR1 Serial port 3 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 1
+ * (read/write).
+ * Ser3UTCR2 Serial port 3 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 2
+ * (read/write).
+ * Ser3UTCR3 Serial port 3 Universal Asynchronous
+ * Receiver/Transmitter (UART) Control Register 3
+ * (read/write).
+ * Ser3UTDR Serial port 3 Universal Asynchronous
+ * Receiver/Transmitter (UART) Data Register
+ * (read/write).
+ * Ser3UTSR0 Serial port 3 Universal Asynchronous
+ * Receiver/Transmitter (UART) Status Register 0
+ * (read/write).
+ * Ser3UTSR1 Serial port 3 Universal Asynchronous
+ * Receiver/Transmitter (UART) Status Register 1 (read).
*
* Clocks
* fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
- * or 3.5795 MHz).
- * fua, Tua Frequency, period of the UART communication.
+ * or 3.5795 MHz).
+ * fua, Tua Frequency, period of the UART communication.
*/
-#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \
+#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \
(0x80010000 + ((Nb) - 1)*0x00020000)
-#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \
+#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \
(0x80010004 + ((Nb) - 1)*0x00020000)
-#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \
+#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \
(0x80010008 + ((Nb) - 1)*0x00020000)
-#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \
+#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \
(0x8001000C + ((Nb) - 1)*0x00020000)
-#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \
+#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \
(0x80010010 + ((Nb) - 1)*0x00020000)
-#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \
+#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \
(0x80010014 + ((Nb) - 1)*0x00020000)
-#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \
+#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \
(0x8001001C + ((Nb) - 1)*0x00020000)
-#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \
+#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \
(0x80010020 + ((Nb) - 1)*0x00020000)
#define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
#define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
#define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
#define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
-#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
+#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
#define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
#define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
@@ -437,7 +437,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
#define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */
#define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */
#define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */
-#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */
+#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */
#define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */
#define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
@@ -445,57 +445,57 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
#define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
#define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */
#define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */
-#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */
+#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */
#define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */
#define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
#if LANGUAGE == C
-#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \
+#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser1UTCR0)))
-#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \
+#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser1UTCR1)))
-#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \
+#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \
(*((volatile Word *) io_p2v (_Ser1UTCR2)))
-#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \
+#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \
(*((volatile Word *) io_p2v (_Ser1UTCR3)))
-#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \
+#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser1UTDR)))
-#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \
+#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser1UTSR0)))
-#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \
+#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser1UTSR1)))
-#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \
+#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser2UTCR0)))
-#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \
+#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser2UTCR1)))
-#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \
+#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \
(*((volatile Word *) io_p2v (_Ser2UTCR2)))
-#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \
+#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \
(*((volatile Word *) io_p2v (_Ser2UTCR3)))
-#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \
+#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \
(*((volatile Word *) io_p2v (_Ser2UTCR4)))
-#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \
+#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser2UTDR)))
-#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \
+#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser2UTSR0)))
-#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \
+#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser2UTSR1)))
-#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \
+#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser3UTCR0)))
-#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \
+#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser3UTCR1)))
-#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \
+#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \
(*((volatile Word *) io_p2v (_Ser3UTCR2)))
-#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \
+#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \
(*((volatile Word *) io_p2v (_Ser3UTCR3)))
-#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \
+#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser3UTDR)))
-#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \
+#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser3UTSR0)))
-#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \
+#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser3UTSR1)))
#elif LANGUAGE == Assembly
@@ -526,89 +526,89 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
#endif /* LANGUAGE == C */
-#define UTCR0_PE 0x00000001 /* Parity Enable */
-#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */
-#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */
-#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */
-#define UTCR0_SBS 0x00000004 /* Stop Bit Select */
-#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
-#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */
-#define UTCR0_DSS 0x00000008 /* Data Size Select */
-#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
-#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
-#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
- /* (ser. port 1: GPIO [18], */
- /* ser. port 3: GPIO [20]) */
-#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */
-#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
-#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
-#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */
-#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
+#define UTCR0_PE 0x00000001 /* Parity Enable */
+#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */
+#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */
+#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */
+#define UTCR0_SBS 0x00000004 /* Stop Bit Select */
+#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
+#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */
+#define UTCR0_DSS 0x00000008 /* Data Size Select */
+#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
+#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
+#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
+ /* (ser. port 1: GPIO [18], */
+ /* ser. port 3: GPIO [20]) */
+#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */
+#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
+#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
+#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */
+#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
#define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
-#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \
+#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \
(UTCR0_1StpBit + UTCR0_8BitData)
#define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
#define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
/* fua = fxtl/(16*(BRD[11:0] + 1)) */
/* Tua = 16*(BRD [11:0] + 1)*Txtl */
-#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
+#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
(((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
FShft (UTCR1_BRD))
-#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
+#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
(((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
FShft (UTCR2_BRD))
/* fua = fxtl/(16*Floor (Div/16)) */
/* Tua = 16*Floor (Div/16)*Txtl */
-#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
+#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
(((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
FShft (UTCR1_BRD))
-#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
+#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
(((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
FShft (UTCR2_BRD))
/* fua = fxtl/(16*Ceil (Div/16)) */
/* Tua = 16*Ceil (Div/16)*Txtl */
-#define UTCR3_RXE 0x00000001 /* Receive Enable */
-#define UTCR3_TXE 0x00000002 /* Transmit Enable */
-#define UTCR3_BRK 0x00000004 /* BReaK mode */
+#define UTCR3_RXE 0x00000001 /* Receive Enable */
+#define UTCR3_TXE 0x00000002 /* Transmit Enable */
+#define UTCR3_BRK 0x00000004 /* BReaK mode */
#define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
- /* more Interrupt Enable */
+ /* more Interrupt Enable */
#define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
- /* Interrupt Enable */
-#define UTCR3_LBM 0x00000020 /* Look-Back Mode */
-#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \
+ /* Interrupt Enable */
+#define UTCR3_LBM 0x00000020 /* Look-Back Mode */
+#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \
/* TIE, LBM can be set or cleared) */ \
(UTCR3_RXE + UTCR3_TXE)
#define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
- /* (HP-SIR) modulation Enable */
+ /* (HP-SIR) modulation Enable */
#define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
-#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
-#define UTCR4_LPM 0x00000002 /* Low-Power Mode */
-#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */
-#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
+#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
+#define UTCR4_LPM 0x00000002 /* Low-Power Mode */
+#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */
+#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
-#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
-#if 0 /* Hidden receive FIFO bits */
+#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
+#if 0 /* Hidden receive FIFO bits */
#define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
#define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
#define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
#endif /* 0 */
#define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
- /* Service request (read) */
+ /* Service request (read) */
#define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
- /* more Service request (read) */
-#define UTSR0_RID 0x00000004 /* Receiver IDle */
-#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */
-#define UTSR0_REB 0x00000010 /* Receive End of Break */
-#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
+ /* more Service request (read) */
+#define UTSR0_RID 0x00000004 /* Receiver IDle */
+#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */
+#define UTSR0_REB 0x00000010 /* Receive End of Break */
+#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
-#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
+#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
#define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
-#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
+#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
#define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
#define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
@@ -617,27 +617,27 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
* Synchronous Data Link Controller (SDLC) control registers
*
* Registers
- * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Control Register 0 (read/write).
- * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Control Register 1 (read/write).
- * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Control Register 2 (read/write).
- * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Control Register 3 (read/write).
- * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Control Register 4 (read/write).
- * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC)
- * Data Register (read/write).
- * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Status Register 0 (read/write).
- * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC)
- * Status Register 1 (read/write).
+ * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC)
+ * Control Register 0 (read/write).
+ * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC)
+ * Control Register 1 (read/write).
+ * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC)
+ * Control Register 2 (read/write).
+ * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC)
+ * Control Register 3 (read/write).
+ * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC)
+ * Control Register 4 (read/write).
+ * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC)
+ * Data Register (read/write).
+ * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC)
+ * Status Register 0 (read/write).
+ * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC)
+ * Status Register 1 (read/write).
*
* Clocks
* fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
- * or 3.5795 MHz).
- * fsd, Tsd Frequency, period of the SDLC communication.
+ * or 3.5795 MHz).
+ * fsd, Tsd Frequency, period of the SDLC communication.
*/
#define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */
@@ -645,110 +645,110 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
#define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */
#define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */
#define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */
-#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */
+#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */
#define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */
#define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */
#if LANGUAGE == C
-#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \
+#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser1SDCR0)))
-#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \
+#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser1SDCR1)))
-#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \
+#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \
(*((volatile Word *) io_p2v (_Ser1SDCR2)))
-#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \
+#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \
(*((volatile Word *) io_p2v (_Ser1SDCR3)))
-#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \
+#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \
(*((volatile Word *) io_p2v (_Ser1SDCR4)))
-#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \
+#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser1SDDR)))
-#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \
+#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser1SDSR0)))
-#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \
+#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser1SDSR1)))
#endif /* LANGUAGE == C */
-#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */
-#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */
-#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */
+#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */
+#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */
+#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */
#define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */
-#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */
-#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */
-#define SDCR0_LBM 0x00000004 /* Look-Back Mode */
-#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */
-#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */
+#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */
+#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */
+#define SDCR0_LBM 0x00000004 /* Look-Back Mode */
+#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */
+#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */
#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */
- /* (GPIO [16]) */
-#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
-#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
-#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
-#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
-#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
-#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
-#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
+ /* (GPIO [16]) */
+#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
+#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
+#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
+#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
+#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
+#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
+#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
-#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
- /* (GPIO [17]) */
-#define SDCR1_TXE 0x00000002 /* Transmit Enable */
-#define SDCR1_RXE 0x00000004 /* Receive Enable */
+#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
+ /* (GPIO [17]) */
+#define SDCR1_TXE 0x00000002 /* Transmit Enable */
+#define SDCR1_RXE 0x00000004 /* Receive Enable */
#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
- /* more Interrupt Enable */
+ /* more Interrupt Enable */
#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
- /* Interrupt Enable */
-#define SDCR1_AME 0x00000020 /* Address Match Enable */
+ /* Interrupt Enable */
+#define SDCR1_AME 0x00000020 /* Address Match Enable */
#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
-#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
-#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
+#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
+#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */
-#define SDCR2_AMV Fld (8, 0) /* Address Match Value */
+#define SDCR2_AMV Fld (8, 0) /* Address Match Value */
#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
/* fsd = fxtl/(16*(BRD[11:0] + 1)) */
/* Tsd = 16*(BRD[11:0] + 1)*Txtl */
-#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
+#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
(((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
FShft (SDCR3_BRD))
-#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
+#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
(((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
FShft (SDCR4_BRD))
/* fsd = fxtl/(16*Floor (Div/16)) */
/* Tsd = 16*Floor (Div/16)*Txtl */
-#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
+#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
(((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
FShft (SDCR3_BRD))
-#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
+#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
(((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
FShft (SDCR4_BRD))
/* fsd = fxtl/(16*Ceil (Div/16)) */
/* Tsd = 16*Ceil (Div/16)*Txtl */
-#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
-#if 0 /* Hidden receive FIFO bits */
+#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
+#if 0 /* Hidden receive FIFO bits */
#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
-#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
+#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
#endif /* 0 */
-#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
-#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
-#define SDSR0_RAB 0x00000004 /* Receive ABort */
+#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
+#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
+#define SDSR0_RAB 0x00000004 /* Receive ABort */
#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
- /* Service request (read) */
+ /* Service request (read) */
#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
- /* more Service request (read) */
+ /* more Service request (read) */
#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
-#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
+#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
-#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */
-#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
-#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
+#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */
+#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
+#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
@@ -756,159 +756,159 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
* High-Speed Serial to Parallel controller (HSSP) control registers
*
* Registers
- * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
- * controller (HSSP) Control Register 0 (read/write).
- * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
- * controller (HSSP) Control Register 1 (read/write).
- * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
- * controller (HSSP) Data Register (read/write).
- * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
- * controller (HSSP) Status Register 0 (read/write).
- * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
- * controller (HSSP) Status Register 1 (read).
- * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
- * controller (HSSP) Control Register 2 (read/write).
- * [The HSCR2 register is only implemented in
- * versions 2.0 (rev. = 8) and higher of the StrongARM
- * SA-1100.]
+ * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
+ * controller (HSSP) Control Register 0 (read/write).
+ * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
+ * controller (HSSP) Control Register 1 (read/write).
+ * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
+ * controller (HSSP) Data Register (read/write).
+ * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
+ * controller (HSSP) Status Register 0 (read/write).
+ * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
+ * controller (HSSP) Status Register 1 (read).
+ * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
+ * controller (HSSP) Control Register 2 (read/write).
+ * [The HSCR2 register is only implemented in
+ * versions 2.0 (rev. = 8) and higher of the StrongARM
+ * SA-1100.]
*/
#define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */
#define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */
-#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */
+#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */
#define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */
#define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */
#define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */
#if LANGUAGE == C
-#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \
+#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser2HSCR0)))
-#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \
+#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser2HSCR1)))
-#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \
+#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser2HSDR)))
-#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \
+#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser2HSSR0)))
-#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \
+#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser2HSSR1)))
-#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \
+#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \
(*((volatile Word *) io_p2v (_Ser2HSCR2)))
#endif /* LANGUAGE == C */
-#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
+#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
-#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
-#define HSCR0_LBM 0x00000002 /* Look-Back Mode */
+#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
+#define HSCR0_LBM 0x00000002 /* Look-Back Mode */
#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
-#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
-#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
-#define HSCR0_TXE 0x00000008 /* Transmit Enable */
-#define HSCR0_RXE 0x00000010 /* Receive Enable */
+#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
+#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
+#define HSCR0_TXE 0x00000008 /* Transmit Enable */
+#define HSCR0_RXE 0x00000010 /* Receive Enable */
#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
- /* more Interrupt Enable */
+ /* more Interrupt Enable */
#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
- /* Interrupt Enable */
-#define HSCR0_AME 0x00000080 /* Address Match Enable */
+ /* Interrupt Enable */
+#define HSCR0_AME 0x00000080 /* Address Match Enable */
-#define HSCR1_AMV Fld (8, 0) /* Address Match Value */
+#define HSCR1_AMV Fld (8, 0) /* Address Match Value */
-#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
-#if 0 /* Hidden receive FIFO bits */
+#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
+#if 0 /* Hidden receive FIFO bits */
#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
-#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
+#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
#endif /* 0 */
-#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
-#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
-#define HSSR0_RAB 0x00000004 /* Receive ABort */
+#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
+#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
+#define HSSR0_RAB 0x00000004 /* Receive ABort */
#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
- /* Service request (read) */
+ /* Service request (read) */
#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
- /* more Service request (read) */
-#define HSSR0_FRE 0x00000020 /* receive FRaming Error */
+ /* more Service request (read) */
+#define HSSR0_FRE 0x00000020 /* receive FRaming Error */
#define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
-#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
+#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
#define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
#define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
-#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
-#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
+#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
+#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
#define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
#define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */
-#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */
- /* (inverted) */
-#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */
- /* (non-inverted) */
+#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */
+ /* (inverted) */
+#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */
+ /* (non-inverted) */
#define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */
-#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */
- /* (inverted) */
-#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */
- /* (non-inverted) */
+#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */
+ /* (inverted) */
+#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */
+ /* (non-inverted) */
/*
* Multi-media Communications Port (MCP) control registers
*
* Registers
- * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
- * Control Register 0 (read/write).
- * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
- * Data Register 0 (audio, read/write).
- * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
- * Data Register 1 (telecom, read/write).
- * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
- * Data Register 2 (CODEC registers, read/write).
- * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
- * Status Register (read/write).
- * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
- * Control Register 1 (read/write).
- * [The MCCR1 register is only implemented in
- * versions 2.0 (rev. = 8) and higher of the StrongARM
- * SA-1100.]
+ * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
+ * Control Register 0 (read/write).
+ * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
+ * Data Register 0 (audio, read/write).
+ * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
+ * Data Register 1 (telecom, read/write).
+ * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
+ * Data Register 2 (CODEC registers, read/write).
+ * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
+ * Status Register (read/write).
+ * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
+ * Control Register 1 (read/write).
+ * [The MCCR1 register is only implemented in
+ * versions 2.0 (rev. = 8) and higher of the StrongARM
+ * SA-1100.]
*
* Clocks
- * fmc, Tmc Frequency, period of the MCP communication (10 MHz,
- * 12 MHz, or GPIO [21]).
+ * fmc, Tmc Frequency, period of the MCP communication (10 MHz,
+ * 12 MHz, or GPIO [21]).
* faud, Taud Frequency, period of the audio sampling.
* ftcm, Ttcm Frequency, period of the telecom sampling.
*/
#define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */
-#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */
- /* (audio) */
-#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */
- /* (telecom) */
-#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */
- /* (CODEC reg.) */
-#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */
+#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */
+ /* (audio) */
+#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */
+ /* (telecom) */
+#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */
+ /* (CODEC reg.) */
+#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */
#define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */
#if LANGUAGE == C
-#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \
+#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser4MCCR0)))
-#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \
- /* (audio) */ \
+#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \
+ /* (audio) */ \
(*((volatile Word *) io_p2v (_Ser4MCDR0)))
-#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \
- /* (telecom) */ \
+#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \
+ /* (telecom) */ \
(*((volatile Word *) io_p2v (_Ser4MCDR1)))
-#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \
- /* (CODEC reg.) */ \
+#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \
+ /* (CODEC reg.) */ \
(*((volatile Word *) io_p2v (_Ser4MCDR2)))
-#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \
+#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \
(*((volatile Word *) io_p2v (_Ser4MCSR)))
-#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \
+#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser4MCCR1)))
#endif /* LANGUAGE == C */
#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */
- /* [6..127] */
- /* faud = fmc/(32*ASD) */
- /* Taud = 32*ASD*Tmc */
-#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \
- /* [192..4064] */ \
+ /* [6..127] */
+ /* faud = fmc/(32*ASD) */
+ /* Taud = 32*ASD*Tmc */
+#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \
+ /* [192..4064] */ \
((Div)/32 << FShft (MCCR0_ASD))
/* faud = fmc/(32*Floor (Div/32)) */
/* Taud = 32*Floor (Div/32)*Tmc */
@@ -916,12 +916,12 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
(((Div) + 31)/32 << FShft (MCCR0_ASD))
/* faud = fmc/(32*Ceil (Div/32)) */
/* Taud = 32*Ceil (Div/32)*Tmc */
-#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */
- /* Divisor/32 [16..127] */
- /* ftcm = fmc/(32*TSD) */
- /* Ttcm = 32*TSD*Tmc */
-#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \
- /* [512..4064] */ \
+#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */
+ /* Divisor/32 [16..127] */
+ /* ftcm = fmc/(32*TSD) */
+ /* Ttcm = 32*TSD*Tmc */
+#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \
+ /* [512..4064] */ \
((Div)/32 << FShft (MCCR0_TSD))
/* ftcm = fmc/(32*Floor (Div/32)) */
/* Ttcm = 32*Floor (Div/32)*Tmc */
@@ -929,460 +929,460 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
(((Div) + 31)/32 << FShft (MCCR0_TSD))
/* ftcm = fmc/(32*Ceil (Div/32)) */
/* Ttcm = 32*Ceil (Div/32)*Tmc */
-#define MCCR0_MCE 0x00010000 /* MCP Enable */
-#define MCCR0_ECS 0x00020000 /* External Clock Select */
+#define MCCR0_MCE 0x00010000 /* MCP Enable */
+#define MCCR0_ECS 0x00020000 /* External Clock Select */
#define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
-#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
-#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */
- /* sampling/storing Mode */
-#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */
+#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
+#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */
+ /* sampling/storing Mode */
+#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */
#define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */
#define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
- /* or less interrupt Enable */
+ /* or less interrupt Enable */
#define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
- /* or more interrupt Enable */
+ /* or more interrupt Enable */
#define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
- /* or less interrupt Enable */
+ /* or less interrupt Enable */
#define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
- /* more interrupt Enable */
-#define MCCR0_LBM 0x00800000 /* Look-Back Mode */
+ /* more interrupt Enable */
+#define MCCR0_LBM 0x00800000 /* Look-Back Mode */
#define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
-#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
+#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
(((Div) - 1) << FShft (MCCR0_ECP))
-#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */
- /* FIFOs */
+#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */
+ /* FIFOs */
#define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */
- /* FIFOs */
+ /* FIFOs */
- /* receive/transmit CODEC reg. */
- /* FIFOs: */
-#define MCDR2_DATA Fld (16, 0) /* reg. DATA */
-#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
-#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
-#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
-#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
+ /* receive/transmit CODEC reg. */
+ /* FIFOs: */
+#define MCDR2_DATA Fld (16, 0) /* reg. DATA */
+#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
+#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
+#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
+#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
#define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
/* or less Service request (read) */
#define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
- /* more Service request (read) */
+ /* more Service request (read) */
#define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
/* or less Service request (read) */
#define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
/* or more Service request (read) */
#define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
-#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
+#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
#define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
#define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
#define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */
- /* (read) */
+ /* (read) */
#define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */
- /* (read) */
+ /* (read) */
#define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */
- /* (read) */
+ /* (read) */
#define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */
- /* (read) */
+ /* (read) */
#define MCSR_CWC 0x00001000 /* CODEC register Write Completed */
- /* (read) */
+ /* (read) */
#define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
- /* (read) */
-#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
+ /* (read) */
+#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
#define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
-#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */
-#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
- /* (11.981 MHz) */
-#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
- /* (9.585 MHz) */
+#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */
+#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
+ /* (11.981 MHz) */
+#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
+ /* (9.585 MHz) */
/*
* Synchronous Serial Port (SSP) control registers
*
* Registers
- * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control
- * Register 0 (read/write).
- * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control
- * Register 1 (read/write).
- * [Bits SPO and SP are only implemented in versions 2.0
- * (rev. = 8) and higher of the StrongARM SA-1100.]
- * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data
- * Register (read/write).
- * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status
- * Register (read/write).
+ * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control
+ * Register 0 (read/write).
+ * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control
+ * Register 1 (read/write).
+ * [Bits SPO and SP are only implemented in versions 2.0
+ * (rev. = 8) and higher of the StrongARM SA-1100.]
+ * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data
+ * Register (read/write).
+ * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status
+ * Register (read/write).
*
* Clocks
* fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
- * or 3.5795 MHz).
- * fss, Tss Frequency, period of the SSP communication.
+ * or 3.5795 MHz).
+ * fss, Tss Frequency, period of the SSP communication.
*/
#define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */
#define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */
-#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */
-#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */
+#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */
+#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */
#if LANGUAGE == C
-#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \
+#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser4SSCR0)))
-#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \
+#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser4SSCR1)))
-#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \
+#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser4SSDR)))
-#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \
+#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \
(*((volatile Word *) io_p2v (_Ser4SSSR)))
#endif /* LANGUAGE == C */
#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
-#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \
+#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \
(((Size) - 1) << FShft (SSCR0_DSS))
-#define SSCR0_FRF Fld (2, 4) /* FRame Format */
-#define SSCR0_Motorola /* Motorola Serial Peripheral */ \
- /* Interface (SPI) format */ \
+#define SSCR0_FRF Fld (2, 4) /* FRame Format */
+#define SSCR0_Motorola /* Motorola Serial Peripheral */ \
+ /* Interface (SPI) format */ \
(0 << FShft (SSCR0_FRF))
-#define SSCR0_TI /* Texas Instruments Synchronous */ \
- /* Serial format */ \
+#define SSCR0_TI /* Texas Instruments Synchronous */ \
+ /* Serial format */ \
(1 << FShft (SSCR0_FRF))
-#define SSCR0_National /* National Microwire format */ \
+#define SSCR0_National /* National Microwire format */ \
(2 << FShft (SSCR0_FRF))
-#define SSCR0_SSE 0x00000080 /* SSP Enable */
+#define SSCR0_SSE 0x00000080 /* SSP Enable */
#define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
- /* fss = fxtl/(2*(SCR + 1)) */
- /* Tss = 2*(SCR + 1)*Txtl */
-#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \
+ /* fss = fxtl/(2*(SCR + 1)) */
+ /* Tss = 2*(SCR + 1)*Txtl */
+#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \
(((Div) - 2)/2 << FShft (SSCR0_SCR))
/* fss = fxtl/(2*Floor (Div/2)) */
- /* Tss = 2*Floor (Div/2)*Txtl */
+ /* Tss = 2*Floor (Div/2)*Txtl */
#define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \
(((Div) - 1)/2 << FShft (SSCR0_SCR))
/* fss = fxtl/(2*Ceil (Div/2)) */
- /* Tss = 2*Ceil (Div/2)*Txtl */
+ /* Tss = 2*Ceil (Div/2)*Txtl */
#define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
- /* Interrupt Enable */
+ /* Interrupt Enable */
#define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
- /* Interrupt Enable */
-#define SSCR1_LBM 0x00000004 /* Look-Back Mode */
+ /* Interrupt Enable */
+#define SSCR1_LBM 0x00000004 /* Look-Back Mode */
#define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */
-#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
-#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
-#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */
+#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
+#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
+#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */
#define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
/* after frame (SFRM, 1st edge) */
#define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */
/* after frame (SFRM, 1st edge) */
-#define SSCR1_ECS 0x00000020 /* External Clock Select */
-#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */
-#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
+#define SSCR1_ECS 0x00000020 /* External Clock Select */
+#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */
+#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
-#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */
+#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */
#define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
#define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
-#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
+#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
#define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
- /* Service request (read) */
+ /* Service request (read) */
#define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
- /* Service request (read) */
-#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
+ /* Service request (read) */
+#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
/*
* Operating System (OS) timer control registers
*
* Registers
- * OSMR0 Operating System (OS) timer Match Register 0
- * (read/write).
- * OSMR1 Operating System (OS) timer Match Register 1
- * (read/write).
- * OSMR2 Operating System (OS) timer Match Register 2
- * (read/write).
- * OSMR3 Operating System (OS) timer Match Register 3
- * (read/write).
- * OSCR Operating System (OS) timer Counter Register
- * (read/write).
- * OSSR Operating System (OS) timer Status Register
- * (read/write).
- * OWER Operating System (OS) timer Watch-dog Enable Register
- * (read/write).
- * OIER Operating System (OS) timer Interrupt Enable Register
- * (read/write).
+ * OSMR0 Operating System (OS) timer Match Register 0
+ * (read/write).
+ * OSMR1 Operating System (OS) timer Match Register 1
+ * (read/write).
+ * OSMR2 Operating System (OS) timer Match Register 2
+ * (read/write).
+ * OSMR3 Operating System (OS) timer Match Register 3
+ * (read/write).
+ * OSCR Operating System (OS) timer Counter Register
+ * (read/write).
+ * OSSR Operating System (OS) timer Status Register
+ * (read/write).
+ * OWER Operating System (OS) timer Watch-dog Enable Register
+ * (read/write).
+ * OIER Operating System (OS) timer Interrupt Enable Register
+ * (read/write).
*/
-#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \
+#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \
(0x90000000 + (Nb)*4)
-#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */
-#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */
-#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */
-#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */
-#define _OSCR 0x90000010 /* OS timer Counter Reg. */
-#define _OSSR 0x90000014 /* OS timer Status Reg. */
-#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */
-#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */
+#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */
+#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */
+#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */
+#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */
+#define _OSCR 0x90000010 /* OS timer Counter Reg. */
+#define _OSSR 0x90000014 /* OS timer Status Reg. */
+#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */
+#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */
#if LANGUAGE == C
-#define OSMR /* OS timer Match Reg. [0..3] */ \
+#define OSMR /* OS timer Match Reg. [0..3] */ \
((volatile Word *) io_p2v (_OSMR (0)))
-#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */
-#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */
-#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */
-#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */
-#define OSCR /* OS timer Counter Reg. */ \
+#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */
+#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */
+#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */
+#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */
+#define OSCR /* OS timer Counter Reg. */ \
(*((volatile Word *) io_p2v (_OSCR)))
-#define OSSR /* OS timer Status Reg. */ \
+#define OSSR /* OS timer Status Reg. */ \
(*((volatile Word *) io_p2v (_OSSR)))
-#define OWER /* OS timer Watch-dog Enable Reg. */ \
+#define OWER /* OS timer Watch-dog Enable Reg. */ \
(*((volatile Word *) io_p2v (_OWER)))
-#define OIER /* OS timer Interrupt Enable Reg. */ \
+#define OIER /* OS timer Interrupt Enable Reg. */ \
(*((volatile Word *) io_p2v (_OIER)))
#endif /* LANGUAGE == C */
-#define OSSR_M(Nb) /* Match detected [0..3] */ \
+#define OSSR_M(Nb) /* Match detected [0..3] */ \
(0x00000001 << (Nb))
-#define OSSR_M0 OSSR_M (0) /* Match detected 0 */
-#define OSSR_M1 OSSR_M (1) /* Match detected 1 */
-#define OSSR_M2 OSSR_M (2) /* Match detected 2 */
-#define OSSR_M3 OSSR_M (3) /* Match detected 3 */
+#define OSSR_M0 OSSR_M (0) /* Match detected 0 */
+#define OSSR_M1 OSSR_M (1) /* Match detected 1 */
+#define OSSR_M2 OSSR_M (2) /* Match detected 2 */
+#define OSSR_M3 OSSR_M (3) /* Match detected 3 */
-#define OWER_WME 0x00000001 /* Watch-dog Match Enable */
- /* (set only) */
+#define OWER_WME 0x00000001 /* Watch-dog Match Enable */
+ /* (set only) */
-#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \
+#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \
(0x00000001 << (Nb))
-#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */
-#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
-#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */
-#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */
+#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */
+#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
+#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */
+#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */
/*
* Real-Time Clock (RTC) control registers
*
* Registers
- * RTAR Real-Time Clock (RTC) Alarm Register (read/write).
- * RCNR Real-Time Clock (RTC) CouNt Register (read/write).
- * RTTR Real-Time Clock (RTC) Trim Register (read/write).
- * RTSR Real-Time Clock (RTC) Status Register (read/write).
+ * RTAR Real-Time Clock (RTC) Alarm Register (read/write).
+ * RCNR Real-Time Clock (RTC) CouNt Register (read/write).
+ * RTTR Real-Time Clock (RTC) Trim Register (read/write).
+ * RTSR Real-Time Clock (RTC) Status Register (read/write).
*
* Clocks
* frtx, Trtx Frequency, period of the real-time clock crystal
- * (32.768 kHz nominal).
+ * (32.768 kHz nominal).
* frtc, Trtc Frequency, period of the real-time clock counter
- * (1 Hz nominal).
+ * (1 Hz nominal).
*/
-#define _RTAR 0x90010000 /* RTC Alarm Reg. */
-#define _RCNR 0x90010004 /* RTC CouNt Reg. */
-#define _RTTR 0x90010008 /* RTC Trim Reg. */
-#define _RTSR 0x90010010 /* RTC Status Reg. */
+#define _RTAR 0x90010000 /* RTC Alarm Reg. */
+#define _RCNR 0x90010004 /* RTC CouNt Reg. */
+#define _RTTR 0x90010008 /* RTC Trim Reg. */
+#define _RTSR 0x90010010 /* RTC Status Reg. */
#if LANGUAGE == C
-#define RTAR /* RTC Alarm Reg. */ \
+#define RTAR /* RTC Alarm Reg. */ \
(*((volatile Word *) io_p2v (_RTAR)))
-#define RCNR /* RTC CouNt Reg. */ \
+#define RCNR /* RTC CouNt Reg. */ \
(*((volatile Word *) io_p2v (_RCNR)))
-#define RTTR /* RTC Trim Reg. */ \
+#define RTTR /* RTC Trim Reg. */ \
(*((volatile Word *) io_p2v (_RTTR)))
-#define RTSR /* RTC Status Reg. */ \
+#define RTSR /* RTC Status Reg. */ \
(*((volatile Word *) io_p2v (_RTSR)))
#endif /* LANGUAGE == C */
-#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */
-#define RTTR_D Fld (10, 16) /* trim Delete count */
+#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */
+#define RTTR_D Fld (10, 16) /* trim Delete count */
/* frtc = (1023*(C + 1) - D)*frtx/ */
- /* (1023*(C + 1)^2) */
+ /* (1023*(C + 1)^2) */
/* Trtc = (1023*(C + 1)^2)*Trtx/ */
- /* (1023*(C + 1) - D) */
+ /* (1023*(C + 1) - D) */
-#define RTSR_AL 0x00000001 /* ALarm detected */
-#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */
-#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */
-#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */
+#define RTSR_AL 0x00000001 /* ALarm detected */
+#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */
+#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */
+#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */
/*
* Power Manager (PM) control registers
*
* Registers
- * PMCR Power Manager (PM) Control Register (read/write).
- * PSSR Power Manager (PM) Sleep Status Register (read/write).
- * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
- * PWER Power Manager (PM) Wake-up Enable Register
- * (read/write).
- * PCFR Power Manager (PM) general ConFiguration Register
- * (read/write).
- * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
- * Configuration Register (read/write).
- * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
- * Sleep state Register (read/write, see GPIO pins).
- * POSR Power Manager (PM) Oscillator Status Register (read).
+ * PMCR Power Manager (PM) Control Register (read/write).
+ * PSSR Power Manager (PM) Sleep Status Register (read/write).
+ * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
+ * PWER Power Manager (PM) Wake-up Enable Register
+ * (read/write).
+ * PCFR Power Manager (PM) general ConFiguration Register
+ * (read/write).
+ * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
+ * Configuration Register (read/write).
+ * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
+ * Sleep state Register (read/write, see GPIO pins).
+ * POSR Power Manager (PM) Oscillator Status Register (read).
*
* Clocks
* fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
- * or 3.5795 MHz).
+ * or 3.5795 MHz).
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
*/
-#define _PMCR 0x90020000 /* PM Control Reg. */
-#define _PSSR 0x90020004 /* PM Sleep Status Reg. */
-#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */
-#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */
-#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */
-#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */
-#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */
-#define _POSR 0x9002001C /* PM Oscillator Status Reg. */
+#define _PMCR 0x90020000 /* PM Control Reg. */
+#define _PSSR 0x90020004 /* PM Sleep Status Reg. */
+#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */
+#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */
+#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */
+#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */
+#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */
+#define _POSR 0x9002001C /* PM Oscillator Status Reg. */
#if LANGUAGE == C
-#define PMCR /* PM Control Reg. */ \
+#define PMCR /* PM Control Reg. */ \
(*((volatile Word *) io_p2v (_PMCR)))
-#define PSSR /* PM Sleep Status Reg. */ \
+#define PSSR /* PM Sleep Status Reg. */ \
(*((volatile Word *) io_p2v (_PSSR)))
-#define PSPR /* PM Scratch-Pad Reg. */ \
+#define PSPR /* PM Scratch-Pad Reg. */ \
(*((volatile Word *) io_p2v (_PSPR)))
-#define PWER /* PM Wake-up Enable Reg. */ \
+#define PWER /* PM Wake-up Enable Reg. */ \
(*((volatile Word *) io_p2v (_PWER)))
-#define PCFR /* PM general ConFiguration Reg. */ \
+#define PCFR /* PM general ConFiguration Reg. */ \
(*((volatile Word *) io_p2v (_PCFR)))
-#define PPCR /* PM PLL Configuration Reg. */ \
+#define PPCR /* PM PLL Configuration Reg. */ \
(*((volatile Word *) io_p2v (_PPCR)))
-#define PGSR /* PM GPIO Sleep state Reg. */ \
+#define PGSR /* PM GPIO Sleep state Reg. */ \
(*((volatile Word *) io_p2v (_PGSR)))
-#define POSR /* PM Oscillator Status Reg. */ \
+#define POSR /* PM Oscillator Status Reg. */ \
(*((volatile Word *) io_p2v (_POSR)))
#elif LANGUAGE == Assembly
-#define PMCR (io_p2v (_PMCR))
-#define PSSR (io_p2v (_PSSR))
-#define PSPR (io_p2v (_PSPR))
-#define PWER (io_p2v (_PWER))
-#define PCFR (io_p2v (_PCFR))
-#define PPCR (io_p2v (_PPCR))
-#define PGSR (io_p2v (_PGSR))
-#define POSR (io_p2v (_POSR))
+#define PMCR (io_p2v (_PMCR))
+#define PSSR (io_p2v (_PSSR))
+#define PSPR (io_p2v (_PSPR))
+#define PWER (io_p2v (_PWER))
+#define PCFR (io_p2v (_PCFR))
+#define PPCR (io_p2v (_PPCR))
+#define PGSR (io_p2v (_PGSR))
+#define POSR (io_p2v (_POSR))
#endif /* LANGUAGE == C */
-#define PMCR_SF 0x00000001 /* Sleep Force (set only) */
+#define PMCR_SF 0x00000001 /* Sleep Force (set only) */
-#define PSSR_SS 0x00000001 /* Software Sleep */
-#define PSSR_BFS 0x00000002 /* Battery Fault Status */
- /* (BATT_FAULT) */
+#define PSSR_SS 0x00000001 /* Software Sleep */
+#define PSSR_BFS 0x00000002 /* Battery Fault Status */
+ /* (BATT_FAULT) */
#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */
-#define PSSR_DH 0x00000008 /* DRAM control Hold */
-#define PSSR_PH 0x00000010 /* Peripheral control Hold */
-
-#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
-#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
-#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
-#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
-#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
-#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
-#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
-#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
-#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
-#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
-#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
-#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
-#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
-#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
-#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
-#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
-#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
-#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
-#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
-#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
-#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
-#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
-#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
-#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
-#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
-#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
-#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
-#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
-#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
-#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
+#define PSSR_DH 0x00000008 /* DRAM control Hold */
+#define PSSR_PH 0x00000010 /* Peripheral control Hold */
+
+#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
+#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
+#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
+#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
+#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
+#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
+#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
+#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
+#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
+#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
+#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
+#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
+#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
+#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
+#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
+#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
+#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
+#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
+#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
+#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
+#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
+#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
+#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
+#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
+#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
+#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
+#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
+#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
+#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
+#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
#define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
#define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */
#define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */
-#define PCFR_FP 0x00000002 /* Float PCMCIA pins */
-#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
-#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */
-#define PCFR_FS 0x00000004 /* Float Static memory pins */
+#define PCFR_FP 0x00000002 /* Float PCMCIA pins */
+#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
+#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */
+#define PCFR_FS 0x00000004 /* Float Static memory pins */
#define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
#define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */
-#define PCFR_FO 0x00000008 /* Force RTC oscillator */
- /* (32.768 kHz) enable On */
+#define PCFR_FO 0x00000008 /* Force RTC oscillator */
+ /* (32.768 kHz) enable On */
-#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
-#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \
+#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
+#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \
(0x00 << FShft (PPCR_CCF))
-#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \
+#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \
(0x01 << FShft (PPCR_CCF))
-#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \
+#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \
(0x02 << FShft (PPCR_CCF))
-#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \
+#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \
(0x03 << FShft (PPCR_CCF))
-#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \
+#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \
(0x04 << FShft (PPCR_CCF))
-#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \
+#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \
(0x05 << FShft (PPCR_CCF))
-#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \
+#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \
(0x06 << FShft (PPCR_CCF))
-#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \
+#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \
(0x07 << FShft (PPCR_CCF))
-#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \
+#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \
(0x08 << FShft (PPCR_CCF))
-#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \
+#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \
(0x09 << FShft (PPCR_CCF))
-#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \
+#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \
(0x0A << FShft (PPCR_CCF))
-#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \
+#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \
(0x0B << FShft (PPCR_CCF))
-#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \
+#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \
(0x0C << FShft (PPCR_CCF))
-#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \
+#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \
(0x0D << FShft (PPCR_CCF))
-#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \
+#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \
(0x0E << FShft (PPCR_CCF))
-#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \
+#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \
(0x0F << FShft (PPCR_CCF))
- /* 3.6864 MHz crystal (fxtl): */
-#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */
-#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */
-#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */
-#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */
-#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */
-#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */
-#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */
-#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */
-#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */
-#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */
-#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */
-#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */
-#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */
-#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */
-#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */
-#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */
- /* 3.5795 MHz crystal (fxtl): */
-#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */
-#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */
-#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */
-#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */
-#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */
-#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */
-#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */
-#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */
-#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */
-#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */
-#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */
-#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */
-#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */
-#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */
-#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */
-#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */
+ /* 3.6864 MHz crystal (fxtl): */
+#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */
+#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */
+#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */
+#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */
+#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */
+#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */
+#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */
+#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */
+#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */
+#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */
+#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */
+#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */
+#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */
+#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */
+#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */
+#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */
+ /* 3.5795 MHz crystal (fxtl): */
+#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */
+#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */
+#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */
+#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */
+#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */
+#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */
+#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */
+#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */
+#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */
+#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */
+#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */
+#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */
+#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */
+#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */
+#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */
+#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */
#define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */
@@ -1391,75 +1391,75 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
* Reset Controller (RC) control registers
*
* Registers
- * RSRR Reset Controller (RC) Software Reset Register
- * (read/write).
- * RCSR Reset Controller (RC) Status Register (read/write).
+ * RSRR Reset Controller (RC) Software Reset Register
+ * (read/write).
+ * RCSR Reset Controller (RC) Status Register (read/write).
*/
-#define _RSRR 0x90030000 /* RC Software Reset Reg. */
-#define _RCSR 0x90030004 /* RC Status Reg. */
+#define _RSRR 0x90030000 /* RC Software Reset Reg. */
+#define _RCSR 0x90030004 /* RC Status Reg. */
#if LANGUAGE == C
-#define RSRR /* RC Software Reset Reg. */ \
+#define RSRR /* RC Software Reset Reg. */ \
(*((volatile Word *) io_p2v (_RSRR)))
-#define RCSR /* RC Status Reg. */ \
+#define RCSR /* RC Status Reg. */ \
(*((volatile Word *) io_p2v (_RCSR)))
#endif /* LANGUAGE == C */
-#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */
+#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */
-#define RCSR_HWR 0x00000001 /* HardWare Reset */
-#define RCSR_SWR 0x00000002 /* SoftWare Reset */
-#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
-#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
+#define RCSR_HWR 0x00000001 /* HardWare Reset */
+#define RCSR_SWR 0x00000002 /* SoftWare Reset */
+#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
+#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
/*
* Test unit control registers
*
* Registers
- * TUCR Test Unit Control Register (read/write).
+ * TUCR Test Unit Control Register (read/write).
*/
-#define _TUCR 0x90030008 /* Test Unit Control Reg. */
+#define _TUCR 0x90030008 /* Test Unit Control Reg. */
#if LANGUAGE == C
-#define TUCR /* Test Unit Control Reg. */ \
+#define TUCR /* Test Unit Control Reg. */ \
(*((volatile Word *) io_p2v (_TUCR)))
#endif /* LANGUAGE == C */
-#define TUCR_TIC 0x00000040 /* TIC mode */
-#define TUCR_TTST 0x00000080 /* Trim TeST mode */
-#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */
- /* Check */
-#define TUCR_PMD 0x00000200 /* Power Management Disable */
-#define TUCR_MR 0x00000400 /* Memory Request mode */
+#define TUCR_TIC 0x00000040 /* TIC mode */
+#define TUCR_TTST 0x00000080 /* Trim TeST mode */
+#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */
+ /* Check */
+#define TUCR_PMD 0x00000200 /* Power Management Disable */
+#define TUCR_MR 0x00000400 /* Memory Request mode */
#define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */
#define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */
/* grant (MBGNT) on GPIO [22:21] */
-#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */
-#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */
+#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */
+#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */
#define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */
#define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */
-#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */
+#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */
#define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */
-#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \
+#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \
(0 << FShft (TUCR_TSEL))
-#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \
+#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \
(1 << FShft (TUCR_TSEL))
-#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \
+#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \
(2 << FShft (TUCR_TSEL))
-#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \
+#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \
(3 << FShft (TUCR_TSEL))
-#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \
- /* Clocks on GPIO [26:27] */ \
+#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \
+ /* Clocks on GPIO [26:27] */ \
(4 << FShft (TUCR_TSEL))
-#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \
- /* (Alternative) */ \
+#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \
+ /* (Alternative) */ \
(5 << FShft (TUCR_TSEL))
-#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \
+#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \
(6 << FShft (TUCR_TSEL))
-#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \
+#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \
(7 << FShft (TUCR_TSEL))
@@ -1467,52 +1467,52 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
* General-Purpose Input/Output (GPIO) control registers
*
* Registers
- * GPLR General-Purpose Input/Output (GPIO) Pin Level
- * Register (read).
- * GPDR General-Purpose Input/Output (GPIO) Pin Direction
- * Register (read/write).
- * GPSR General-Purpose Input/Output (GPIO) Pin output Set
- * Register (write).
- * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
- * Register (write).
- * GRER General-Purpose Input/Output (GPIO) Rising-Edge
- * detect Register (read/write).
- * GFER General-Purpose Input/Output (GPIO) Falling-Edge
- * detect Register (read/write).
- * GEDR General-Purpose Input/Output (GPIO) Edge Detect
- * status Register (read/write).
- * GAFR General-Purpose Input/Output (GPIO) Alternate
- * Function Register (read/write).
+ * GPLR General-Purpose Input/Output (GPIO) Pin Level
+ * Register (read).
+ * GPDR General-Purpose Input/Output (GPIO) Pin Direction
+ * Register (read/write).
+ * GPSR General-Purpose Input/Output (GPIO) Pin output Set
+ * Register (write).
+ * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
+ * Register (write).
+ * GRER General-Purpose Input/Output (GPIO) Rising-Edge
+ * detect Register (read/write).
+ * GFER General-Purpose Input/Output (GPIO) Falling-Edge
+ * detect Register (read/write).
+ * GEDR General-Purpose Input/Output (GPIO) Edge Detect
+ * status Register (read/write).
+ * GAFR General-Purpose Input/Output (GPIO) Alternate
+ * Function Register (read/write).
*
* Clock
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
*/
-#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */
-#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */
-#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */
-#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */
-#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */
-#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */
-#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */
-#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */
+#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */
+#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */
+#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */
+#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */
+#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */
+#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */
+#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */
+#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */
#if LANGUAGE == C
-#define GPLR /* GPIO Pin Level Reg. */ \
+#define GPLR /* GPIO Pin Level Reg. */ \
(*((volatile Word *) io_p2v (_GPLR)))
-#define GPDR /* GPIO Pin Direction Reg. */ \
+#define GPDR /* GPIO Pin Direction Reg. */ \
(*((volatile Word *) io_p2v (_GPDR)))
-#define GPSR /* GPIO Pin output Set Reg. */ \
+#define GPSR /* GPIO Pin output Set Reg. */ \
(*((volatile Word *) io_p2v (_GPSR)))
-#define GPCR /* GPIO Pin output Clear Reg. */ \
+#define GPCR /* GPIO Pin output Clear Reg. */ \
(*((volatile Word *) io_p2v (_GPCR)))
-#define GRER /* GPIO Rising-Edge detect Reg. */ \
+#define GRER /* GPIO Rising-Edge detect Reg. */ \
(*((volatile Word *) io_p2v (_GRER)))
-#define GFER /* GPIO Falling-Edge detect Reg. */ \
+#define GFER /* GPIO Falling-Edge detect Reg. */ \
(*((volatile Word *) io_p2v (_GFER)))
-#define GEDR /* GPIO Edge Detect status Reg. */ \
+#define GEDR /* GPIO Edge Detect status Reg. */ \
(*((volatile Word *) io_p2v (_GEDR)))
-#define GAFR /* GPIO Alternate Function Reg. */ \
+#define GAFR /* GPIO Alternate Function Reg. */ \
(*((volatile Word *) io_p2v (_GAFR)))
#elif LANGUAGE == Assembly
@@ -1530,280 +1530,280 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
#define GPIO_MIN (0)
#define GPIO_MAX (27)
-#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \
+#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \
(0x00000001 << (Nb))
-#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */
-#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */
-#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */
-#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */
-#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */
-#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */
-#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */
-#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */
-#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */
-#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */
-#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */
-#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */
-#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */
-#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */
-#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */
-#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */
-#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */
-#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */
-#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */
-#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */
-#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */
-#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */
-#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */
-#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */
-#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */
-#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */
-#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */
-#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */
-
-#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \
+#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */
+#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */
+#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */
+#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */
+#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */
+#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */
+#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */
+#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */
+#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */
+#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */
+#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */
+#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */
+#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */
+#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */
+#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */
+#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */
+#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */
+#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */
+#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */
+#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */
+#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */
+#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */
+#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */
+#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */
+#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */
+#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */
+#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */
+#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */
+
+#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \
GPIO_GPIO ((Nb) - 6)
-#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */
-#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */
-#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */
-#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */
-#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */
-#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */
-#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */
-#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */
- /* ser. port 4: */
-#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */
-#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */
-#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */
-#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */
- /* ser. port 1: */
-#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */
-#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */
-#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */
-#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */
-#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */
- /* ser. port 4: */
-#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */
- /* ser. port 3: */
-#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */
- /* ser. port 4: */
-#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */
- /* test controller: */
-#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */
-#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */
-#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */
-#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */
-#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */
-#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
+#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */
+#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */
+#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */
+#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */
+#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */
+#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */
+#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */
+#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */
+ /* ser. port 4: */
+#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */
+#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */
+#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */
+#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */
+ /* ser. port 1: */
+#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */
+#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */
+#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */
+#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */
+#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */
+ /* ser. port 4: */
+#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */
+ /* ser. port 3: */
+#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */
+ /* ser. port 4: */
+#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */
+ /* test controller: */
+#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */
+#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */
+#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */
+#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */
+#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */
+#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */
-#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */
+#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */
-#define GPDR_In 0 /* Input */
-#define GPDR_Out 1 /* Output */
+#define GPDR_In 0 /* Input */
+#define GPDR_Out 1 /* Output */
/*
* Interrupt Controller (IC) control registers
*
* Registers
- * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ)
- * Pending register (read).
- * ICMR Interrupt Controller (IC) Mask Register (read/write).
- * ICLR Interrupt Controller (IC) Level Register (read/write).
- * ICCR Interrupt Controller (IC) Control Register
- * (read/write).
- * [The ICCR register is only implemented in versions 2.0
- * (rev. = 8) and higher of the StrongARM SA-1100.]
- * ICFP Interrupt Controller (IC) Fast Interrupt reQuest
- * (FIQ) Pending register (read).
- * ICPR Interrupt Controller (IC) Pending Register (read).
- * [The ICPR register is active low (inverted) in
- * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
- * StrongARM SA-1100, it is active high (non-inverted) in
- * versions 2.0 (rev. = 8) and higher.]
+ * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ)
+ * Pending register (read).
+ * ICMR Interrupt Controller (IC) Mask Register (read/write).
+ * ICLR Interrupt Controller (IC) Level Register (read/write).
+ * ICCR Interrupt Controller (IC) Control Register
+ * (read/write).
+ * [The ICCR register is only implemented in versions 2.0
+ * (rev. = 8) and higher of the StrongARM SA-1100.]
+ * ICFP Interrupt Controller (IC) Fast Interrupt reQuest
+ * (FIQ) Pending register (read).
+ * ICPR Interrupt Controller (IC) Pending Register (read).
+ * [The ICPR register is active low (inverted) in
+ * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ * StrongARM SA-1100, it is active high (non-inverted) in
+ * versions 2.0 (rev. = 8) and higher.]
*/
-#define _ICIP 0x90050000 /* IC IRQ Pending reg. */
-#define _ICMR 0x90050004 /* IC Mask Reg. */
-#define _ICLR 0x90050008 /* IC Level Reg. */
-#define _ICCR 0x9005000C /* IC Control Reg. */
-#define _ICFP 0x90050010 /* IC FIQ Pending reg. */
-#define _ICPR 0x90050020 /* IC Pending Reg. */
+#define _ICIP 0x90050000 /* IC IRQ Pending reg. */
+#define _ICMR 0x90050004 /* IC Mask Reg. */
+#define _ICLR 0x90050008 /* IC Level Reg. */
+#define _ICCR 0x9005000C /* IC Control Reg. */
+#define _ICFP 0x90050010 /* IC FIQ Pending reg. */
+#define _ICPR 0x90050020 /* IC Pending Reg. */
#if LANGUAGE == C
-#define ICIP /* IC IRQ Pending reg. */ \
+#define ICIP /* IC IRQ Pending reg. */ \
(*((volatile Word *) io_p2v (_ICIP)))
-#define ICMR /* IC Mask Reg. */ \
+#define ICMR /* IC Mask Reg. */ \
(*((volatile Word *) io_p2v (_ICMR)))
-#define ICLR /* IC Level Reg. */ \
+#define ICLR /* IC Level Reg. */ \
(*((volatile Word *) io_p2v (_ICLR)))
-#define ICCR /* IC Control Reg. */ \
+#define ICCR /* IC Control Reg. */ \
(*((volatile Word *) io_p2v (_ICCR)))
-#define ICFP /* IC FIQ Pending reg. */ \
+#define ICFP /* IC FIQ Pending reg. */ \
(*((volatile Word *) io_p2v (_ICFP)))
-#define ICPR /* IC Pending Reg. */ \
+#define ICPR /* IC Pending Reg. */ \
(*((volatile Word *) io_p2v (_ICPR)))
#endif /* LANGUAGE == C */
-#define IC_GPIO(Nb) /* GPIO [0..10] */ \
+#define IC_GPIO(Nb) /* GPIO [0..10] */ \
(0x00000001 << (Nb))
-#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */
-#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
-#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */
-#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */
-#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */
-#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */
-#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */
-#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */
-#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */
-#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */
-#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */
-#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */
-#define IC_LCD 0x00001000 /* LCD controller */
-#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
-#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
-#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
-#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */
-#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */
-#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */
-#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */
-#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \
+#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */
+#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
+#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */
+#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */
+#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */
+#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */
+#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */
+#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */
+#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */
+#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */
+#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */
+#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */
+#define IC_LCD 0x00001000 /* LCD controller */
+#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
+#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
+#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
+#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */
+#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */
+#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */
+#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */
+#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \
(0x00100000 << (Nb))
-#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */
-#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
-#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */
-#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */
-#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */
-#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */
-#define IC_OST(Nb) /* OS Timer match [0..3] */ \
+#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */
+#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
+#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */
+#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */
+#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */
+#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */
+#define IC_OST(Nb) /* OS Timer match [0..3] */ \
(0x04000000 << (Nb))
-#define IC_OST0 IC_OST (0) /* OS Timer match 0 */
-#define IC_OST1 IC_OST (1) /* OS Timer match 1 */
-#define IC_OST2 IC_OST (2) /* OS Timer match 2 */
-#define IC_OST3 IC_OST (3) /* OS Timer match 3 */
-#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
-#define IC_RTCAlrm 0x80000000 /* RTC Alarm */
-
-#define ICLR_IRQ 0 /* Interrupt ReQuest */
-#define ICLR_FIQ 1 /* Fast Interrupt reQuest */
-
-#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
- /* Mask */
+#define IC_OST0 IC_OST (0) /* OS Timer match 0 */
+#define IC_OST1 IC_OST (1) /* OS Timer match 1 */
+#define IC_OST2 IC_OST (2) /* OS Timer match 2 */
+#define IC_OST3 IC_OST (3) /* OS Timer match 3 */
+#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
+#define IC_RTCAlrm 0x80000000 /* RTC Alarm */
+
+#define ICLR_IRQ 0 /* Interrupt ReQuest */
+#define ICLR_FIQ 1 /* Fast Interrupt reQuest */
+
+#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
+ /* Mask */
#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
- /* (ICMR ignored) */
+ /* (ICMR ignored) */
#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
- /* enable (ICMR used) */
+ /* enable (ICMR used) */
/*
* Peripheral Pin Controller (PPC) control registers
*
* Registers
- * PPDR Peripheral Pin Controller (PPC) Pin Direction
- * Register (read/write).
- * PPSR Peripheral Pin Controller (PPC) Pin State Register
- * (read/write).
- * PPAR Peripheral Pin Controller (PPC) Pin Assignment
- * Register (read/write).
- * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
- * Direction Register (read/write).
- * PPFR Peripheral Pin Controller (PPC) Pin Flag Register
- * (read).
+ * PPDR Peripheral Pin Controller (PPC) Pin Direction
+ * Register (read/write).
+ * PPSR Peripheral Pin Controller (PPC) Pin State Register
+ * (read/write).
+ * PPAR Peripheral Pin Controller (PPC) Pin Assignment
+ * Register (read/write).
+ * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
+ * Direction Register (read/write).
+ * PPFR Peripheral Pin Controller (PPC) Pin Flag Register
+ * (read).
*/
-#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */
-#define _PPSR 0x90060004 /* PPC Pin State Reg. */
-#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */
-#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */
- /* Reg. */
-#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */
+#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */
+#define _PPSR 0x90060004 /* PPC Pin State Reg. */
+#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */
+#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */
+ /* Reg. */
+#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */
#if LANGUAGE == C
-#define PPDR /* PPC Pin Direction Reg. */ \
+#define PPDR /* PPC Pin Direction Reg. */ \
(*((volatile Word *) io_p2v (_PPDR)))
-#define PPSR /* PPC Pin State Reg. */ \
+#define PPSR /* PPC Pin State Reg. */ \
(*((volatile Word *) io_p2v (_PPSR)))
-#define PPAR /* PPC Pin Assignment Reg. */ \
+#define PPAR /* PPC Pin Assignment Reg. */ \
(*((volatile Word *) io_p2v (_PPAR)))
-#define PSDR /* PPC Sleep-mode pin Direction */ \
- /* Reg. */ \
+#define PSDR /* PPC Sleep-mode pin Direction */ \
+ /* Reg. */ \
(*((volatile Word *) io_p2v (_PSDR)))
-#define PPFR /* PPC Pin Flag Reg. */ \
+#define PPFR /* PPC Pin Flag Reg. */ \
(*((volatile Word *) io_p2v (_PPFR)))
#endif /* LANGUAGE == C */
-#define PPC_LDD(Nb) /* LCD Data [0..7] */ \
+#define PPC_LDD(Nb) /* LCD Data [0..7] */ \
(0x00000001 << (Nb))
-#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */
-#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
-#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */
-#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */
-#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */
-#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */
-#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */
-#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */
-#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */
-#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */
-#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */
-#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */
- /* ser. port 1: */
-#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
-#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
- /* ser. port 2: */
-#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
-#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
- /* ser. port 3: */
-#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */
-#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */
- /* ser. port 4: */
-#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */
-#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */
-#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */
-#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */
-
-#define PPDR_In 0 /* Input */
-#define PPDR_Out 1 /* Output */
-
- /* ser. port 1: */
-#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */
-#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */
-#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
- /* ser. port 4: */
-#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */
+#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */
+#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
+#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */
+#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */
+#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */
+#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */
+#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */
+#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */
+#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */
+#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */
+#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */
+#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */
+ /* ser. port 1: */
+#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
+#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
+ /* ser. port 2: */
+#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
+#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
+ /* ser. port 3: */
+#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */
+#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */
+ /* ser. port 4: */
+#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */
+#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */
+#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */
+#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */
+
+#define PPDR_In 0 /* Input */
+#define PPDR_Out 1 /* Output */
+
+ /* ser. port 1: */
+#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */
+#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */
+#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
+ /* ser. port 4: */
+#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */
#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */
- /* & SFRM_C */
-#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
+ /* & SFRM_C */
+#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
-#define PSDR_OutL 0 /* Output Low in sleep mode */
-#define PSDR_Flt 1 /* Floating (input) in sleep mode */
+#define PSDR_OutL 0 /* Output Low in sleep mode */
+#define PSDR_Flt 1 /* Floating (input) in sleep mode */
-#define PPFR_LCD 0x00000001 /* LCD controller */
+#define PPFR_LCD 0x00000001 /* LCD controller */
#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
-#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */
-#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */
-#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */
-#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
-#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */
-#define PPFR_PerEn 0 /* Peripheral Enabled */
-#define PPFR_PPCEn 1 /* PPC Enabled */
+#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */
+#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */
+#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */
+#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
+#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */
+#define PPFR_PerEn 0 /* Peripheral Enabled */
+#define PPFR_PPCEn 1 /* PPC Enabled */
/*
* Dynamic Random-Access Memory (DRAM) control registers
*
* Registers
- * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
- * CoNFiGuration register (read/write).
- * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
- * Column Address Strobe (CAS) shift register 0
- * (read/write).
- * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
- * Column Address Strobe (CAS) shift register 1
- * (read/write).
- * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
- * Column Address Strobe (CAS) shift register 2
- * (read/write).
+ * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
+ * CoNFiGuration register (read/write).
+ * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
+ * Column Address Strobe (CAS) shift register 0
+ * (read/write).
+ * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
+ * Column Address Strobe (CAS) shift register 1
+ * (read/write).
+ * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
+ * Column Address Strobe (CAS) shift register 2
+ * (read/write).
*
* Clocks
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
@@ -1811,23 +1811,23 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
* fcas, Tcas Frequency, period of the DRAM CAS shift registers.
*/
- /* Memory system: */
-#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */
-#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \
+ /* Memory system: */
+#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */
+#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \
(0xA0000004 + (Nb)*4)
-#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */
-#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */
-#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */
+#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */
+#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */
+#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */
#if LANGUAGE == C
- /* Memory system: */
-#define MDCNFG /* DRAM CoNFiGuration reg. */ \
+ /* Memory system: */
+#define MDCNFG /* DRAM CoNFiGuration reg. */ \
(*((volatile Word *) io_p2v (_MDCNFG)))
-#define MDCAS /* DRAM CAS shift reg. [0..3] */ \
+#define MDCAS /* DRAM CAS shift reg. [0..3] */ \
((volatile Word *) io_p2v (_MDCAS (0)))
-#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */
-#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */
-#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */
+#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */
+#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */
+#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */
#elif LANGUAGE == Assembly
@@ -1836,58 +1836,58 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
#endif /* LANGUAGE == C */
/* SA1100 MDCNFG values */
-#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
+#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
(0x00000001 << (Nb))
-#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */
-#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
-#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */
-#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */
-#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
-#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \
+#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */
+#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
+#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */
+#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */
+#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
+#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \
(((Add) - 9) << FShft (MDCNFG_DRAC))
#define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */
- /* (fcas = fcpu/2) */
+ /* (fcas = fcpu/2) */
#define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
-#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
+#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
(((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
-#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \
+#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \
(((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
-#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
-#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \
+#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
+#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \
(((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
-#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \
+#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \
(((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
-#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */
-#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \
+#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */
+#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \
((Tcpu) << FShft (MDCNFG_TDL))
#define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */
- /* [Tmem] */
-#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \
- /* [0..262136 Tcpu] */ \
+ /* [Tmem] */
+#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \
+ /* [0..262136 Tcpu] */ \
((Tcpu)/8 << FShft (MDCNFG_DRI))
/* SA1110 MDCNFG values */
-#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */
-#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
+#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */
+#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
#define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */
-#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
+#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
#define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */
- /* bank 0/1 */
+ /* bank 0/1 */
#define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
-#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
+#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
#define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/
- /* deassertion 0/1 */
+ /* deassertion 0/1 */
#define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
-#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */
-#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
+#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */
+#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
#define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */
-#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
+#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
#define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */
- /* bank 0/1 */
+ /* bank 0/1 */
#define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
-#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
+#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
#define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/
- /* deassertion 0/1 */
+ /* deassertion 0/1 */
#define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
@@ -1895,32 +1895,32 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
* Static memory control registers
*
* Registers
- * MSC0 Memory system: Static memory Control register 0
- * (read/write).
- * MSC1 Memory system: Static memory Control register 1
- * (read/write).
+ * MSC0 Memory system: Static memory Control register 0
+ * (read/write).
+ * MSC1 Memory system: Static memory Control register 1
+ * (read/write).
*
* Clocks
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
* fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
*/
- /* Memory system: */
-#define _MSC(Nb) /* Static memory Control reg. */ \
- /* [0..1] */ \
+ /* Memory system: */
+#define _MSC(Nb) /* Static memory Control reg. */ \
+ /* [0..1] */ \
(0xA0000010 + (Nb)*4)
-#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */
-#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */
+#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */
+#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */
#define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */
#if LANGUAGE == C
- /* Memory system: */
-#define MSC /* Static memory Control reg. */ \
- /* [0..1] */ \
+ /* Memory system: */
+#define MSC /* Static memory Control reg. */ \
+ /* [0..1] */ \
((volatile Word *) io_p2v (_MSC (0)))
-#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */
-#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */
-#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */
+#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */
+#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */
+#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */
#elif LANGUAGE == Assembly
@@ -1930,54 +1930,54 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
#endif /* LANGUAGE == C */
-#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \
+#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \
Fld (16, ((Nb) Modulo 2)*16)
-#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */
-#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */
-#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */
-#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */
+#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */
+#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */
+#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */
+#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */
-#define MSC_RT Fld (2, 0) /* ROM/static memory Type */
-#define MSC_NonBrst /* Non-Burst static memory */ \
+#define MSC_RT Fld (2, 0) /* ROM/static memory Type */
+#define MSC_NonBrst /* Non-Burst static memory */ \
(0 << FShft (MSC_RT))
-#define MSC_SRAM /* 32-bit byte-writable SRAM */ \
+#define MSC_SRAM /* 32-bit byte-writable SRAM */ \
(1 << FShft (MSC_RT))
-#define MSC_Brst4 /* Burst-of-4 static memory */ \
+#define MSC_Brst4 /* Burst-of-4 static memory */ \
(2 << FShft (MSC_RT))
-#define MSC_Brst8 /* Burst-of-8 static memory */ \
+#define MSC_Brst8 /* Burst-of-8 static memory */ \
(3 << FShft (MSC_RT))
-#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */
-#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
-#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
-#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
- /* First access - 1(.5) [Tmem] */
-#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
+#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */
+#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
+#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
+#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
+ /* First access - 1(.5) [Tmem] */
+#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
/* static memory) [3..65 Tcpu] */ \
((((Tcpu) - 3)/2) << FShft (MSC_RDF))
-#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
+#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MSC_RDF))
-#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
+#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
/* static memory) [2..64 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MSC_RDF))
-#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \
+#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \
((((Tcpu) - 1)/2) << FShft (MSC_RDF))
-#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
- /* Next access - 1 [Tmem] */
-#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
+#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
+ /* Next access - 1 [Tmem] */
+#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
/* static memory) [2..64 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MSC_RDN))
-#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \
+#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \
((((Tcpu) - 1)/2) << FShft (MSC_RDN))
-#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
+#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
/* static memory) [2..64 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MSC_RDN))
-#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \
+#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \
((((Tcpu) - 1)/2) << FShft (MSC_RDN))
-#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */
- /* time/2 [Tmem] */
-#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \
+#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */
+ /* time/2 [Tmem] */
+#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \
(((Tcpu)/4) << FShft (MSC_RRR))
-#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \
+#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \
((((Tcpu) + 3)/4) << FShft (MSC_RRR))
@@ -1986,8 +1986,8 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
* register
*
* Register
- * MECR Memory system: Expansion memory bus (PCMCIA)
- * Configuration Register (read/write).
+ * MECR Memory system: Expansion memory bus (PCMCIA)
+ * Configuration Register (read/write).
*
* Clocks
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
@@ -1995,37 +1995,37 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
* fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK).
*/
- /* Memory system: */
-#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */
- /* Configuration Reg. */
+ /* Memory system: */
+#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */
+ /* Configuration Reg. */
#if LANGUAGE == C
- /* Memory system: */
-#define MECR /* Expansion memory bus (PCMCIA) */ \
- /* Configuration Reg. */ \
+ /* Memory system: */
+#define MECR /* Expansion memory bus (PCMCIA) */ \
+ /* Configuration Reg. */ \
(*((volatile Word *) io_p2v (_MECR)))
#endif /* LANGUAGE == C */
-#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
+#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
Fld (15, (Nb)*16)
-#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */
-#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */
+#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */
+#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */
-#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
-#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \
+#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
+#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
-#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \
+#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \
((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
-#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
- /* [Tmem] */
-#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \
+#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
+ /* [Tmem] */
+#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MECR_BSA))
-#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \
+#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \
((((Tcpu) - 1)/2) << FShft (MECR_BSA))
#define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
-#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \
+#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MECR_BSM))
-#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \
+#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \
((((Tcpu) - 1)/2) << FShft (MECR_BSM))
/*
@@ -2035,7 +2035,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
#define _MDREFR 0xA000001C
#if LANGUAGE == C
- /* Memory system: */
+ /* Memory system: */
#define MDREFR \
(*((volatile Word *) io_p2v (_MDREFR)))
@@ -2064,769 +2064,769 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
* Direct Memory Access (DMA) control registers
*
* Registers
- * DDAR0 Direct Memory Access (DMA) Device Address Register
- * channel 0 (read/write).
- * DCSR0 Direct Memory Access (DMA) Control and Status
- * Register channel 0 (read/write).
- * DBSA0 Direct Memory Access (DMA) Buffer Start address
- * register A channel 0 (read/write).
- * DBTA0 Direct Memory Access (DMA) Buffer Transfer count
- * register A channel 0 (read/write).
- * DBSB0 Direct Memory Access (DMA) Buffer Start address
- * register B channel 0 (read/write).
- * DBTB0 Direct Memory Access (DMA) Buffer Transfer count
- * register B channel 0 (read/write).
+ * DDAR0 Direct Memory Access (DMA) Device Address Register
+ * channel 0 (read/write).
+ * DCSR0 Direct Memory Access (DMA) Control and Status
+ * Register channel 0 (read/write).
+ * DBSA0 Direct Memory Access (DMA) Buffer Start address
+ * register A channel 0 (read/write).
+ * DBTA0 Direct Memory Access (DMA) Buffer Transfer count
+ * register A channel 0 (read/write).
+ * DBSB0 Direct Memory Access (DMA) Buffer Start address
+ * register B channel 0 (read/write).
+ * DBTB0 Direct Memory Access (DMA) Buffer Transfer count
+ * register B channel 0 (read/write).
*
- * DDAR1 Direct Memory Access (DMA) Device Address Register
- * channel 1 (read/write).
- * DCSR1 Direct Memory Access (DMA) Control and Status
- * Register channel 1 (read/write).
- * DBSA1 Direct Memory Access (DMA) Buffer Start address
- * register A channel 1 (read/write).
- * DBTA1 Direct Memory Access (DMA) Buffer Transfer count
- * register A channel 1 (read/write).
- * DBSB1 Direct Memory Access (DMA) Buffer Start address
- * register B channel 1 (read/write).
- * DBTB1 Direct Memory Access (DMA) Buffer Transfer count
- * register B channel 1 (read/write).
+ * DDAR1 Direct Memory Access (DMA) Device Address Register
+ * channel 1 (read/write).
+ * DCSR1 Direct Memory Access (DMA) Control and Status
+ * Register channel 1 (read/write).
+ * DBSA1 Direct Memory Access (DMA) Buffer Start address
+ * register A channel 1 (read/write).
+ * DBTA1 Direct Memory Access (DMA) Buffer Transfer count
+ * register A channel 1 (read/write).
+ * DBSB1 Direct Memory Access (DMA) Buffer Start address
+ * register B channel 1 (read/write).
+ * DBTB1 Direct Memory Access (DMA) Buffer Transfer count
+ * register B channel 1 (read/write).
*
- * DDAR2 Direct Memory Access (DMA) Device Address Register
- * channel 2 (read/write).
- * DCSR2 Direct Memory Access (DMA) Control and Status
- * Register channel 2 (read/write).
- * DBSA2 Direct Memory Access (DMA) Buffer Start address
- * register A channel 2 (read/write).
- * DBTA2 Direct Memory Access (DMA) Buffer Transfer count
- * register A channel 2 (read/write).
- * DBSB2 Direct Memory Access (DMA) Buffer Start address
- * register B channel 2 (read/write).
- * DBTB2 Direct Memory Access (DMA) Buffer Transfer count
- * register B channel 2 (read/write).
+ * DDAR2 Direct Memory Access (DMA) Device Address Register
+ * channel 2 (read/write).
+ * DCSR2 Direct Memory Access (DMA) Control and Status
+ * Register channel 2 (read/write).
+ * DBSA2 Direct Memory Access (DMA) Buffer Start address
+ * register A channel 2 (read/write).
+ * DBTA2 Direct Memory Access (DMA) Buffer Transfer count
+ * register A channel 2 (read/write).
+ * DBSB2 Direct Memory Access (DMA) Buffer Start address
+ * register B channel 2 (read/write).
+ * DBTB2 Direct Memory Access (DMA) Buffer Transfer count
+ * register B channel 2 (read/write).
*
- * DDAR3 Direct Memory Access (DMA) Device Address Register
- * channel 3 (read/write).
- * DCSR3 Direct Memory Access (DMA) Control and Status
- * Register channel 3 (read/write).
- * DBSA3 Direct Memory Access (DMA) Buffer Start address
- * register A channel 3 (read/write).
- * DBTA3 Direct Memory Access (DMA) Buffer Transfer count
- * register A channel 3 (read/write).
- * DBSB3 Direct Memory Access (DMA) Buffer Start address
- * register B channel 3 (read/write).
- * DBTB3 Direct Memory Access (DMA) Buffer Transfer count
- * register B channel 3 (read/write).
+ * DDAR3 Direct Memory Access (DMA) Device Address Register
+ * channel 3 (read/write).
+ * DCSR3 Direct Memory Access (DMA) Control and Status
+ * Register channel 3 (read/write).
+ * DBSA3 Direct Memory Access (DMA) Buffer Start address
+ * register A channel 3 (read/write).
+ * DBTA3 Direct Memory Access (DMA) Buffer Transfer count
+ * register A channel 3 (read/write).
+ * DBSB3 Direct Memory Access (DMA) Buffer Start address
+ * register B channel 3 (read/write).
+ * DBTB3 Direct Memory Access (DMA) Buffer Transfer count
+ * register B channel 3 (read/write).
*
- * DDAR4 Direct Memory Access (DMA) Device Address Register
- * channel 4 (read/write).
- * DCSR4 Direct Memory Access (DMA) Control and Status
- * Register channel 4 (read/write).
- * DBSA4 Direct Memory Access (DMA) Buffer Start address
- * register A channel 4 (read/write).
- * DBTA4 Direct Memory Access (DMA) Buffer Transfer count
- * register A channel 4 (read/write).
- * DBSB4 Direct Memory Access (DMA) Buffer Start address
- * register B channel 4 (read/write).
- * DBTB4 Direct Memory Access (DMA) Buffer Transfer count
- * register B channel 4 (read/write).
+ * DDAR4 Direct Memory Access (DMA) Device Address Register
+ * channel 4 (read/write).
+ * DCSR4 Direct Memory Access (DMA) Control and Status
+ * Register channel 4 (read/write).
+ * DBSA4 Direct Memory Access (DMA) Buffer Start address
+ * register A channel 4 (read/write).
+ * DBTA4 Direct Memory Access (DMA) Buffer Transfer count
+ * register A channel 4 (read/write).
+ * DBSB4 Direct Memory Access (DMA) Buffer Start address
+ * register B channel 4 (read/write).
+ * DBTB4 Direct Memory Access (DMA) Buffer Transfer count
+ * register B channel 4 (read/write).
*
- * DDAR5 Direct Memory Access (DMA) Device Address Register
- * channel 5 (read/write).
- * DCSR5 Direct Memory Access (DMA) Control and Status
- * Register channel 5 (read/write).
- * DBSA5 Direct Memory Access (DMA) Buffer Start address
- * register A channel 5 (read/write).
- * DBTA5 Direct Memory Access (DMA) Buffer Transfer count
- * register A channel 5 (read/write).
- * DBSB5 Direct Memory Access (DMA) Buffer Start address
- * register B channel 5 (read/write).
- * DBTB5 Direct Memory Access (DMA) Buffer Transfer count
- * register B channel 5 (read/write).
+ * DDAR5 Direct Memory Access (DMA) Device Address Register
+ * channel 5 (read/write).
+ * DCSR5 Direct Memory Access (DMA) Control and Status
+ * Register channel 5 (read/write).
+ * DBSA5 Direct Memory Access (DMA) Buffer Start address
+ * register A channel 5 (read/write).
+ * DBTA5 Direct Memory Access (DMA) Buffer Transfer count
+ * register A channel 5 (read/write).
+ * DBSB5 Direct Memory Access (DMA) Buffer Start address
+ * register B channel 5 (read/write).
+ * DBTB5 Direct Memory Access (DMA) Buffer Transfer count
+ * register B channel 5 (read/write).
*/
-#define DMASp 0x00000020 /* DMA control reg. Space [byte] */
+#define DMASp 0x00000020 /* DMA control reg. Space [byte] */
-#define _DDAR(Nb) /* DMA Device Address Reg. */ \
- /* channel [0..5] */ \
+#define _DDAR(Nb) /* DMA Device Address Reg. */ \
+ /* channel [0..5] */ \
(0xB0000000 + (Nb)*DMASp)
-#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \
- /* channel [0..5] (write) */ \
+#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \
+ /* channel [0..5] (write) */ \
(0xB0000004 + (Nb)*DMASp)
-#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \
- /* channel [0..5] (write) */ \
+#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \
+ /* channel [0..5] (write) */ \
(0xB0000008 + (Nb)*DMASp)
-#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \
- /* channel [0..5] (read) */ \
+#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \
+ /* channel [0..5] (read) */ \
(0xB000000C + (Nb)*DMASp)
-#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \
- /* channel [0..5] */ \
+#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \
+ /* channel [0..5] */ \
(0xB0000010 + (Nb)*DMASp)
-#define _DBTA(Nb) /* DMA Buffer Transfer count */ \
- /* reg. A channel [0..5] */ \
+#define _DBTA(Nb) /* DMA Buffer Transfer count */ \
+ /* reg. A channel [0..5] */ \
(0xB0000014 + (Nb)*DMASp)
-#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \
- /* channel [0..5] */ \
+#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \
+ /* channel [0..5] */ \
(0xB0000018 + (Nb)*DMASp)
-#define _DBTB(Nb) /* DMA Buffer Transfer count */ \
- /* reg. B channel [0..5] */ \
+#define _DBTB(Nb) /* DMA Buffer Transfer count */ \
+ /* reg. B channel [0..5] */ \
(0xB000001C + (Nb)*DMASp)
-#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */
- /* channel 0 */
+#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */
+ /* channel 0 */
#define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */
- /* channel 0 (write) */
+ /* channel 0 (write) */
#define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */
- /* channel 0 (write) */
+ /* channel 0 (write) */
#define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */
- /* channel 0 (read) */
-#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */
- /* channel 0 */
-#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */
- /* reg. A channel 0 */
-#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */
- /* channel 0 */
-#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */
- /* reg. B channel 0 */
-
-#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */
- /* channel 1 */
+ /* channel 0 (read) */
+#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */
+ /* channel 0 */
+#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */
+ /* reg. A channel 0 */
+#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */
+ /* channel 0 */
+#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */
+ /* reg. B channel 0 */
+
+#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */
+ /* channel 1 */
#define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */
- /* channel 1 (write) */
+ /* channel 1 (write) */
#define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */
- /* channel 1 (write) */
+ /* channel 1 (write) */
#define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */
- /* channel 1 (read) */
-#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */
- /* channel 1 */
-#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */
- /* reg. A channel 1 */
-#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */
- /* channel 1 */
-#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */
- /* reg. B channel 1 */
-
-#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */
- /* channel 2 */
+ /* channel 1 (read) */
+#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */
+ /* channel 1 */
+#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */
+ /* reg. A channel 1 */
+#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */
+ /* channel 1 */
+#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */
+ /* reg. B channel 1 */
+
+#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */
+ /* channel 2 */
#define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */
- /* channel 2 (write) */
+ /* channel 2 (write) */
#define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */
- /* channel 2 (write) */
+ /* channel 2 (write) */
#define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */
- /* channel 2 (read) */
-#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */
- /* channel 2 */
-#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */
- /* reg. A channel 2 */
-#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */
- /* channel 2 */
-#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */
- /* reg. B channel 2 */
-
-#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */
- /* channel 3 */
+ /* channel 2 (read) */
+#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */
+ /* channel 2 */
+#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */
+ /* reg. A channel 2 */
+#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */
+ /* channel 2 */
+#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */
+ /* reg. B channel 2 */
+
+#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */
+ /* channel 3 */
#define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */
- /* channel 3 (write) */
+ /* channel 3 (write) */
#define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */
- /* channel 3 (write) */
+ /* channel 3 (write) */
#define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */
- /* channel 3 (read) */
-#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */
- /* channel 3 */
-#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */
- /* reg. A channel 3 */
-#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */
- /* channel 3 */
-#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */
- /* reg. B channel 3 */
-
-#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */
- /* channel 4 */
+ /* channel 3 (read) */
+#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */
+ /* channel 3 */
+#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */
+ /* reg. A channel 3 */
+#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */
+ /* channel 3 */
+#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */
+ /* reg. B channel 3 */
+
+#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */
+ /* channel 4 */
#define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */
- /* channel 4 (write) */
+ /* channel 4 (write) */
#define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */
- /* channel 4 (write) */
+ /* channel 4 (write) */
#define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */
- /* channel 4 (read) */
-#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */
- /* channel 4 */
-#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */
- /* reg. A channel 4 */
-#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */
- /* channel 4 */
-#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */
- /* reg. B channel 4 */
-
-#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */
- /* channel 5 */
+ /* channel 4 (read) */
+#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */
+ /* channel 4 */
+#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */
+ /* reg. A channel 4 */
+#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */
+ /* channel 4 */
+#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */
+ /* reg. B channel 4 */
+
+#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */
+ /* channel 5 */
#define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */
- /* channel 5 (write) */
+ /* channel 5 (write) */
#define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */
- /* channel 5 (write) */
+ /* channel 5 (write) */
#define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */
- /* channel 5 (read) */
-#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */
- /* channel 5 */
-#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */
- /* reg. A channel 5 */
-#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */
- /* channel 5 */
-#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */
- /* reg. B channel 5 */
+ /* channel 5 (read) */
+#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */
+ /* channel 5 */
+#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */
+ /* reg. A channel 5 */
+#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */
+ /* channel 5 */
+#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */
+ /* reg. B channel 5 */
#if LANGUAGE == C
-#define DDAR0 /* DMA Device Address Reg. */ \
- /* channel 0 */ \
+#define DDAR0 /* DMA Device Address Reg. */ \
+ /* channel 0 */ \
(*((volatile Word *) io_p2v (_DDAR0)))
-#define SetDCSR0 /* Set DMA Control & Status Reg. */ \
- /* channel 0 (write) */ \
+#define SetDCSR0 /* Set DMA Control & Status Reg. */ \
+ /* channel 0 (write) */ \
(*((volatile Word *) io_p2v (_SetDCSR0)))
-#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \
- /* channel 0 (write) */ \
+#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \
+ /* channel 0 (write) */ \
(*((volatile Word *) io_p2v (_ClrDCSR0)))
-#define RdDCSR0 /* Read DMA Control & Status Reg. */ \
- /* channel 0 (read) */ \
+#define RdDCSR0 /* Read DMA Control & Status Reg. */ \
+ /* channel 0 (read) */ \
(*((volatile Word *) io_p2v (_RdDCSR0)))
-#define DBSA0 /* DMA Buffer Start address reg. A */ \
- /* channel 0 */ \
+#define DBSA0 /* DMA Buffer Start address reg. A */ \
+ /* channel 0 */ \
(*((volatile Address *) io_p2v (_DBSA0)))
-#define DBTA0 /* DMA Buffer Transfer count */ \
- /* reg. A channel 0 */ \
+#define DBTA0 /* DMA Buffer Transfer count */ \
+ /* reg. A channel 0 */ \
(*((volatile Word *) io_p2v (_DBTA0)))
-#define DBSB0 /* DMA Buffer Start address reg. B */ \
- /* channel 0 */ \
+#define DBSB0 /* DMA Buffer Start address reg. B */ \
+ /* channel 0 */ \
(*((volatile Address *) io_p2v (_DBSB0)))
-#define DBTB0 /* DMA Buffer Transfer count */ \
- /* reg. B channel 0 */ \
+#define DBTB0 /* DMA Buffer Transfer count */ \
+ /* reg. B channel 0 */ \
(*((volatile Word *) io_p2v (_DBTB0)))
-#define DDAR1 /* DMA Device Address Reg. */ \
- /* channel 1 */ \
+#define DDAR1 /* DMA Device Address Reg. */ \
+ /* channel 1 */ \
(*((volatile Word *) io_p2v (_DDAR1)))
-#define SetDCSR1 /* Set DMA Control & Status Reg. */ \
- /* channel 1 (write) */ \
+#define SetDCSR1 /* Set DMA Control & Status Reg. */ \
+ /* channel 1 (write) */ \
(*((volatile Word *) io_p2v (_SetDCSR1)))
-#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \
- /* channel 1 (write) */ \
+#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \
+ /* channel 1 (write) */ \
(*((volatile Word *) io_p2v (_ClrDCSR1)))
-#define RdDCSR1 /* Read DMA Control & Status Reg. */ \
- /* channel 1 (read) */ \
+#define RdDCSR1 /* Read DMA Control & Status Reg. */ \
+ /* channel 1 (read) */ \
(*((volatile Word *) io_p2v (_RdDCSR1)))
-#define DBSA1 /* DMA Buffer Start address reg. A */ \
- /* channel 1 */ \
+#define DBSA1 /* DMA Buffer Start address reg. A */ \
+ /* channel 1 */ \
(*((volatile Address *) io_p2v (_DBSA1)))
-#define DBTA1 /* DMA Buffer Transfer count */ \
- /* reg. A channel 1 */ \
+#define DBTA1 /* DMA Buffer Transfer count */ \
+ /* reg. A channel 1 */ \
(*((volatile Word *) io_p2v (_DBTA1)))
-#define DBSB1 /* DMA Buffer Start address reg. B */ \
- /* channel 1 */ \
+#define DBSB1 /* DMA Buffer Start address reg. B */ \
+ /* channel 1 */ \
(*((volatile Address *) io_p2v (_DBSB1)))
-#define DBTB1 /* DMA Buffer Transfer count */ \
- /* reg. B channel 1 */ \
+#define DBTB1 /* DMA Buffer Transfer count */ \
+ /* reg. B channel 1 */ \
(*((volatile Word *) io_p2v (_DBTB1)))
-#define DDAR2 /* DMA Device Address Reg. */ \
- /* channel 2 */ \
+#define DDAR2 /* DMA Device Address Reg. */ \
+ /* channel 2 */ \
(*((volatile Word *) io_p2v (_DDAR2)))
-#define SetDCSR2 /* Set DMA Control & Status Reg. */ \
- /* channel 2 (write) */ \
+#define SetDCSR2 /* Set DMA Control & Status Reg. */ \
+ /* channel 2 (write) */ \
(*((volatile Word *) io_p2v (_SetDCSR2)))
-#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \
- /* channel 2 (write) */ \
+#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \
+ /* channel 2 (write) */ \
(*((volatile Word *) io_p2v (_ClrDCSR2)))
-#define RdDCSR2 /* Read DMA Control & Status Reg. */ \
- /* channel 2 (read) */ \
+#define RdDCSR2 /* Read DMA Control & Status Reg. */ \
+ /* channel 2 (read) */ \
(*((volatile Word *) io_p2v (_RdDCSR2)))
-#define DBSA2 /* DMA Buffer Start address reg. A */ \
- /* channel 2 */ \
+#define DBSA2 /* DMA Buffer Start address reg. A */ \
+ /* channel 2 */ \
(*((volatile Address *) io_p2v (_DBSA2)))
-#define DBTA2 /* DMA Buffer Transfer count */ \
- /* reg. A channel 2 */ \
+#define DBTA2 /* DMA Buffer Transfer count */ \
+ /* reg. A channel 2 */ \
(*((volatile Word *) io_p2v (_DBTA2)))
-#define DBSB2 /* DMA Buffer Start address reg. B */ \
- /* channel 2 */ \
+#define DBSB2 /* DMA Buffer Start address reg. B */ \
+ /* channel 2 */ \
(*((volatile Address *) io_p2v (_DBSB2)))
-#define DBTB2 /* DMA Buffer Transfer count */ \
- /* reg. B channel 2 */ \
+#define DBTB2 /* DMA Buffer Transfer count */ \
+ /* reg. B channel 2 */ \
(*((volatile Word *) io_p2v (_DBTB2)))
-#define DDAR3 /* DMA Device Address Reg. */ \
- /* channel 3 */ \
+#define DDAR3 /* DMA Device Address Reg. */ \
+ /* channel 3 */ \
(*((volatile Word *) io_p2v (_DDAR3)))
-#define SetDCSR3 /* Set DMA Control & Status Reg. */ \
- /* channel 3 (write) */ \
+#define SetDCSR3 /* Set DMA Control & Status Reg. */ \
+ /* channel 3 (write) */ \
(*((volatile Word *) io_p2v (_SetDCSR3)))
-#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \
- /* channel 3 (write) */ \
+#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \
+ /* channel 3 (write) */ \
(*((volatile Word *) io_p2v (_ClrDCSR3)))
-#define RdDCSR3 /* Read DMA Control & Status Reg. */ \
- /* channel 3 (read) */ \
+#define RdDCSR3 /* Read DMA Control & Status Reg. */ \
+ /* channel 3 (read) */ \
(*((volatile Word *) io_p2v (_RdDCSR3)))
-#define DBSA3 /* DMA Buffer Start address reg. A */ \
- /* channel 3 */ \
+#define DBSA3 /* DMA Buffer Start address reg. A */ \
+ /* channel 3 */ \
(*((volatile Address *) io_p2v (_DBSA3)))
-#define DBTA3 /* DMA Buffer Transfer count */ \
- /* reg. A channel 3 */ \
+#define DBTA3 /* DMA Buffer Transfer count */ \
+ /* reg. A channel 3 */ \
(*((volatile Word *) io_p2v (_DBTA3)))
-#define DBSB3 /* DMA Buffer Start address reg. B */ \
- /* channel 3 */ \
+#define DBSB3 /* DMA Buffer Start address reg. B */ \
+ /* channel 3 */ \
(*((volatile Address *) io_p2v (_DBSB3)))
-#define DBTB3 /* DMA Buffer Transfer count */ \
- /* reg. B channel 3 */ \
+#define DBTB3 /* DMA Buffer Transfer count */ \
+ /* reg. B channel 3 */ \
(*((volatile Word *) io_p2v (_DBTB3)))
-#define DDAR4 /* DMA Device Address Reg. */ \
- /* channel 4 */ \
+#define DDAR4 /* DMA Device Address Reg. */ \
+ /* channel 4 */ \
(*((volatile Word *) io_p2v (_DDAR4)))
-#define SetDCSR4 /* Set DMA Control & Status Reg. */ \
- /* channel 4 (write) */ \
+#define SetDCSR4 /* Set DMA Control & Status Reg. */ \
+ /* channel 4 (write) */ \
(*((volatile Word *) io_p2v (_SetDCSR4)))
-#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \
- /* channel 4 (write) */ \
+#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \
+ /* channel 4 (write) */ \
(*((volatile Word *) io_p2v (_ClrDCSR4)))
-#define RdDCSR4 /* Read DMA Control & Status Reg. */ \
- /* channel 4 (read) */ \
+#define RdDCSR4 /* Read DMA Control & Status Reg. */ \
+ /* channel 4 (read) */ \
(*((volatile Word *) io_p2v (_RdDCSR4)))
-#define DBSA4 /* DMA Buffer Start address reg. A */ \
- /* channel 4 */ \
+#define DBSA4 /* DMA Buffer Start address reg. A */ \
+ /* channel 4 */ \
(*((volatile Address *) io_p2v (_DBSA4)))
-#define DBTA4 /* DMA Buffer Transfer count */ \
- /* reg. A channel 4 */ \
+#define DBTA4 /* DMA Buffer Transfer count */ \
+ /* reg. A channel 4 */ \
(*((volatile Word *) io_p2v (_DBTA4)))
-#define DBSB4 /* DMA Buffer Start address reg. B */ \
- /* channel 4 */ \
+#define DBSB4 /* DMA Buffer Start address reg. B */ \
+ /* channel 4 */ \
(*((volatile Address *) io_p2v (_DBSB4)))
-#define DBTB4 /* DMA Buffer Transfer count */ \
- /* reg. B channel 4 */ \
+#define DBTB4 /* DMA Buffer Transfer count */ \
+ /* reg. B channel 4 */ \
(*((volatile Word *) io_p2v (_DBTB4)))
-#define DDAR5 /* DMA Device Address Reg. */ \
- /* channel 5 */ \
+#define DDAR5 /* DMA Device Address Reg. */ \
+ /* channel 5 */ \
(*((volatile Word *) io_p2v (_DDAR5)))
-#define SetDCSR5 /* Set DMA Control & Status Reg. */ \
- /* channel 5 (write) */ \
+#define SetDCSR5 /* Set DMA Control & Status Reg. */ \
+ /* channel 5 (write) */ \
(*((volatile Word *) io_p2v (_SetDCSR5)))
-#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \
- /* channel 5 (write) */ \
+#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \
+ /* channel 5 (write) */ \
(*((volatile Word *) io_p2v (_ClrDCSR5)))
-#define RdDCSR5 /* Read DMA Control & Status Reg. */ \
- /* channel 5 (read) */ \
+#define RdDCSR5 /* Read DMA Control & Status Reg. */ \
+ /* channel 5 (read) */ \
(*((volatile Word *) io_p2v (_RdDCSR5)))
-#define DBSA5 /* DMA Buffer Start address reg. A */ \
- /* channel 5 */ \
+#define DBSA5 /* DMA Buffer Start address reg. A */ \
+ /* channel 5 */ \
(*((volatile Address *) io_p2v (_DBSA5)))
-#define DBTA5 /* DMA Buffer Transfer count */ \
- /* reg. A channel 5 */ \
+#define DBTA5 /* DMA Buffer Transfer count */ \
+ /* reg. A channel 5 */ \
(*((volatile Word *) io_p2v (_DBTA5)))
-#define DBSB5 /* DMA Buffer Start address reg. B */ \
- /* channel 5 */ \
+#define DBSB5 /* DMA Buffer Start address reg. B */ \
+ /* channel 5 */ \
(*((volatile Address *) io_p2v (_DBSB5)))
-#define DBTB5 /* DMA Buffer Transfer count */ \
- /* reg. B channel 5 */ \
+#define DBTB5 /* DMA Buffer Transfer count */ \
+ /* reg. B channel 5 */ \
(*((volatile Word *) io_p2v (_DBTB5)))
#endif /* LANGUAGE == C */
-#define DDAR_RW 0x00000001 /* device data Read/Write */
-#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
- /* (memory -> device) */
-#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
- /* (device -> memory) */
-#define DDAR_E 0x00000002 /* big/little Endian device */
-#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */
-#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
-#define DDAR_BS 0x00000004 /* device Burst Size */
-#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
-#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
-#define DDAR_DW 0x00000008 /* device Data Width */
-#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
-#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
-#define DDAR_DS Fld (4, 4) /* Device Select */
-#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \
+#define DDAR_RW 0x00000001 /* device data Read/Write */
+#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
+ /* (memory -> device) */
+#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
+ /* (device -> memory) */
+#define DDAR_E 0x00000002 /* big/little Endian device */
+#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */
+#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
+#define DDAR_BS 0x00000004 /* device Burst Size */
+#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
+#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
+#define DDAR_DW 0x00000008 /* device Data Width */
+#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
+#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
+#define DDAR_DS Fld (4, 4) /* Device Select */
+#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \
(0x0 << FShft (DDAR_DS))
-#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \
+#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \
(0x1 << FShft (DDAR_DS))
-#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
+#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
(0x2 << FShft (DDAR_DS))
-#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
+#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
(0x3 << FShft (DDAR_DS))
-#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
+#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
(0x4 << FShft (DDAR_DS))
-#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
+#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
(0x5 << FShft (DDAR_DS))
-#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \
+#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \
(0x6 << FShft (DDAR_DS))
-#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \
+#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \
(0x7 << FShft (DDAR_DS))
-#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \
+#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \
(0x8 << FShft (DDAR_DS))
-#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \
+#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \
(0x9 << FShft (DDAR_DS))
-#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \
- /* (audio) */ \
+#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \
+ /* (audio) */ \
(0xA << FShft (DDAR_DS))
-#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \
- /* (audio) */ \
+#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \
+ /* (audio) */ \
(0xB << FShft (DDAR_DS))
-#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
- /* (telecom) */ \
+#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
+ /* (telecom) */ \
(0xC << FShft (DDAR_DS))
-#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
- /* (telecom) */ \
+#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
+ /* (telecom) */ \
(0xD << FShft (DDAR_DS))
-#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \
+#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \
(0xE << FShft (DDAR_DS))
-#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \
+#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \
(0xF << FShft (DDAR_DS))
-#define DDAR_DA Fld (24, 8) /* Device Address */
-#define DDAR_DevAdd(Add) /* Device Address */ \
+#define DDAR_DA Fld (24, 8) /* Device Address */
+#define DDAR_DevAdd(Add) /* Device Address */ \
(((Add) & 0xF0000000) | \
(((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
-#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
+#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR))
-#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
+#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR))
-#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
+#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR))
-#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
+#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR))
-#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
+#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR))
-#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
+#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR))
-#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
+#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR))
-#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
+#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR))
-#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
+#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR))
-#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
+#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR))
-#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
+#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR))
-#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
+#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR))
-#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
+#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0))
-#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
+#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0))
-#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
- /* (telecom) */ \
+#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
+ /* (telecom) */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1))
-#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
- /* (telecom) */ \
+#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
+ /* (telecom) */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1))
-#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
+#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR))
-#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
+#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR))
-#define DCSR_RUN 0x00000001 /* DMA RUNing */
-#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
-#define DCSR_ERROR 0x00000004 /* DMA ERROR */
-#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
+#define DCSR_RUN 0x00000001 /* DMA RUNing */
+#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
+#define DCSR_ERROR 0x00000004 /* DMA ERROR */
+#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */
-#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */
+#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */
#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */
-#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */
-#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */
-#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
+#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */
+#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */
+#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
-#define DBT_TC Fld (13, 0) /* Transfer Count */
-#define DBTA_TCA DBT_TC /* Transfer Count buffer A */
-#define DBTB_TCB DBT_TC /* Transfer Count buffer B */
+#define DBT_TC Fld (13, 0) /* Transfer Count */
+#define DBTA_TCA DBT_TC /* Transfer Count buffer A */
+#define DBTB_TCB DBT_TC /* Transfer Count buffer B */
/*
* Liquid Crystal Display (LCD) control registers
*
* Registers
- * LCCR0 Liquid Crystal Display (LCD) Control Register 0
- * (read/write).
- * [Bits LDM, BAM, and ERM are only implemented in
- * versions 2.0 (rev. = 8) and higher of the StrongARM
- * SA-1100.]
- * LCSR Liquid Crystal Display (LCD) Status Register
- * (read/write).
- * [Bit LDD can be only read in versions 1.0 (rev. = 1)
- * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
- * read and written (cleared) in versions 2.0 (rev. = 8)
- * and higher.]
- * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access
- * (DMA) Base Address Register channel 1 (read/write).
- * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access
- * (DMA) Current Address Register channel 1 (read).
- * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access
- * (DMA) Base Address Register channel 2 (read/write).
- * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access
- * (DMA) Current Address Register channel 2 (read).
- * LCCR1 Liquid Crystal Display (LCD) Control Register 1
- * (read/write).
- * [The LCCR1 register can be only written in
- * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
- * StrongARM SA-1100, it can be written and read in
- * versions 2.0 (rev. = 8) and higher.]
- * LCCR2 Liquid Crystal Display (LCD) Control Register 2
- * (read/write).
- * [The LCCR1 register can be only written in
- * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
- * StrongARM SA-1100, it can be written and read in
- * versions 2.0 (rev. = 8) and higher.]
- * LCCR3 Liquid Crystal Display (LCD) Control Register 3
- * (read/write).
- * [The LCCR1 register can be only written in
- * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
- * StrongARM SA-1100, it can be written and read in
- * versions 2.0 (rev. = 8) and higher. Bit PCP is only
- * implemented in versions 2.0 (rev. = 8) and higher of
- * the StrongARM SA-1100.]
+ * LCCR0 Liquid Crystal Display (LCD) Control Register 0
+ * (read/write).
+ * [Bits LDM, BAM, and ERM are only implemented in
+ * versions 2.0 (rev. = 8) and higher of the StrongARM
+ * SA-1100.]
+ * LCSR Liquid Crystal Display (LCD) Status Register
+ * (read/write).
+ * [Bit LDD can be only read in versions 1.0 (rev. = 1)
+ * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
+ * read and written (cleared) in versions 2.0 (rev. = 8)
+ * and higher.]
+ * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access
+ * (DMA) Base Address Register channel 1 (read/write).
+ * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access
+ * (DMA) Current Address Register channel 1 (read).
+ * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access
+ * (DMA) Base Address Register channel 2 (read/write).
+ * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access
+ * (DMA) Current Address Register channel 2 (read).
+ * LCCR1 Liquid Crystal Display (LCD) Control Register 1
+ * (read/write).
+ * [The LCCR1 register can be only written in
+ * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ * StrongARM SA-1100, it can be written and read in
+ * versions 2.0 (rev. = 8) and higher.]
+ * LCCR2 Liquid Crystal Display (LCD) Control Register 2
+ * (read/write).
+ * [The LCCR1 register can be only written in
+ * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ * StrongARM SA-1100, it can be written and read in
+ * versions 2.0 (rev. = 8) and higher.]
+ * LCCR3 Liquid Crystal Display (LCD) Control Register 3
+ * (read/write).
+ * [The LCCR1 register can be only written in
+ * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ * StrongARM SA-1100, it can be written and read in
+ * versions 2.0 (rev. = 8) and higher. Bit PCP is only
+ * implemented in versions 2.0 (rev. = 8) and higher of
+ * the StrongARM SA-1100.]
*
* Clocks
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
* fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
* fpix, Tpix Frequency, period of the pixel clock.
- * fln, Tln Frequency, period of the line clock.
- * fac, Tac Frequency, period of the AC bias clock.
+ * fln, Tln Frequency, period of the line clock.
+ * fac, Tac Frequency, period of the AC bias clock.
*/
-#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */
-#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
- /* [byte] */ \
+#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */
+#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
+ /* [byte] */ \
(16*LCD_PEntrySp)
-#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
- /* [byte] */ \
+#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
+ /* [byte] */ \
(256*LCD_PEntrySp)
-#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
- /* dummy-Palette Space [byte] */ \
+#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
+ /* dummy-Palette Space [byte] */ \
(16*LCD_PEntrySp)
#define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */
#define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */
#define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */
-#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */
-#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */
-#define LCD_4Bit /* LCD 4-Bit pixel mode */ \
+#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */
+#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */
+#define LCD_4Bit /* LCD 4-Bit pixel mode */ \
(0 << FShft (LCD_PBS))
-#define LCD_8Bit /* LCD 8-Bit pixel mode */ \
+#define LCD_8Bit /* LCD 8-Bit pixel mode */ \
(1 << FShft (LCD_PBS))
-#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
+#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
(2 << FShft (LCD_PBS))
-#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */
-#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
-#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
-#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */
-#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */
-#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */
-#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */
-#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
-#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */
-#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */
-#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */
-#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */
-#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */
-#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */
-#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
-#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
- /* (Alternative) */
-
-#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */
-#define _LCSR 0xB0100004 /* LCD Status Reg. */
-#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */
- /* channel 1 */
-#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */
- /* channel 1 */
-#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */
- /* channel 2 */
-#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */
- /* channel 2 */
-#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */
-#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */
-#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */
+#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */
+#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
+#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
+#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */
+#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */
+#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */
+#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */
+#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
+#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */
+#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */
+#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */
+#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */
+#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */
+#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */
+#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
+#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
+ /* (Alternative) */
+
+#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */
+#define _LCSR 0xB0100004 /* LCD Status Reg. */
+#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */
+ /* channel 1 */
+#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */
+ /* channel 1 */
+#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */
+ /* channel 2 */
+#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */
+ /* channel 2 */
+#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */
+#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */
+#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */
#if LANGUAGE == C
-#define LCCR0 /* LCD Control Reg. 0 */ \
+#define LCCR0 /* LCD Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_LCCR0)))
-#define LCSR /* LCD Status Reg. */ \
+#define LCSR /* LCD Status Reg. */ \
(*((volatile Word *) io_p2v (_LCSR)))
-#define DBAR1 /* LCD DMA Base Address Reg. */ \
- /* channel 1 */ \
+#define DBAR1 /* LCD DMA Base Address Reg. */ \
+ /* channel 1 */ \
(*((volatile Address *) io_p2v (_DBAR1)))
-#define DCAR1 /* LCD DMA Current Address Reg. */ \
- /* channel 1 */ \
+#define DCAR1 /* LCD DMA Current Address Reg. */ \
+ /* channel 1 */ \
(*((volatile Address *) io_p2v (_DCAR1)))
-#define DBAR2 /* LCD DMA Base Address Reg. */ \
- /* channel 2 */ \
+#define DBAR2 /* LCD DMA Base Address Reg. */ \
+ /* channel 2 */ \
(*((volatile Address *) io_p2v (_DBAR2)))
-#define DCAR2 /* LCD DMA Current Address Reg. */ \
- /* channel 2 */ \
+#define DCAR2 /* LCD DMA Current Address Reg. */ \
+ /* channel 2 */ \
(*((volatile Address *) io_p2v (_DCAR2)))
-#define LCCR1 /* LCD Control Reg. 1 */ \
+#define LCCR1 /* LCD Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_LCCR1)))
-#define LCCR2 /* LCD Control Reg. 2 */ \
+#define LCCR2 /* LCD Control Reg. 2 */ \
(*((volatile Word *) io_p2v (_LCCR2)))
-#define LCCR3 /* LCD Control Reg. 3 */ \
+#define LCCR3 /* LCD Control Reg. 3 */ \
(*((volatile Word *) io_p2v (_LCCR3)))
#endif /* LANGUAGE == C */
-#define LCCR0_LEN 0x00000001 /* LCD ENable */
+#define LCCR0_LEN 0x00000001 /* LCD ENable */
#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
-#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
-#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
-#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */
- /* Select */
-#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
-#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
-#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */
- /* interrupt Mask (disable) */
-#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
- /* interrupt Mask (disable) */
+#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
+#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
+#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */
+ /* Select */
+#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
+#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
+#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */
+ /* interrupt Mask (disable) */
+#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
+ /* interrupt Mask (disable) */
#define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */
/* IUU, OOL, OUL, OOU, and OUU) */
- /* interrupt Mask (disable) */
+ /* interrupt Mask (disable) */
#define LCCR0_PAS 0x00000080 /* Passive/Active display Select */
-#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
-#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
-#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */
-#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */
-#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
+#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
+#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
+#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */
+#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */
+#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
#define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */
- /* display mode) */
-#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
- /* display */
-#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
- /* display */
-#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */
- /* [Tmem] */
-#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \
- /* [0..510 Tcpu] */ \
+ /* display mode) */
+#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
+ /* display */
+#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
+ /* display */
+#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */
+ /* [Tmem] */
+#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \
+ /* [0..510 Tcpu] */ \
((Tcpu)/2 << FShft (LCCR0_PDD))
-#define LCSR_LDD 0x00000001 /* LCD Disable Done */
-#define LCSR_BAU 0x00000002 /* Base Address Update (read) */
-#define LCSR_BER 0x00000004 /* Bus ERror */
-#define LCSR_ABC 0x00000008 /* AC Bias clock Count */
-#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
- /* panel */
-#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
- /* panel */
-#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
- /* panel */
-#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
- /* panel */
-#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
- /* panel */
-#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
- /* panel */
-#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
- /* panel */
-#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
- /* panel */
-
-#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
-#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \
+#define LCSR_LDD 0x00000001 /* LCD Disable Done */
+#define LCSR_BAU 0x00000002 /* Base Address Update (read) */
+#define LCSR_BER 0x00000004 /* Bus ERror */
+#define LCSR_ABC 0x00000008 /* AC Bias clock Count */
+#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
+ /* panel */
+#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
+ /* panel */
+#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
+ /* panel */
+#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
+ /* panel */
+#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
+ /* panel */
+#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
+ /* panel */
+#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
+ /* panel */
+#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
+ /* panel */
+
+#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
+#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \
(((Pixel) - 16)/16 << FShft (LCCR1_PPL))
-#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
+#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
/* pulse Width - 2 [Tpix] (L_LCLK) */
-#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
- /* pulse Width [2..65 Tpix] */ \
+#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
+ /* pulse Width [2..65 Tpix] */ \
(((Tpix) - 2) << FShft (LCCR1_HSW))
#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
- /* count - 1 [Tpix] */
-#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
- /* [1..256 Tpix] */ \
+ /* count - 1 [Tpix] */
+#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
+ /* [1..256 Tpix] */ \
(((Tpix) - 1) << FShft (LCCR1_ELW))
#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
- /* Wait count - 1 [Tpix] */
-#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
- /* [1..256 Tpix] */ \
+ /* Wait count - 1 [Tpix] */
+#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
+ /* [1..256 Tpix] */ \
(((Tpix) - 1) << FShft (LCCR1_BLW))
-#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
-#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
+#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
+#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
(((Line) - 1) << FShft (LCCR2_LPP))
#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
- /* Width - 1 [Tln] (L_FCLK) */
-#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
- /* Width [1..64 Tln] */ \
+ /* Width - 1 [Tln] (L_FCLK) */
+#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
+ /* Width [1..64 Tln] */ \
(((Tln) - 1) << FShft (LCCR2_VSW))
#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
- /* count [Tln] */
-#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
- /* [0..255 Tln] */ \
+ /* count [Tln] */
+#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
+ /* [0..255 Tln] */ \
((Tln) << FShft (LCCR2_EFW))
#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
- /* Wait count [Tln] */
-#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
- /* [0..255 Tln] */ \
+ /* Wait count [Tln] */
+#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
+ /* [0..255 Tln] */ \
((Tln) << FShft (LCCR2_BFW))
-#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
- /* [1..255] (L_PCLK) */
- /* fpix = fcpu/(2*(PCD + 2)) */
- /* Tpix = 2*(PCD + 2)*Tcpu */
-#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
+#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
+ /* [1..255] (L_PCLK) */
+ /* fpix = fcpu/(2*(PCD + 2)) */
+ /* Tpix = 2*(PCD + 2)*Tcpu */
+#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
(((Div) - 4)/2 << FShft (LCCR3_PCD))
/* fpix = fcpu/(2*Floor (Div/2)) */
/* Tpix = 2*Floor (Div/2)*Tcpu */
#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
(((Div) - 3)/2 << FShft (LCCR3_PCD))
/* fpix = fcpu/(2*Ceil (Div/2)) */
- /* Tpix = 2*Ceil (Div/2)*Tcpu */
+ /* Tpix = 2*Ceil (Div/2)*Tcpu */
#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
- /* [Tln] (L_BIAS) */
-#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
+ /* [Tln] (L_BIAS) */
+#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
(((Div) - 2)/2 << FShft (LCCR3_ACB))
/* fac = fln/(2*Floor (Div/2)) */
- /* Tac = 2*Floor (Div/2)*Tln */
-#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
+ /* Tac = 2*Floor (Div/2)*Tln */
+#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
(((Div) - 1)/2 << FShft (LCCR3_ACB))
- /* fac = fln/(2*Ceil (Div/2)) */
- /* Tac = 2*Ceil (Div/2)*Tln */
-#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */
- /* Interrupt */
-#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \
- /* Off */ \
+ /* fac = fln/(2*Ceil (Div/2)) */
+ /* Tac = 2*Ceil (Div/2)*Tln */
+#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */
+ /* Interrupt */
+#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \
+ /* Off */ \
(0 << FShft (LCCR3_API))
-#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \
- /* [1..15] */ \
+#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \
+ /* [1..15] */ \
((Trans) << FShft (LCCR3_API))
#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */
- /* Polarity (L_FCLK) */
+ /* Polarity (L_FCLK) */
#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
- /* active High */
+ /* active High */
#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
- /* active Low */
-#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
- /* pulse Polarity (L_LCLK) */
-#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
- /* pulse active High */
-#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
- /* pulse active Low */
+ /* active Low */
+#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
+ /* pulse Polarity (L_LCLK) */
+#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
+ /* pulse active High */
+#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
+ /* pulse active Low */
#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
-#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
-#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
+#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
+#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
- /* active display mode) */
-#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
-#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
+ /* active display mode) */
+#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
+#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
#undef C
diff --git a/include/ahci.h b/include/ahci.h
index 80701e2..b363ee1 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -91,12 +91,12 @@
#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
-#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \
+#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \
| PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
-#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \
- | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \
- | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \
+#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \
+ | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \
+ | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \
| PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
| PORT_IRQ_D2H_REG_FIS
@@ -172,7 +172,7 @@ struct ahci_ioports {
};
struct ahci_probe_ent {
- pci_dev_t dev;
+ pci_dev_t dev;
struct ahci_ioports port[AHCI_MAX_PORTS];
u32 n_ports;
u32 hard_port_no;
diff --git a/include/armcoremodule.h b/include/armcoremodule.h
index 7dac6f8..f1ded85 100644
--- a/include/armcoremodule.h
+++ b/include/armcoremodule.h
@@ -28,20 +28,20 @@
#ifndef __ARMCOREMODULE_H
#define __ARMCOREMODULE_H
-#define CM_BASE 0x10000000
+#define CM_BASE 0x10000000
/* CM registers common to all CMs */
/* Note that observed values after reboot into the ARM Boot Monitor
have been used as defaults, rather than the POR values */
-#define OS_CTRL 0x0000000C
+#define OS_CTRL 0x0000000C
#define CMMASK_REMAP 0x00000005 /* set remap & led */
#define CMMASK_RESET 0x00000008
-#define OS_LOCK 0x00000014
-#define CMVAL_LOCK1 0x0000A000 /* locking value */
+#define OS_LOCK 0x00000014
+#define CMVAL_LOCK1 0x0000A000 /* locking value */
#define CMVAL_LOCK2 0x0000005F /* locking value */
#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
#define OS_SDRAM 0x00000020
-#define OS_INIT 0x00000024
+#define OS_INIT 0x00000024
#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
#define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */
diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h
index f0529fd..c650c3b 100644
--- a/include/asm-arm/arch-arm720t/netarm_mem_module.h
+++ b/include/asm-arm/arch-arm720t/netarm_mem_module.h
@@ -170,15 +170,15 @@
/* Option B Registers (0xFFC0_00x8) */
#define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001)
#define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002)
-#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000)
-#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004)
-#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008)
-#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C)
-
-#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000)
-#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010)
-#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020)
-#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030)
+#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000)
+#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004)
+#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008)
+#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C)
+
+#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000)
+#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010)
+#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020)
+#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030)
#endif
#endif
diff --git a/include/asm-arm/arch-arm720t/netarm_ser_module.h b/include/asm-arm/arch-arm720t/netarm_ser_module.h
index fceabd1..6fbae11 100644
--- a/include/asm-arm/arch-arm720t/netarm_ser_module.h
+++ b/include/asm-arm/arch-arm720t/netarm_ser_module.h
@@ -284,21 +284,21 @@ typedef struct {
/* from section 7.5.4 of HW Ref Guide */
/* #ifdef CONFIG_NETARM_PLL_BYPASS */
-#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \
- NETARM_SER_BR_RX_CLK_INT | \
- NETARM_SER_BR_TX_CLK_INT | \
- NETARM_SER_BR_CLK_EXT_5 | \
- ( ( ( ( NETARM_XTAL_FREQ / \
- ( x * 10 ) ) - 1 ) / 16 ) & \
+#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \
+ NETARM_SER_BR_RX_CLK_INT | \
+ NETARM_SER_BR_TX_CLK_INT | \
+ NETARM_SER_BR_CLK_EXT_5 | \
+ ( ( ( ( NETARM_XTAL_FREQ / \
+ ( x * 10 ) ) - 1 ) / 16 ) & \
NETARM_SER_BR_MASK ) )
/*
#else
-#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \
- NETARM_SER_BR_RX_CLK_INT | \
- NETARM_SER_BR_TX_CLK_INT | \
- NETARM_SER_BR_CLK_SYSTEM | \
- ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \
- ( x * 2 ) ) - 1 ) / 16 ) & \
+#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \
+ NETARM_SER_BR_RX_CLK_INT | \
+ NETARM_SER_BR_TX_CLK_INT | \
+ NETARM_SER_BR_CLK_SYSTEM | \
+ ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \
+ ( x * 2 ) ) - 1 ) / 16 ) & \
NETARM_SER_BR_MASK ) )
#endif
*/
@@ -313,13 +313,13 @@ typedef struct {
/* #ifdef CONFIG_NETARM_PLL_BYPASS */
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
( ( ( ( 10 * NETARM_XTAL_FREQ ) / \
- ( x * 5 * 512 ) ) - 1 ) & \
+ ( x * 5 * 512 ) ) - 1 ) & \
NETARM_SER_RX_GAP_MASK ) )
/*
#else
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \
- ( x * 512 ) ) - 1 ) & \
+ ( x * 512 ) ) - 1 ) & \
NETARM_SER_RX_GAP_MASK ) )
#endif
*/
@@ -327,11 +327,11 @@ typedef struct {
#if 0
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \
- ( x * 5 * 512 ) ) - 1 ) & \
+ ( x * 5 * 512 ) ) - 1 ) & \
NETARM_SER_RX_GAP_MASK ) )
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
( ( ( ( 10 * NETARM_XTAL_FREQ ) / \
- ( x * 512 ) ) - 1 ) & \
+ ( x * 512 ) ) - 1 ) & \
NETARM_SER_RX_GAP_MASK ) )
#endif
diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-arm720t/s3c4510b.h
index 73a3b6d..6b8c8ed 100644
--- a/include/asm-arm/arch-arm720t/s3c4510b.h
+++ b/include/asm-arm/arch-arm720t/s3c4510b.h
@@ -35,7 +35,7 @@
/* Special Register Start Address After System Reset */
#define REG_BASE (0x03ff0000)
-#define SPSTR (REG_BASE)
+#define SPSTR (REG_BASE)
/* *********************** */
/* System Manager Register */
@@ -100,7 +100,7 @@
#define REG_I2C_CON (REG_BASE+0xf000)
#define REG_I2C_BUF (REG_BASE+0xf004)
#define REG_I2C_PS (REG_BASE+0xf008)
-#define REG_I2C_COUNT (REG_BASE+0xf00c)
+#define REG_I2C_COUNT (REG_BASE+0xf00c)
/********************/
/* GDMA 0 */
@@ -149,7 +149,7 @@
/********************/
/* Timer Register */
/********************/
-#define REG_TMOD (REG_BASE+0x6000)
+#define REG_TMOD (REG_BASE+0x6000)
#define REG_TDATA0 (REG_BASE+0x6004)
#define REG_TDATA1 (REG_BASE+0x6008)
#define REG_TCNT0 (REG_BASE+0x600c)
@@ -159,8 +159,8 @@
/* I/O Port Interface */
/**********************/
#define REG_IOPMODE (REG_BASE+0x5000)
-#define REG_IOPCON (REG_BASE+0x5004)
-#define REG_IOPDATA (REG_BASE+0x5008)
+#define REG_IOPCON (REG_BASE+0x5004)
+#define REG_IOPDATA (REG_BASE+0x5008)
/*********************************/
/* Interrupt Controller Register */
diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
index 0e01005..2f7f710 100644
--- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h
+++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
@@ -32,17 +32,17 @@ typedef volatile unsigned int AT91_REG; /* Hardware register definition */
/*****************************************************************************/
typedef struct _AT91S_TC
{
- AT91_REG TC_CCR; /* Channel Control Register */
- AT91_REG TC_CMR; /* Channel Mode Register */
- AT91_REG Reserved0[2]; /* */
- AT91_REG TC_CV; /* Counter Value */
- AT91_REG TC_RA; /* Register A */
- AT91_REG TC_RB; /* Register B */
- AT91_REG TC_RC; /* Register C */
- AT91_REG TC_SR; /* Status Register */
- AT91_REG TC_IER; /* Interrupt Enable Register */
- AT91_REG TC_IDR; /* Interrupt Disable Register */
- AT91_REG TC_IMR; /* Interrupt Mask Register */
+ AT91_REG TC_CCR; /* Channel Control Register */
+ AT91_REG TC_CMR; /* Channel Mode Register */
+ AT91_REG Reserved0[2]; /* */
+ AT91_REG TC_CV; /* Counter Value */
+ AT91_REG TC_RA; /* Register A */
+ AT91_REG TC_RB; /* Register B */
+ AT91_REG TC_RC; /* Register C */
+ AT91_REG TC_SR; /* Status Register */
+ AT91_REG TC_IER; /* Interrupt Enable Register */
+ AT91_REG TC_IDR; /* Interrupt Disable Register */
+ AT91_REG TC_IMR; /* Interrupt Mask Register */
} AT91S_TC, *AT91PS_TC;
#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
@@ -65,33 +65,33 @@ typedef struct _AT91S_TC
/*****************************************************************************/
typedef struct _AT91S_USART
{
- AT91_REG US_CR; /* Control Register */
- AT91_REG US_MR; /* Mode Register */
- AT91_REG US_IER; /* Interrupt Enable Register */
- AT91_REG US_IDR; /* Interrupt Disable Register */
- AT91_REG US_IMR; /* Interrupt Mask Register */
- AT91_REG US_CSR; /* Channel Status Register */
- AT91_REG US_RHR; /* Receiver Holding Register */
- AT91_REG US_THR; /* Transmitter Holding Register */
- AT91_REG US_BRGR; /* Baud Rate Generator Register */
- AT91_REG US_RTOR; /* Receiver Time-out Register */
- AT91_REG US_TTGR; /* Transmitter Time-guard Register */
- AT91_REG Reserved0[5]; /* */
- AT91_REG US_FIDI; /* FI_DI_Ratio Register */
- AT91_REG US_NER; /* Nb Errors Register */
- AT91_REG US_XXR; /* XON_XOFF Register */
- AT91_REG US_IF; /* IRDA_FILTER Register */
+ AT91_REG US_CR; /* Control Register */
+ AT91_REG US_MR; /* Mode Register */
+ AT91_REG US_IER; /* Interrupt Enable Register */
+ AT91_REG US_IDR; /* Interrupt Disable Register */
+ AT91_REG US_IMR; /* Interrupt Mask Register */
+ AT91_REG US_CSR; /* Channel Status Register */
+ AT91_REG US_RHR; /* Receiver Holding Register */
+ AT91_REG US_THR; /* Transmitter Holding Register */
+ AT91_REG US_BRGR; /* Baud Rate Generator Register */
+ AT91_REG US_RTOR; /* Receiver Time-out Register */
+ AT91_REG US_TTGR; /* Transmitter Time-guard Register */
+ AT91_REG Reserved0[5]; /* */
+ AT91_REG US_FIDI; /* FI_DI_Ratio Register */
+ AT91_REG US_NER; /* Nb Errors Register */
+ AT91_REG US_XXR; /* XON_XOFF Register */
+ AT91_REG US_IF; /* IRDA_FILTER Register */
AT91_REG Reserved1[44]; /* */
- AT91_REG US_RPR; /* Receive Pointer Register */
- AT91_REG US_RCR; /* Receive Counter Register */
- AT91_REG US_TPR; /* Transmit Pointer Register */
- AT91_REG US_TCR; /* Transmit Counter Register */
- AT91_REG US_RNPR; /* Receive Next Pointer Register */
- AT91_REG US_RNCR; /* Receive Next Counter Register */
- AT91_REG US_TNPR; /* Transmit Next Pointer Register */
- AT91_REG US_TNCR; /* Transmit Next Counter Register */
- AT91_REG US_PTCR; /* PDC Transfer Control Register */
- AT91_REG US_PTSR; /* PDC Transfer Status Register */
+ AT91_REG US_RPR; /* Receive Pointer Register */
+ AT91_REG US_RCR; /* Receive Counter Register */
+ AT91_REG US_TPR; /* Transmit Pointer Register */
+ AT91_REG US_TCR; /* Transmit Counter Register */
+ AT91_REG US_RNPR; /* Receive Next Pointer Register */
+ AT91_REG US_RNCR; /* Receive Next Counter Register */
+ AT91_REG US_TNPR; /* Transmit Next Pointer Register */
+ AT91_REG US_TNCR; /* Transmit Next Counter Register */
+ AT91_REG US_PTCR; /* PDC Transfer Control Register */
+ AT91_REG US_PTSR; /* PDC Transfer Status Register */
} AT91S_USART, *AT91PS_USART;
/*****************************************************************************/
@@ -99,10 +99,10 @@ typedef struct _AT91S_USART
/*****************************************************************************/
typedef struct _AT91S_CKGR
{
- AT91_REG CKGR_MOR; /* Main Oscillator Register */
- AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
- AT91_REG CKGR_PLLAR; /* PLL A Register */
- AT91_REG CKGR_PLLBR; /* PLL B Register */
+ AT91_REG CKGR_MOR; /* Main Oscillator Register */
+ AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
+ AT91_REG CKGR_PLLAR; /* PLL A Register */
+ AT91_REG CKGR_PLLBR; /* PLL B Register */
} AT91S_CKGR, *AT91PS_CKGR;
/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
@@ -146,41 +146,41 @@ typedef struct _AT91S_CKGR
/*****************************************************************************/
typedef struct _AT91S_PIO
{
- AT91_REG PIO_PER; /* PIO Enable Register */
- AT91_REG PIO_PDR; /* PIO Disable Register */
- AT91_REG PIO_PSR; /* PIO Status Register */
- AT91_REG Reserved0[1]; /* */
- AT91_REG PIO_OER; /* Output Enable Register */
- AT91_REG PIO_ODR; /* Output Disable Registerr */
- AT91_REG PIO_OSR; /* Output Status Register */
- AT91_REG Reserved1[1]; /* */
- AT91_REG PIO_IFER; /* Input Filter Enable Register */
- AT91_REG PIO_IFDR; /* Input Filter Disable Register */
- AT91_REG PIO_IFSR; /* Input Filter Status Register */
- AT91_REG Reserved2[1]; /* */
- AT91_REG PIO_SODR; /* Set Output Data Register */
- AT91_REG PIO_CODR; /* Clear Output Data Register */
- AT91_REG PIO_ODSR; /* Output Data Status Register */
- AT91_REG PIO_PDSR; /* Pin Data Status Register */
- AT91_REG PIO_IER; /* Interrupt Enable Register */
- AT91_REG PIO_IDR; /* Interrupt Disable Register */
- AT91_REG PIO_IMR; /* Interrupt Mask Register */
- AT91_REG PIO_ISR; /* Interrupt Status Register */
- AT91_REG PIO_MDER; /* Multi-driver Enable Register */
- AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
- AT91_REG PIO_MDSR; /* Multi-driver Status Register */
- AT91_REG Reserved3[1]; /* */
- AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
- AT91_REG PIO_PPUER; /* Pull-up Enable Register */
- AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */
- AT91_REG Reserved4[1]; /* */
- AT91_REG PIO_ASR; /* Select A Register */
- AT91_REG PIO_BSR; /* Select B Register */
- AT91_REG PIO_ABSR; /* AB Select Status Register */
- AT91_REG Reserved5[9]; /* */
- AT91_REG PIO_OWER; /* Output Write Enable Register */
- AT91_REG PIO_OWDR; /* Output Write Disable Register */
- AT91_REG PIO_OWSR; /* Output Write Status Register */
+ AT91_REG PIO_PER; /* PIO Enable Register */
+ AT91_REG PIO_PDR; /* PIO Disable Register */
+ AT91_REG PIO_PSR; /* PIO Status Register */
+ AT91_REG Reserved0[1]; /* */
+ AT91_REG PIO_OER; /* Output Enable Register */
+ AT91_REG PIO_ODR; /* Output Disable Registerr */
+ AT91_REG PIO_OSR; /* Output Status Register */
+ AT91_REG Reserved1[1]; /* */
+ AT91_REG PIO_IFER; /* Input Filter Enable Register */
+ AT91_REG PIO_IFDR; /* Input Filter Disable Register */
+ AT91_REG PIO_IFSR; /* Input Filter Status Register */
+ AT91_REG Reserved2[1]; /* */
+ AT91_REG PIO_SODR; /* Set Output Data Register */
+ AT91_REG PIO_CODR; /* Clear Output Data Register */
+ AT91_REG PIO_ODSR; /* Output Data Status Register */
+ AT91_REG PIO_PDSR; /* Pin Data Status Register */
+ AT91_REG PIO_IER; /* Interrupt Enable Register */
+ AT91_REG PIO_IDR; /* Interrupt Disable Register */
+ AT91_REG PIO_IMR; /* Interrupt Mask Register */
+ AT91_REG PIO_ISR; /* Interrupt Status Register */
+ AT91_REG PIO_MDER; /* Multi-driver Enable Register */
+ AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
+ AT91_REG PIO_MDSR; /* Multi-driver Status Register */
+ AT91_REG Reserved3[1]; /* */
+ AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
+ AT91_REG PIO_PPUER; /* Pull-up Enable Register */
+ AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */
+ AT91_REG Reserved4[1]; /* */
+ AT91_REG PIO_ASR; /* Select A Register */
+ AT91_REG PIO_BSR; /* Select B Register */
+ AT91_REG PIO_ABSR; /* AB Select Status Register */
+ AT91_REG Reserved5[9]; /* */
+ AT91_REG PIO_OWER; /* Output Write Enable Register */
+ AT91_REG PIO_OWDR; /* Output Write Disable Register */
+ AT91_REG PIO_OWSR; /* Output Write Status Register */
} AT91S_PIO, *AT91PS_PIO;
@@ -189,30 +189,30 @@ typedef struct _AT91S_PIO
/*****************************************************************************/
typedef struct _AT91S_DBGU
{
- AT91_REG DBGU_CR; /* Control Register */
- AT91_REG DBGU_MR; /* Mode Register */
- AT91_REG DBGU_IER; /* Interrupt Enable Register */
- AT91_REG DBGU_IDR; /* Interrupt Disable Register */
- AT91_REG DBGU_IMR; /* Interrupt Mask Register */
- AT91_REG DBGU_CSR; /* Channel Status Register */
- AT91_REG DBGU_RHR; /* Receiver Holding Register */
- AT91_REG DBGU_THR; /* Transmitter Holding Register */
- AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
- AT91_REG Reserved0[7]; /* */
- AT91_REG DBGU_C1R; /* Chip ID1 Register */
- AT91_REG DBGU_C2R; /* Chip ID2 Register */
- AT91_REG DBGU_FNTR; /* Force NTRST Register */
- AT91_REG Reserved1[45]; /* */
- AT91_REG DBGU_RPR; /* Receive Pointer Register */
- AT91_REG DBGU_RCR; /* Receive Counter Register */
- AT91_REG DBGU_TPR; /* Transmit Pointer Register */
- AT91_REG DBGU_TCR; /* Transmit Counter Register */
- AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
- AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
- AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
- AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
- AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
- AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
+ AT91_REG DBGU_CR; /* Control Register */
+ AT91_REG DBGU_MR; /* Mode Register */
+ AT91_REG DBGU_IER; /* Interrupt Enable Register */
+ AT91_REG DBGU_IDR; /* Interrupt Disable Register */
+ AT91_REG DBGU_IMR; /* Interrupt Mask Register */
+ AT91_REG DBGU_CSR; /* Channel Status Register */
+ AT91_REG DBGU_RHR; /* Receiver Holding Register */
+ AT91_REG DBGU_THR; /* Transmitter Holding Register */
+ AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
+ AT91_REG Reserved0[7]; /* */
+ AT91_REG DBGU_C1R; /* Chip ID1 Register */
+ AT91_REG DBGU_C2R; /* Chip ID2 Register */
+ AT91_REG DBGU_FNTR; /* Force NTRST Register */
+ AT91_REG Reserved1[45]; /* */
+ AT91_REG DBGU_RPR; /* Receive Pointer Register */
+ AT91_REG DBGU_RCR; /* Receive Counter Register */
+ AT91_REG DBGU_TPR; /* Transmit Pointer Register */
+ AT91_REG DBGU_TCR; /* Transmit Counter Register */
+ AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
+ AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
+ AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
+ AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
+ AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
+ AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
} AT91S_DBGU, *AT91PS_DBGU;
/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
@@ -247,7 +247,7 @@ typedef struct _AT91S_DBGU
/*****************************************************************************/
typedef struct _AT91S_SMC2
{
- AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
+ AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
} AT91S_SMC2, *AT91PS_SMC2;
/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */
@@ -272,21 +272,21 @@ typedef struct _AT91S_SMC2
/*****************************************************************************/
typedef struct _AT91S_PMC
{
- AT91_REG PMC_SCER; /* System Clock Enable Register */
- AT91_REG PMC_SCDR; /* System Clock Disable Register */
- AT91_REG PMC_SCSR; /* System Clock Status Register */
- AT91_REG Reserved0[1]; /* */
- AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
- AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
- AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
- AT91_REG Reserved1[5]; /* */
- AT91_REG PMC_MCKR; /* Master Clock Register */
- AT91_REG Reserved2[3]; /* */
- AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */
- AT91_REG PMC_IER; /* Interrupt Enable Register */
- AT91_REG PMC_IDR; /* Interrupt Disable Register */
- AT91_REG PMC_SR; /* Status Register */
- AT91_REG PMC_IMR; /* Interrupt Mask Register */
+ AT91_REG PMC_SCER; /* System Clock Enable Register */
+ AT91_REG PMC_SCDR; /* System Clock Disable Register */
+ AT91_REG PMC_SCSR; /* System Clock Status Register */
+ AT91_REG Reserved0[1]; /* */
+ AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
+ AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
+ AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
+ AT91_REG Reserved1[5]; /* */
+ AT91_REG PMC_MCKR; /* Master Clock Register */
+ AT91_REG Reserved2[3]; /* */
+ AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */
+ AT91_REG PMC_IER; /* Interrupt Enable Register */
+ AT91_REG PMC_IDR; /* Interrupt Disable Register */
+ AT91_REG PMC_SR; /* Status Register */
+ AT91_REG PMC_IMR; /* Interrupt Mask Register */
} AT91S_PMC, *AT91PS_PMC;
/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
@@ -346,49 +346,49 @@ typedef struct _AT91S_PMC
/*****************************************************************************/
typedef struct _AT91S_EMAC
{
- AT91_REG EMAC_CTL; /* Network Control Register */
- AT91_REG EMAC_CFG; /* Network Configuration Register */
- AT91_REG EMAC_SR; /* Network Status Register */
- AT91_REG EMAC_TAR; /* Transmit Address Register */
- AT91_REG EMAC_TCR; /* Transmit Control Register */
- AT91_REG EMAC_TSR; /* Transmit Status Register */
- AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
- AT91_REG Reserved0[1]; /* */
- AT91_REG EMAC_RSR; /* Receive Status Register */
- AT91_REG EMAC_ISR; /* Interrupt Status Register */
- AT91_REG EMAC_IER; /* Interrupt Enable Register */
- AT91_REG EMAC_IDR; /* Interrupt Disable Register */
- AT91_REG EMAC_IMR; /* Interrupt Mask Register */
- AT91_REG EMAC_MAN; /* PHY Maintenance Register */
- AT91_REG Reserved1[2]; /* */
- AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */
- AT91_REG EMAC_SCOL; /* Single Collision Frame Register */
- AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */
- AT91_REG EMAC_OK; /* Frames Received OK Register */
- AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */
- AT91_REG EMAC_ALE; /* Alignment Error Register */
- AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */
- AT91_REG EMAC_LCOL; /* Late Collision Register */
- AT91_REG EMAC_ECOL; /* Excessive Collision Register */
- AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
- AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */
- AT91_REG EMAC_CDE; /* Code Error Register */
- AT91_REG EMAC_ELR; /* Excessive Length Error Register */
- AT91_REG EMAC_RJB; /* Receive Jabber Register */
- AT91_REG EMAC_USF; /* Undersize Frame Register */
- AT91_REG EMAC_SQEE; /* SQE Test Error Register */
- AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */
- AT91_REG Reserved2[3]; /* */
- AT91_REG EMAC_HSH; /* Hash Address High[63:32] */
- AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */
- AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */
- AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */
- AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */
- AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */
- AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */
- AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */
- AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */
- AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */
+ AT91_REG EMAC_CTL; /* Network Control Register */
+ AT91_REG EMAC_CFG; /* Network Configuration Register */
+ AT91_REG EMAC_SR; /* Network Status Register */
+ AT91_REG EMAC_TAR; /* Transmit Address Register */
+ AT91_REG EMAC_TCR; /* Transmit Control Register */
+ AT91_REG EMAC_TSR; /* Transmit Status Register */
+ AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
+ AT91_REG Reserved0[1]; /* */
+ AT91_REG EMAC_RSR; /* Receive Status Register */
+ AT91_REG EMAC_ISR; /* Interrupt Status Register */
+ AT91_REG EMAC_IER; /* Interrupt Enable Register */
+ AT91_REG EMAC_IDR; /* Interrupt Disable Register */
+ AT91_REG EMAC_IMR; /* Interrupt Mask Register */
+ AT91_REG EMAC_MAN; /* PHY Maintenance Register */
+ AT91_REG Reserved1[2]; /* */
+ AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */
+ AT91_REG EMAC_SCOL; /* Single Collision Frame Register */
+ AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */
+ AT91_REG EMAC_OK; /* Frames Received OK Register */
+ AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */
+ AT91_REG EMAC_ALE; /* Alignment Error Register */
+ AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */
+ AT91_REG EMAC_LCOL; /* Late Collision Register */
+ AT91_REG EMAC_ECOL; /* Excessive Collision Register */
+ AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
+ AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */
+ AT91_REG EMAC_CDE; /* Code Error Register */
+ AT91_REG EMAC_ELR; /* Excessive Length Error Register */
+ AT91_REG EMAC_RJB; /* Receive Jabber Register */
+ AT91_REG EMAC_USF; /* Undersize Frame Register */
+ AT91_REG EMAC_SQEE; /* SQE Test Error Register */
+ AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */
+ AT91_REG Reserved2[3]; /* */
+ AT91_REG EMAC_HSH; /* Hash Address High[63:32] */
+ AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */
+ AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */
+ AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */
+ AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */
+ AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */
+ AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */
+ AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */
+ AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */
+ AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */
} AT91S_EMAC, *AT91PS_EMAC;
/* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */
@@ -476,27 +476,27 @@ typedef struct _AT91S_EMAC
/*****************************************************************************/
typedef struct _AT91S_SPI
{
- AT91_REG SPI_CR; /* Control Register */
- AT91_REG SPI_MR; /* Mode Register */
- AT91_REG SPI_RDR; /* Receive Data Register */
- AT91_REG SPI_TDR; /* Transmit Data Register */
- AT91_REG SPI_SR; /* Status Register */
- AT91_REG SPI_IER; /* Interrupt Enable Register */
- AT91_REG SPI_IDR; /* Interrupt Disable Register */
- AT91_REG SPI_IMR; /* Interrupt Mask Register */
- AT91_REG Reserved0[4]; /* */
- AT91_REG SPI_CSR[4]; /* Chip Select Register */
+ AT91_REG SPI_CR; /* Control Register */
+ AT91_REG SPI_MR; /* Mode Register */
+ AT91_REG SPI_RDR; /* Receive Data Register */
+ AT91_REG SPI_TDR; /* Transmit Data Register */
+ AT91_REG SPI_SR; /* Status Register */
+ AT91_REG SPI_IER; /* Interrupt Enable Register */
+ AT91_REG SPI_IDR; /* Interrupt Disable Register */
+ AT91_REG SPI_IMR; /* Interrupt Mask Register */
+ AT91_REG Reserved0[4]; /* */
+ AT91_REG SPI_CSR[4]; /* Chip Select Register */
AT91_REG Reserved1[48]; /* */
- AT91_REG SPI_RPR; /* Receive Pointer Register */
- AT91_REG SPI_RCR; /* Receive Counter Register */
- AT91_REG SPI_TPR; /* Transmit Pointer Register */
- AT91_REG SPI_TCR; /* Transmit Counter Register */
- AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
- AT91_REG SPI_RNCR; /* Receive Next Counter Register */
- AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
- AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
- AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
- AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
+ AT91_REG SPI_RPR; /* Receive Pointer Register */
+ AT91_REG SPI_RCR; /* Receive Counter Register */
+ AT91_REG SPI_TPR; /* Transmit Pointer Register */
+ AT91_REG SPI_TCR; /* Transmit Counter Register */
+ AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
+ AT91_REG SPI_RNCR; /* Receive Next Counter Register */
+ AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
+ AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
+ AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
+ AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
} AT91S_SPI, *AT91PS_SPI;
/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
@@ -560,16 +560,16 @@ typedef struct _AT91S_SPI
/*****************************************************************************/
typedef struct _AT91S_PDC
{
- AT91_REG PDC_RPR; /* Receive Pointer Register */
- AT91_REG PDC_RCR; /* Receive Counter Register */
- AT91_REG PDC_TPR; /* Transmit Pointer Register */
- AT91_REG PDC_TCR; /* Transmit Counter Register */
- AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
- AT91_REG PDC_RNCR; /* Receive Next Counter Register */
- AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
- AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
- AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
- AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
+ AT91_REG PDC_RPR; /* Receive Pointer Register */
+ AT91_REG PDC_RCR; /* Receive Counter Register */
+ AT91_REG PDC_TPR; /* Transmit Pointer Register */
+ AT91_REG PDC_TCR; /* Transmit Counter Register */
+ AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
+ AT91_REG PDC_RNCR; /* Receive Next Counter Register */
+ AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
+ AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
+ AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
+ AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
} AT91S_PDC, *AT91PS_PDC;
/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
@@ -700,7 +700,7 @@ typedef struct _AT91S_PDC
#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */
#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
-#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */
+#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */
#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
@@ -775,7 +775,7 @@ typedef struct _AT91S_PDC
#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */
#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */
-#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */
+#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */
#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */
#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */
#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */
diff --git a/include/asm-arm/arch-at91sam9/at91_pmc.h b/include/asm-arm/arch-at91sam9/at91_pmc.h
index 103be86..b57875d 100644
--- a/include/asm-arm/arch-at91sam9/at91_pmc.h
+++ b/include/asm-arm/arch-at91sam9/at91_pmc.h
@@ -96,4 +96,9 @@
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
+#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
+#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
+
+#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
+
#endif
diff --git a/include/asm-arm/arch-at91sam9/at91cap9.h b/include/asm-arm/arch-at91sam9/at91cap9.h
index d1b33a0..0b52228 100644
--- a/include/asm-arm/arch-at91sam9/at91cap9.h
+++ b/include/asm-arm/arch-at91sam9/at91cap9.h
@@ -101,13 +101,25 @@
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
+#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
+#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS)
+#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS)
#define AT91_USART0 AT91CAP9_BASE_US0
#define AT91_USART1 AT91CAP9_BASE_US1
#define AT91_USART2 AT91CAP9_BASE_US2
/*
+ * SCKCR flags
+ */
+#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */
+#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */
+#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */
+#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */
+#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3)
+#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3)
+
+/*
* Internal Memory.
*/
#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
diff --git a/include/asm-arm/arch-at91sam9/at91sam9261.h b/include/asm-arm/arch-at91sam9/at91sam9261.h
new file mode 100644
index 0000000..752d81d
--- /dev/null
+++ b/include/asm-arm/arch-at91sam9/at91sam9261.h
@@ -0,0 +1,105 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
+ *
+ * Copyright (C) SAN People
+ *
+ * Common definitions.
+ * Based on AT91SAM9261 datasheet revision E. (Preliminary)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9261_H
+#define AT91SAM9261_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS 1 /* System Peripherals */
+#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
+#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
+#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
+#define AT91SAM9261_ID_US0 6 /* USART 0 */
+#define AT91SAM9261_ID_US1 7 /* USART 1 */
+#define AT91SAM9261_ID_US2 8 /* USART 2 */
+#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
+#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
+#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
+#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
+#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
+#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
+#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
+#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
+#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
+#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
+#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
+#define AT91SAM9261_ID_UHP 20 /* USB Host port */
+#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
+#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
+#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
+#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9261_BASE_TCB0 0xfffa0000
+#define AT91SAM9261_BASE_TC0 0xfffa0000
+#define AT91SAM9261_BASE_TC1 0xfffa0040
+#define AT91SAM9261_BASE_TC2 0xfffa0080
+#define AT91SAM9261_BASE_UDP 0xfffa4000
+#define AT91SAM9261_BASE_MCI 0xfffa8000
+#define AT91SAM9261_BASE_TWI 0xfffac000
+#define AT91SAM9261_BASE_US0 0xfffb0000
+#define AT91SAM9261_BASE_US1 0xfffb4000
+#define AT91SAM9261_BASE_US2 0xfffb8000
+#define AT91SAM9261_BASE_SSC0 0xfffbc000
+#define AT91SAM9261_BASE_SSC1 0xfffc0000
+#define AT91SAM9261_BASE_SSC2 0xfffc4000
+#define AT91SAM9261_BASE_SPI0 0xfffc8000
+#define AT91SAM9261_BASE_SPI1 0xfffcc000
+#define AT91_BASE_SYS 0xffffea00
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
+
+#define AT91_USART0 AT91SAM9261_BASE_US0
+#define AT91_USART1 AT91SAM9261_BASE_US1
+#define AT91_USART2 AT91SAM9261_BASE_US2
+
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
+#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
+
+#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
+#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
+
+#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
+#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
+
+
+#endif
diff --git a/include/asm-arm/arch-at91sam9/at91sam9261_matrix.h b/include/asm-arm/arch-at91sam9/at91sam9261_matrix.h
new file mode 100644
index 0000000..e2bfc4b
--- /dev/null
+++ b/include/asm-arm/arch-at91sam9/at91sam9261_matrix.h
@@ -0,0 +1,64 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h]
+ *
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9261_MATRIX_H
+#define AT91SAM9261_MATRIX_H
+
+#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
+#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
+
+#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */
+#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
+#define AT91_MATRIX_ITCM_0 (0 << 0)
+#define AT91_MATRIX_ITCM_16 (5 << 0)
+#define AT91_MATRIX_ITCM_32 (6 << 0)
+#define AT91_MATRIX_ITCM_64 (7 << 0)
+#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
+#define AT91_MATRIX_DTCM_0 (0 << 4)
+#define AT91_MATRIX_DTCM_16 (5 << 4)
+#define AT91_MATRIX_DTCM_32 (6 << 4)
+#define AT91_MATRIX_DTCM_64 (7 << 4)
+
+#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91_MATRIX_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91_MATRIX_CS3A_SMC (0 << 3)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91_MATRIX_CS4A_SMC (0 << 4)
+#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91_MATRIX_CS5A_SMC (0 << 5)
+#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+
+#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */
+#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
+
+#endif
diff --git a/include/asm-arm/arch-at91sam9/at91sam9263.h b/include/asm-arm/arch-at91sam9/at91sam9263.h
new file mode 100644
index 0000000..98251cb
--- /dev/null
+++ b/include/asm-arm/arch-at91sam9/at91sam9263.h
@@ -0,0 +1,127 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h]
+ *
+ * (C) 2007 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91SAM9263 datasheet revision B (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9263_H
+#define AT91SAM9263_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS 1 /* System Peripherals */
+#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
+#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
+#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
+#define AT91SAM9263_ID_US0 7 /* USART 0 */
+#define AT91SAM9263_ID_US1 8 /* USART 1 */
+#define AT91SAM9263_ID_US2 9 /* USART 2 */
+#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
+#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
+#define AT91SAM9263_ID_CAN 12 /* CAN */
+#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
+#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
+#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
+#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
+#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
+#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
+#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
+#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
+#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
+#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
+#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
+#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
+#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
+#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
+#define AT91SAM9263_ID_UHP 29 /* USB Host port */
+#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
+#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9263_BASE_UDP 0xfff78000
+#define AT91SAM9263_BASE_TCB0 0xfff7c000
+#define AT91SAM9263_BASE_TC0 0xfff7c000
+#define AT91SAM9263_BASE_TC1 0xfff7c040
+#define AT91SAM9263_BASE_TC2 0xfff7c080
+#define AT91SAM9263_BASE_MCI0 0xfff80000
+#define AT91SAM9263_BASE_MCI1 0xfff84000
+#define AT91SAM9263_BASE_TWI 0xfff88000
+#define AT91SAM9263_BASE_US0 0xfff8c000
+#define AT91SAM9263_BASE_US1 0xfff90000
+#define AT91SAM9263_BASE_US2 0xfff94000
+#define AT91SAM9263_BASE_SSC0 0xfff98000
+#define AT91SAM9263_BASE_SSC1 0xfff9c000
+#define AT91SAM9263_BASE_AC97C 0xfffa0000
+#define AT91SAM9263_BASE_SPI0 0xfffa4000
+#define AT91SAM9263_BASE_SPI1 0xfffa8000
+#define AT91SAM9263_BASE_CAN 0xfffac000
+#define AT91SAM9263_BASE_PWMC 0xfffb8000
+#define AT91SAM9263_BASE_EMAC 0xfffbc000
+#define AT91SAM9263_BASE_ISI 0xfffc4000
+#define AT91SAM9263_BASE_2DGE 0xfffc8000
+#define AT91_BASE_SYS 0xffffe000
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
+#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
+#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
+#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
+#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
+#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
+#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
+#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
+#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
+#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
+#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
+#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
+
+#define AT91_USART0 AT91SAM9263_BASE_US0
+#define AT91_USART1 AT91SAM9263_BASE_US1
+#define AT91_USART2 AT91SAM9263_BASE_US2
+
+#define AT91_SMC AT91_SMC0
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
+#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
+
+#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
+#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
+
+#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
+#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
+
+#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
+#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
+#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
+
+
+#endif
diff --git a/include/asm-arm/arch-at91sam9/at91sam9263_matrix.h b/include/asm-arm/arch-at91sam9/at91sam9263_matrix.h
new file mode 100644
index 0000000..83aaaab
--- /dev/null
+++ b/include/asm-arm/arch-at91sam9/at91sam9263_matrix.h
@@ -0,0 +1,129 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h]
+ *
+ * Copyright (C) 2006 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9263 datasheet revision B (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9263_MATRIX_H
+#define AT91SAM9263_MATRIX_H
+
+#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
+#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+
+#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
+#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
+#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
+#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
+#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
+
+#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
+#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91_MATRIX_RCB2 (1 << 2)
+#define AT91_MATRIX_RCB3 (1 << 3)
+#define AT91_MATRIX_RCB4 (1 << 4)
+#define AT91_MATRIX_RCB5 (1 << 5)
+#define AT91_MATRIX_RCB6 (1 << 6)
+#define AT91_MATRIX_RCB7 (1 << 7)
+#define AT91_MATRIX_RCB8 (1 << 8)
+
+#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
+#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
+#define AT91_MATRIX_ITCM_0 (0 << 0)
+#define AT91_MATRIX_ITCM_16 (5 << 0)
+#define AT91_MATRIX_ITCM_32 (6 << 0)
+#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
+#define AT91_MATRIX_DTCM_0 (0 << 4)
+#define AT91_MATRIX_DTCM_16 (5 << 4)
+#define AT91_MATRIX_DTCM_32 (6 << 4)
+
+#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
+#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
+#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
+#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
+#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
+
+#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */
+#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
+#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
+
+#endif
diff --git a/include/asm-arm/arch-at91sam9/at91sam9rl.h b/include/asm-arm/arch-at91sam9/at91sam9rl.h
new file mode 100644
index 0000000..215bbc8
--- /dev/null
+++ b/include/asm-arm/arch-at91sam9/at91sam9rl.h
@@ -0,0 +1,115 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h]
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * Common definitions.
+ * Based on AT91SAM9RL datasheet revision A. (Preliminary)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef AT91SAM9RL_H
+#define AT91SAM9RL_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS 1 /* System Controller */
+#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
+#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
+#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
+#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
+#define AT91SAM9RL_ID_US0 6 /* USART 0 */
+#define AT91SAM9RL_ID_US1 7 /* USART 1 */
+#define AT91SAM9RL_ID_US2 8 /* USART 2 */
+#define AT91SAM9RL_ID_US3 9 /* USART 3 */
+#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
+#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
+#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
+#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
+#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
+#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
+#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
+#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
+#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
+#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
+#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
+#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
+#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
+#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
+#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
+#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9RL_BASE_TCB0 0xfffa0000
+#define AT91SAM9RL_BASE_TC0 0xfffa0000
+#define AT91SAM9RL_BASE_TC1 0xfffa0040
+#define AT91SAM9RL_BASE_TC2 0xfffa0080
+#define AT91SAM9RL_BASE_MCI 0xfffa4000
+#define AT91SAM9RL_BASE_TWI0 0xfffa8000
+#define AT91SAM9RL_BASE_TWI1 0xfffac000
+#define AT91SAM9RL_BASE_US0 0xfffb0000
+#define AT91SAM9RL_BASE_US1 0xfffb4000
+#define AT91SAM9RL_BASE_US2 0xfffb8000
+#define AT91SAM9RL_BASE_US3 0xfffbc000
+#define AT91SAM9RL_BASE_SSC0 0xfffc0000
+#define AT91SAM9RL_BASE_SSC1 0xfffc4000
+#define AT91SAM9RL_BASE_PWMC 0xfffc8000
+#define AT91SAM9RL_BASE_SPI 0xfffcc000
+#define AT91SAM9RL_BASE_TSC 0xfffd0000
+#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
+#define AT91SAM9RL_BASE_AC97C 0xfffd8000
+#define AT91_BASE_SYS 0xffffc000
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
+#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
+#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
+#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
+#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS)
+#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
+#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
+#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
+
+#define AT91_USART0 AT91SAM9RL_BASE_US0
+#define AT91_USART1 AT91SAM9RL_BASE_US1
+#define AT91_USART2 AT91SAM9RL_BASE_US2
+#define AT91_USART3 AT91SAM9RL_BASE_US3
+
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
+#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
+
+#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
+#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
+
+#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
+#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */
+
+#endif
diff --git a/include/asm-arm/arch-at91sam9/at91sam9rl_matrix.h b/include/asm-arm/arch-at91sam9/at91sam9rl_matrix.h
new file mode 100644
index 0000000..af8d914
--- /dev/null
+++ b/include/asm-arm/arch-at91sam9/at91sam9rl_matrix.h
@@ -0,0 +1,96 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h]
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9RL datasheet revision A. (Preliminary)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef AT91SAM9RL_MATRIX_H
+#define AT91SAM9RL_MATRIX_H
+
+#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
+#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+
+#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+
+#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
+#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91_MATRIX_RCB2 (1 << 2)
+#define AT91_MATRIX_RCB3 (1 << 3)
+#define AT91_MATRIX_RCB4 (1 << 4)
+#define AT91_MATRIX_RCB5 (1 << 5)
+
+#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
+#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
+#define AT91_MATRIX_ITCM_0 (0 << 0)
+#define AT91_MATRIX_ITCM_16 (5 << 0)
+#define AT91_MATRIX_ITCM_32 (6 << 0)
+#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
+#define AT91_MATRIX_DTCM_0 (0 << 4)
+#define AT91_MATRIX_DTCM_16 (5 << 4)
+#define AT91_MATRIX_DTCM_32 (6 << 4)
+
+#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
+#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91_MATRIX_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91_MATRIX_CS3A_SMC (0 << 3)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91_MATRIX_CS4A_SMC (0 << 4)
+#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91_MATRIX_CS5A_SMC (0 << 5)
+#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+
+
+#endif
diff --git a/include/asm-arm/arch-at91sam9/clk.h b/include/asm-arm/arch-at91sam9/clk.h
index f67b435..1b502c8 100644
--- a/include/asm-arm/arch-at91sam9/clk.h
+++ b/include/asm-arm/arch-at91sam9/clk.h
@@ -36,4 +36,10 @@ static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
return AT91_MASTER_CLOCK;
}
+static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
+{
+ return AT91_MASTER_CLOCK;
+}
+
+
#endif /* __ASM_ARM_ARCH_CLK_H__ */
diff --git a/include/asm-arm/arch-at91sam9/gpio.h b/include/asm-arm/arch-at91sam9/gpio.h
index c157e10..c4d7b97 100644
--- a/include/asm-arm/arch-at91sam9/gpio.h
+++ b/include/asm-arm/arch-at91sam9/gpio.h
@@ -218,7 +218,7 @@ static inline unsigned pin_to_mask(unsigned pin)
*/
static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
{
- void *pio = pin_to_controller(pin);
+ void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + PIO_IDR);
@@ -232,7 +232,7 @@ static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
*/
static inline int at91_set_A_periph(unsigned pin, int use_pullup)
{
- void *pio = pin_to_controller(pin);
+ void *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
__raw_writel(mask, pio + PIO_IDR);
diff --git a/include/asm-arm/arch-at91sam9/hardware.h b/include/asm-arm/arch-at91sam9/hardware.h
index d2fe453..f312419 100644
--- a/include/asm-arm/arch-at91sam9/hardware.h
+++ b/include/asm-arm/arch-at91sam9/hardware.h
@@ -26,10 +26,19 @@
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
#elif defined(CONFIG_AT91SAM9261)
#include <asm/arch/at91sam9261.h>
+#define AT91_BASE_SPI AT91SAM9261_BASE_SPI0
+#define AT91_ID_UHP AT91SAM9261_ID_UHP
+#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
#elif defined(CONFIG_AT91SAM9263)
#include <asm/arch/at91sam9263.h>
+#define AT91_BASE_EMAC AT91SAM9263_BASE_EMAC
+#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0
+#define AT91_ID_UHP AT91SAM9263_ID_UHP
+#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
#elif defined(CONFIG_AT91SAM9RL)
#include <asm/arch/at91sam9rl.h>
+#define AT91_BASE_SPI AT91SAM9RL_BASE_SPI
+#define AT91_ID_UHP AT91SAM9RL_ID_UHP
#elif defined(CONFIG_AT91CAP9)
#include <asm/arch/at91cap9.h>
#define AT91_BASE_EMAC AT91CAP9_BASE_EMAC
@@ -42,15 +51,4 @@
#error "Unsupported AT91 processor"
#endif
-/*
- * container_of - cast a member of a structure out to the containing structure
- *
- * @ptr: the pointer to the member.
- * @type: the type of the container struct this is embedded in.
- * @member: the name of the member within the struct.
- */
-#define container_of(ptr, type, member) ({ \
- const typeof(((type *)0)->member) *__mptr = (ptr); \
- (type *)((char *)__mptr - offsetof(type, member)); })
-
#endif
diff --git a/include/asm-arm/arch-ixp/ixp425.h b/include/asm-arm/arch-ixp/ixp425.h
index 11dc356..2114437 100644
--- a/include/asm-arm/arch-ixp/ixp425.h
+++ b/include/asm-arm/arch-ixp/ixp425.h
@@ -53,13 +53,13 @@
*
* 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr
*
- * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG
+ * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG
*
* 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG
*
* 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL
*
- * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG
+ * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG
*/
/*
@@ -171,17 +171,17 @@
#define IXP425_SDR_REFRESH_OFFSET 0x04
#define IXP425_SDR_IR_OFFSET 0x08
-#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x))
+#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x))
#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
-#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
-#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
+#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
+#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
/*
* UART registers
*/
-#define IXP425_UART1 0
-#define IXP425_UART2 0x1000
+#define IXP425_UART1 0
+#define IXP425_UART2 0x1000
#define IXP425_UART_RBR_OFFSET 0x00
#define IXP425_UART_THR_OFFSET 0x00
@@ -476,49 +476,49 @@
*/
/* CSR bit definitions */
-#define PCI_CSR_HOST BIT(0)
-#define PCI_CSR_ARBEN BIT(1)
-#define PCI_CSR_ADS BIT(2)
-#define PCI_CSR_PDS BIT(3)
-#define PCI_CSR_ABE BIT(4)
-#define PCI_CSR_DBT BIT(5)
-#define PCI_CSR_ASE BIT(8)
-#define PCI_CSR_IC BIT(15)
+#define PCI_CSR_HOST BIT(0)
+#define PCI_CSR_ARBEN BIT(1)
+#define PCI_CSR_ADS BIT(2)
+#define PCI_CSR_PDS BIT(3)
+#define PCI_CSR_ABE BIT(4)
+#define PCI_CSR_DBT BIT(5)
+#define PCI_CSR_ASE BIT(8)
+#define PCI_CSR_IC BIT(15)
/* ISR (Interrupt status) Register bit definitions */
-#define PCI_ISR_PSE BIT(0)
-#define PCI_ISR_PFE BIT(1)
-#define PCI_ISR_PPE BIT(2)
-#define PCI_ISR_AHBE BIT(3)
-#define PCI_ISR_APDC BIT(4)
-#define PCI_ISR_PADC BIT(5)
-#define PCI_ISR_ADB BIT(6)
-#define PCI_ISR_PDB BIT(7)
+#define PCI_ISR_PSE BIT(0)
+#define PCI_ISR_PFE BIT(1)
+#define PCI_ISR_PPE BIT(2)
+#define PCI_ISR_AHBE BIT(3)
+#define PCI_ISR_APDC BIT(4)
+#define PCI_ISR_PADC BIT(5)
+#define PCI_ISR_ADB BIT(6)
+#define PCI_ISR_PDB BIT(7)
/* INTEN (Interrupt Enable) Register bit definitions */
-#define PCI_INTEN_PSE BIT(0)
-#define PCI_INTEN_PFE BIT(1)
-#define PCI_INTEN_PPE BIT(2)
-#define PCI_INTEN_AHBE BIT(3)
-#define PCI_INTEN_APDC BIT(4)
-#define PCI_INTEN_PADC BIT(5)
-#define PCI_INTEN_ADB BIT(6)
-#define PCI_INTEN_PDB BIT(7)
+#define PCI_INTEN_PSE BIT(0)
+#define PCI_INTEN_PFE BIT(1)
+#define PCI_INTEN_PPE BIT(2)
+#define PCI_INTEN_AHBE BIT(3)
+#define PCI_INTEN_APDC BIT(4)
+#define PCI_INTEN_PADC BIT(5)
+#define PCI_INTEN_ADB BIT(6)
+#define PCI_INTEN_PDB BIT(7)
/*
* Shift value for byte enable on NP cmd/byte enable register
*/
-#define IXP425_PCI_NP_CBE_BESL 4
+#define IXP425_PCI_NP_CBE_BESL 4
/*
* PCI commands supported by NP access unit
*/
-#define NP_CMD_IOREAD 0x2
-#define NP_CMD_IOWRITE 0x3
-#define NP_CMD_CONFIGREAD 0xa
-#define NP_CMD_CONFIGWRITE 0xb
-#define NP_CMD_MEMREAD 0x6
-#define NP_CMD_MEMWRITE 0x7
+#define NP_CMD_IOREAD 0x2
+#define NP_CMD_IOWRITE 0x3
+#define NP_CMD_CONFIGREAD 0xa
+#define NP_CMD_CONFIGWRITE 0xb
+#define NP_CMD_MEMREAD 0x6
+#define NP_CMD_MEMWRITE 0x7
#if 0
#ifndef __ASSEMBLY__
diff --git a/include/asm-arm/arch-omap24xx/clocks.h b/include/asm-arm/arch-omap24xx/clocks.h
index 2a95af1..2e92569 100644
--- a/include/asm-arm/arch-omap24xx/clocks.h
+++ b/include/asm-arm/arch-omap24xx/clocks.h
@@ -35,9 +35,9 @@
; PRCM Scheme II
;
; Enable clocks and DPLL for:
-; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50
-; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
-; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0]
+; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50
+; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
+; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0]
; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0]
; DSPI=100 6 CM_CLKSEL_DSP[6:5]
; DSP_S bypass CM_CLKSEL_DSP[7]
@@ -64,9 +64,9 @@
; PRCM Scheme III
;
; Enable clocks and DPLL for:
-; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266
-; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
-; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0]
+; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266
+; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
+; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0]
; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0]
; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5]
; DSP_S ACTIVATED CM_CLKSEL_DSP[7]
diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h
index 2ac5ea2..104a21c 100644
--- a/include/asm-arm/arch-pxa/bitfield.h
+++ b/include/asm-arm/arch-pxa/bitfield.h
@@ -1,13 +1,13 @@
/*
- * FILE bitfield.h
+ * FILE bitfield.h
*
- * Version 1.1
- * Author Copyright (c) Marc A. Viredaz, 1998
- * DEC Western Research Laboratory, Palo Alto, CA
- * Date April 1998 (April 1997)
- * System Advanced RISC Machine (ARM)
+ * Version 1.1
+ * Author Copyright (c) Marc A. Viredaz, 1998
+ * DEC Western Research Laboratory, Palo Alto, CA
+ * Date April 1998 (April 1997)
+ * System Advanced RISC Machine (ARM)
* Language C or ARM Assembly
- * Purpose Definition of macros to operate on bit fields.
+ * Purpose Definition of macros to operate on bit fields.
*/
@@ -35,11 +35,11 @@
* line-size limit).
*
* Input
- * Size Size of the bit field, in number of bits.
- * Shft Shift value of the bit field with respect to bit 0.
+ * Size Size of the bit field, in number of bits.
+ * Shft Shift value of the bit field with respect to bit 0.
*
* Output
- * Fld Encoded bit field.
+ * Fld Encoded bit field.
*/
#define Fld(Size, Shft) (((Size) << 16) + (Shft))
@@ -54,14 +54,14 @@
* bit field.
*
* Input
- * Field Encoded bit field (using the macro "Fld").
+ * Field Encoded bit field (using the macro "Fld").
*
* Output
- * FSize Size of the bit field, in number of bits.
- * FShft Shift value of the bit field with respect to bit 0.
- * FMsk Mask for the bit field.
- * FAlnMsk Mask for the bit field, aligned on bit 0.
- * F1stBit First bit of the bit field.
+ * FSize Size of the bit field, in number of bits.
+ * FShft Shift value of the bit field with respect to bit 0.
+ * FMsk Mask for the bit field.
+ * FAlnMsk Mask for the bit field, aligned on bit 0.
+ * F1stBit First bit of the bit field.
*/
#define FSize(Field) ((Field) >> 16)
@@ -79,11 +79,11 @@
* former appropriately.
*
* Input
- * Value Bit-field value.
- * Field Encoded bit field (using the macro "Fld").
+ * Value Bit-field value.
+ * Field Encoded bit field (using the macro "Fld").
*
* Output
- * FInsrt Bit-field value positioned appropriately.
+ * FInsrt Bit-field value positioned appropriately.
*/
#define FInsrt(Value, Field) \
@@ -98,11 +98,11 @@
* shifting it appropriately.
*
* Input
- * Data Data containing the bit-field to be extracted.
- * Field Encoded bit field (using the macro "Fld").
+ * Data Data containing the bit-field to be extracted.
+ * Field Encoded bit field (using the macro "Fld").
*
* Output
- * FExtr Bit-field value.
+ * FExtr Bit-field value.
*/
#define FExtr(Data, Field) \
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
index b9304b1..9440d80 100644
--- a/include/asm-arm/arch-pxa/mmc.h
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -16,95 +16,95 @@
/* PXA-250 MMC controller registers */
/* MMC_STRPCL */
-#define MMC_STRPCL_STOP_CLK (0x0001UL)
+#define MMC_STRPCL_STOP_CLK (0x0001UL)
#define MMC_STRPCL_START_CLK (0x0002UL)
/* MMC_STAT */
#define MMC_STAT_END_CMD_RES (0x0001UL << 13)
-#define MMC_STAT_PRG_DONE (0x0001UL << 12)
-#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11)
-#define MMC_STAT_CLK_EN (0x0001UL << 8)
-#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7)
-#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6)
-#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5)
+#define MMC_STAT_PRG_DONE (0x0001UL << 12)
+#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11)
+#define MMC_STAT_CLK_EN (0x0001UL << 8)
+#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7)
+#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6)
+#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5)
#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4)
-#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3)
-#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2)
-#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1)
-#define MMC_STAT_READ_TIME_OUT (0x0001UL)
+#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3)
+#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2)
+#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1)
+#define MMC_STAT_READ_TIME_OUT (0x0001UL)
#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
|MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
|MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
/* MMC_CLKRT */
-#define MMC_CLKRT_20MHZ (0x0000UL)
-#define MMC_CLKRT_10MHZ (0x0001UL)
-#define MMC_CLKRT_5MHZ (0x0002UL)
+#define MMC_CLKRT_20MHZ (0x0000UL)
+#define MMC_CLKRT_10MHZ (0x0001UL)
+#define MMC_CLKRT_5MHZ (0x0002UL)
#define MMC_CLKRT_2_5MHZ (0x0003UL)
-#define MMC_CLKRT_1_25MHZ (0x0004UL)
-#define MMC_CLKRT_0_625MHZ (0x0005UL)
-#define MMC_CLKRT_0_3125MHZ (0x0006UL)
+#define MMC_CLKRT_1_25MHZ (0x0004UL)
+#define MMC_CLKRT_0_625MHZ (0x0005UL)
+#define MMC_CLKRT_0_3125MHZ (0x0006UL)
/* MMC_SPI */
-#define MMC_SPI_DISABLE (0x00UL)
-#define MMC_SPI_EN (0x01UL)
-#define MMC_SPI_CS_EN (0x01UL << 2)
-#define MMC_SPI_CS_ADDRESS (0x01UL << 3)
-#define MMC_SPI_CRC_ON (0x01UL << 1)
+#define MMC_SPI_DISABLE (0x00UL)
+#define MMC_SPI_EN (0x01UL)
+#define MMC_SPI_CS_EN (0x01UL << 2)
+#define MMC_SPI_CS_ADDRESS (0x01UL << 3)
+#define MMC_SPI_CRC_ON (0x01UL << 1)
/* MMC_CMDAT */
#define MMC_CMDAT_SD_4DAT (0x0001UL << 8)
#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7)
-#define MMC_CMDAT_INIT (0x0001UL << 6)
-#define MMC_CMDAT_BUSY (0x0001UL << 5)
-#define MMC_CMDAT_BCR (0x0003UL << 5)
+#define MMC_CMDAT_INIT (0x0001UL << 6)
+#define MMC_CMDAT_BUSY (0x0001UL << 5)
+#define MMC_CMDAT_BCR (0x0003UL << 5)
#define MMC_CMDAT_STREAM (0x0001UL << 4)
-#define MMC_CMDAT_BLOCK (0x0000UL << 4)
-#define MMC_CMDAT_WRITE (0x0001UL << 3)
-#define MMC_CMDAT_READ (0x0000UL << 3)
-#define MMC_CMDAT_DATA_EN (0x0001UL << 2)
-#define MMC_CMDAT_R0 (0)
-#define MMC_CMDAT_R1 (0x0001UL)
-#define MMC_CMDAT_R2 (0x0002UL)
-#define MMC_CMDAT_R3 (0x0003UL)
+#define MMC_CMDAT_BLOCK (0x0000UL << 4)
+#define MMC_CMDAT_WRITE (0x0001UL << 3)
+#define MMC_CMDAT_READ (0x0000UL << 3)
+#define MMC_CMDAT_DATA_EN (0x0001UL << 2)
+#define MMC_CMDAT_R0 (0)
+#define MMC_CMDAT_R1 (0x0001UL)
+#define MMC_CMDAT_R2 (0x0002UL)
+#define MMC_CMDAT_R3 (0x0003UL)
/* MMC_RESTO */
-#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */
+#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */
/* MMC_RDTO */
-#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */
+#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */
/* MMC_BLKLEN */
-#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */
+#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */
/* MMC_PRTBUF */
-#define MMC_PRTBUF_BUF_PART_FULL (0x01UL)
+#define MMC_PRTBUF_BUF_PART_FULL (0x01UL)
#define MMC_PRTBUF_BUF_FULL (0x00UL )
/* MMC_I_MASK */
#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6)
#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5)
-#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4)
-#define MMC_I_MASK_STOP_CMD (0x01UL << 3)
-#define MMC_I_MASK_END_CMD_RES (0x01UL << 2)
-#define MMC_I_MASK_PRG_DONE (0x01UL << 1)
+#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4)
+#define MMC_I_MASK_STOP_CMD (0x01UL << 3)
+#define MMC_I_MASK_END_CMD_RES (0x01UL << 2)
+#define MMC_I_MASK_PRG_DONE (0x01UL << 1)
#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL)
-#define MMC_I_MASK_ALL (0x07fUL)
+#define MMC_I_MASK_ALL (0x07fUL)
/* MMC_I_REG */
-#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6)
-#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5)
+#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6)
+#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5)
#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4)
-#define MMC_I_REG_STOP_CMD (0x01UL << 3)
-#define MMC_I_REG_END_CMD_RES (0x01UL << 2)
-#define MMC_I_REG_PRG_DONE (0x01UL << 1)
-#define MMC_I_REG_DATA_TRAN_DONE (0x01UL)
-#define MMC_I_REG_ALL (0x007fUL)
+#define MMC_I_REG_STOP_CMD (0x01UL << 3)
+#define MMC_I_REG_END_CMD_RES (0x01UL << 2)
+#define MMC_I_REG_PRG_DONE (0x01UL << 1)
+#define MMC_I_REG_DATA_TRAN_DONE (0x01UL)
+#define MMC_I_REG_ALL (0x007fUL)
/* MMC_CMD */
-#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */
+#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */
#define CMD(x) (x)
#define MMC_DEFAULT_RCA 1
@@ -112,11 +112,11 @@
#define MMC_BLOCK_SIZE 512
#define MMC_CMD_RESET 0
#define MMC_CMD_SEND_OP_COND 1
-#define MMC_CMD_ALL_SEND_CID 2
+#define MMC_CMD_ALL_SEND_CID 2
#define MMC_CMD_SET_RCA 3
#define MMC_CMD_SELECT_CARD 7
-#define MMC_CMD_SEND_CSD 9
-#define MMC_CMD_SEND_CID 10
+#define MMC_CMD_SEND_CSD 9
+#define MMC_CMD_SEND_CID 10
#define MMC_CMD_SEND_STATUS 13
#define MMC_CMD_SET_BLOCKLEN 16
#define MMC_CMD_READ_BLOCK 17
@@ -203,5 +203,4 @@ typedef struct mmc_csd
ecc:2;
} mmc_csd_t;
-
#endif /* __MMC_PXA_P_H__ */
diff --git a/include/asm-arm/arch-s3c24x0/memory.h b/include/asm-arm/arch-s3c24x0/memory.h
index 333f218..5e254d2 100644
--- a/include/asm-arm/arch-s3c24x0/memory.h
+++ b/include/asm-arm/arch-s3c24x0/memory.h
@@ -103,10 +103,10 @@ extern unsigned long __phys_to_virt(unsigned long ppage);
* The nodes are matched with the physical memory bank addresses which are
* incidentally the same as virtual addresses.
*
- * node 0: 0xc0000000 - 0xc7ffffff
- * node 1: 0xc8000000 - 0xcfffffff
- * node 2: 0xd0000000 - 0xd7ffffff
- * node 3: 0xd8000000 - 0xdfffffff
+ * node 0: 0xc0000000 - 0xc7ffffff
+ * node 1: 0xc8000000 - 0xcfffffff
+ * node 2: 0xd0000000 - 0xd7ffffff
+ * node 3: 0xd8000000 - 0xdfffffff
*/
#define NR_NODES 4
diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h
index 2ac5ea2..104a21c 100644
--- a/include/asm-arm/arch-sa1100/bitfield.h
+++ b/include/asm-arm/arch-sa1100/bitfield.h
@@ -1,13 +1,13 @@
/*
- * FILE bitfield.h
+ * FILE bitfield.h
*
- * Version 1.1
- * Author Copyright (c) Marc A. Viredaz, 1998
- * DEC Western Research Laboratory, Palo Alto, CA
- * Date April 1998 (April 1997)
- * System Advanced RISC Machine (ARM)
+ * Version 1.1
+ * Author Copyright (c) Marc A. Viredaz, 1998
+ * DEC Western Research Laboratory, Palo Alto, CA
+ * Date April 1998 (April 1997)
+ * System Advanced RISC Machine (ARM)
* Language C or ARM Assembly
- * Purpose Definition of macros to operate on bit fields.
+ * Purpose Definition of macros to operate on bit fields.
*/
@@ -35,11 +35,11 @@
* line-size limit).
*
* Input
- * Size Size of the bit field, in number of bits.
- * Shft Shift value of the bit field with respect to bit 0.
+ * Size Size of the bit field, in number of bits.
+ * Shft Shift value of the bit field with respect to bit 0.
*
* Output
- * Fld Encoded bit field.
+ * Fld Encoded bit field.
*/
#define Fld(Size, Shft) (((Size) << 16) + (Shft))
@@ -54,14 +54,14 @@
* bit field.
*
* Input
- * Field Encoded bit field (using the macro "Fld").
+ * Field Encoded bit field (using the macro "Fld").
*
* Output
- * FSize Size of the bit field, in number of bits.
- * FShft Shift value of the bit field with respect to bit 0.
- * FMsk Mask for the bit field.
- * FAlnMsk Mask for the bit field, aligned on bit 0.
- * F1stBit First bit of the bit field.
+ * FSize Size of the bit field, in number of bits.
+ * FShft Shift value of the bit field with respect to bit 0.
+ * FMsk Mask for the bit field.
+ * FAlnMsk Mask for the bit field, aligned on bit 0.
+ * F1stBit First bit of the bit field.
*/
#define FSize(Field) ((Field) >> 16)
@@ -79,11 +79,11 @@
* former appropriately.
*
* Input
- * Value Bit-field value.
- * Field Encoded bit field (using the macro "Fld").
+ * Value Bit-field value.
+ * Field Encoded bit field (using the macro "Fld").
*
* Output
- * FInsrt Bit-field value positioned appropriately.
+ * FInsrt Bit-field value positioned appropriately.
*/
#define FInsrt(Value, Field) \
@@ -98,11 +98,11 @@
* shifting it appropriately.
*
* Input
- * Data Data containing the bit-field to be extracted.
- * Field Encoded bit field (using the macro "Fld").
+ * Data Data containing the bit-field to be extracted.
+ * Field Encoded bit field (using the macro "Fld").
*
* Output
- * FExtr Bit-field value.
+ * FExtr Bit-field value.
*/
#define FExtr(Data, Field) \
diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h
index 0410b5e..7564ff1 100644
--- a/include/asm-arm/global_data.h
+++ b/include/asm-arm/global_data.h
@@ -61,6 +61,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8")
diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h
index c120312..b11d555 100644
--- a/include/asm-arm/u-boot.h
+++ b/include/asm-arm/u-boot.h
@@ -47,7 +47,7 @@ typedef struct bd_info {
{
ulong start;
ulong size;
- } bi_dram[CONFIG_NR_DRAM_BANKS];
+ } bi_dram[CONFIG_NR_DRAM_BANKS];
#ifdef CONFIG_HAS_ETH1
/* second onboard ethernet port */
unsigned char bi_enet1addr[6];
diff --git a/include/asm-avr32/arch-at32ap700x/chip-features.h b/include/asm-avr32/arch-at32ap700x/chip-features.h
index 29b1fd6..c47107e 100644
--- a/include/asm-avr32/arch-at32ap700x/chip-features.h
+++ b/include/asm-avr32/arch-at32ap700x/chip-features.h
@@ -25,6 +25,7 @@
/* Currently, all the AP700x chips have these */
#define AT32AP700x_CHIP_HAS_USART
#define AT32AP700x_CHIP_HAS_MMCI
+#define AT32AP700x_CHIP_HAS_SPI
/* Only AP7000 has ethernet interface */
#ifdef CONFIG_AT32AP7000
diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
index 385319a..a9d8431 100644
--- a/include/asm-avr32/arch-at32ap700x/clk.h
+++ b/include/asm-avr32/arch-at32ap700x/clk.h
@@ -58,7 +58,7 @@ static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
return get_pba_clk_rate();
}
#endif
-#ifdef AT32AP700x_CHIP_HAS_USART
+#ifdef AT32AP700x_CHIP_HAS_MACB
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
{
return get_pbb_clk_rate();
@@ -74,6 +74,14 @@ static inline unsigned long get_mci_clk_rate(void)
return get_pbb_clk_rate();
}
#endif
+#ifdef AT32AP700x_CHIP_HAS_SPI
+static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
+{
+ return get_pba_clk_rate();
+}
+#endif
+
+extern void clk_init(void);
/* Board code may need the SDRAM base clock as a compile-time constant */
#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h
index b10a3e4..ef20cea 100644
--- a/include/asm-avr32/arch-at32ap700x/gpio.h
+++ b/include/asm-avr32/arch-at32ap700x/gpio.h
@@ -216,5 +216,9 @@ void gpio_enable_macb1(void);
#ifdef AT32AP700x_CHIP_HAS_MMCI
void gpio_enable_mmci(void);
#endif
+#ifdef AT32AP700x_CHIP_HAS_SPI
+void gpio_enable_spi0(unsigned long cs_mask);
+void gpio_enable_spi1(unsigned long cs_mask);
+#endif
#endif /* __ASM_AVR32_ARCH_GPIO_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/hmatrix.h b/include/asm-avr32/arch-at32ap700x/hmatrix.h
new file mode 100644
index 0000000..d6b6263
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/hmatrix.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_HMATRIX_H__
+#define __ASM_AVR32_ARCH_HMATRIX_H__
+
+#include <asm/hmatrix-common.h>
+
+/* Bitfields in SFR4 (EBI) */
+#define HMATRIX_EBI_SDRAM_ENABLE_OFFSET 1
+#define HMATRIX_EBI_SDRAM_ENABLE_SIZE 1
+#define HMATRIX_EBI_NAND_ENABLE_OFFSET 3
+#define HMATRIX_EBI_NAND_ENABLE_SIZE 1
+#define HMATRIX_EBI_CF0_ENABLE_OFFSET 4
+#define HMATRIX_EBI_CF0_ENABLE_SIZE 1
+#define HMATRIX_EBI_CF1_ENABLE_OFFSET 5
+#define HMATRIX_EBI_CF1_ENABLE_SIZE 1
+#define HMATRIX_EBI_PULLUP_DISABLE_OFFSET 8
+#define HMATRIX_EBI_PULLUP_DISABLE_SIZE 1
+
+/* HSB masters */
+#define HMATRIX_MASTER_CPU_DCACHE 0
+#define HMATRIX_MASTER_CPU_ICACHE 1
+#define HMATRIX_MASTER_PDC 2
+#define HMATRIX_MASTER_ISI 3
+#define HMATRIX_MASTER_USBA 4
+#define HMATRIX_MASTER_LCDC 5
+#define HMATRIX_MASTER_MACB0 6
+#define HMATRIX_MASTER_MACB1 7
+#define HMATRIX_MASTER_DMACA_M0 8
+#define HMATRIX_MASTER_DMACA_M1 9
+
+/* HSB slaves */
+#define HMATRIX_SLAVE_SRAM0 0
+#define HMATRIX_SLAVE_SRAM1 1
+#define HMATRIX_SLAVE_PBA 2
+#define HMATRIX_SLAVE_PBB 3
+#define HMATRIX_SLAVE_EBI 4
+#define HMATRIX_SLAVE_USBA 5
+#define HMATRIX_SLAVE_LCDC 6
+#define HMATRIX_SLAVE_DMACA 7
+
+#endif /* __ASM_AVR32_ARCH_HMATRIX_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/hmatrix2.h b/include/asm-avr32/arch-at32ap700x/hmatrix2.h
deleted file mode 100644
index b0e787a..0000000
--- a/include/asm-avr32/arch-at32ap700x/hmatrix2.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * Register definition for the High-speed Bus Matrix
- */
-#ifndef __ASM_AVR32_HMATRIX2_H__
-#define __ASM_AVR32_HMATRIX2_H__
-
-/* HMATRIX2 register offsets */
-#define HMATRIX2_MCFG0 0x0000
-#define HMATRIX2_MCFG1 0x0004
-#define HMATRIX2_MCFG2 0x0008
-#define HMATRIX2_MCFG3 0x000c
-#define HMATRIX2_MCFG4 0x0010
-#define HMATRIX2_MCFG5 0x0014
-#define HMATRIX2_MCFG6 0x0018
-#define HMATRIX2_MCFG7 0x001c
-#define HMATRIX2_MCFG8 0x0020
-#define HMATRIX2_MCFG9 0x0024
-#define HMATRIX2_MCFG10 0x0028
-#define HMATRIX2_MCFG11 0x002c
-#define HMATRIX2_MCFG12 0x0030
-#define HMATRIX2_MCFG13 0x0034
-#define HMATRIX2_MCFG14 0x0038
-#define HMATRIX2_MCFG15 0x003c
-#define HMATRIX2_SCFG0 0x0040
-#define HMATRIX2_SCFG1 0x0044
-#define HMATRIX2_SCFG2 0x0048
-#define HMATRIX2_SCFG3 0x004c
-#define HMATRIX2_SCFG4 0x0050
-#define HMATRIX2_SCFG5 0x0054
-#define HMATRIX2_SCFG6 0x0058
-#define HMATRIX2_SCFG7 0x005c
-#define HMATRIX2_SCFG8 0x0060
-#define HMATRIX2_SCFG9 0x0064
-#define HMATRIX2_SCFG10 0x0068
-#define HMATRIX2_SCFG11 0x006c
-#define HMATRIX2_SCFG12 0x0070
-#define HMATRIX2_SCFG13 0x0074
-#define HMATRIX2_SCFG14 0x0078
-#define HMATRIX2_SCFG15 0x007c
-#define HMATRIX2_PRAS0 0x0080
-#define HMATRIX2_PRBS0 0x0084
-#define HMATRIX2_PRAS1 0x0088
-#define HMATRIX2_PRBS1 0x008c
-#define HMATRIX2_PRAS2 0x0090
-#define HMATRIX2_PRBS2 0x0094
-#define HMATRIX2_PRAS3 0x0098
-#define HMATRIX2_PRBS3 0x009c
-#define HMATRIX2_PRAS4 0x00a0
-#define HMATRIX2_PRBS4 0x00a4
-#define HMATRIX2_PRAS5 0x00a8
-#define HMATRIX2_PRBS5 0x00ac
-#define HMATRIX2_PRAS6 0x00b0
-#define HMATRIX2_PRBS6 0x00b4
-#define HMATRIX2_PRAS7 0x00b8
-#define HMATRIX2_PRBS7 0x00bc
-#define HMATRIX2_PRAS8 0x00c0
-#define HMATRIX2_PRBS8 0x00c4
-#define HMATRIX2_PRAS9 0x00c8
-#define HMATRIX2_PRBS9 0x00cc
-#define HMATRIX2_PRAS10 0x00d0
-#define HMATRIX2_PRBS10 0x00d4
-#define HMATRIX2_PRAS11 0x00d8
-#define HMATRIX2_PRBS11 0x00dc
-#define HMATRIX2_PRAS12 0x00e0
-#define HMATRIX2_PRBS12 0x00e4
-#define HMATRIX2_PRAS13 0x00e8
-#define HMATRIX2_PRBS13 0x00ec
-#define HMATRIX2_PRAS14 0x00f0
-#define HMATRIX2_PRBS14 0x00f4
-#define HMATRIX2_PRAS15 0x00f8
-#define HMATRIX2_PRBS15 0x00fc
-#define HMATRIX2_MRCR 0x0100
-#define HMATRIX2_SFR0 0x0110
-#define HMATRIX2_SFR1 0x0114
-#define HMATRIX2_SFR2 0x0118
-#define HMATRIX2_SFR3 0x011c
-#define HMATRIX2_SFR4 0x0120
-#define HMATRIX2_SFR5 0x0124
-#define HMATRIX2_SFR6 0x0128
-#define HMATRIX2_SFR7 0x012c
-#define HMATRIX2_SFR8 0x0130
-#define HMATRIX2_SFR9 0x0134
-#define HMATRIX2_SFR10 0x0138
-#define HMATRIX2_SFR11 0x013c
-#define HMATRIX2_SFR12 0x0140
-#define HMATRIX2_SFR13 0x0144
-#define HMATRIX2_SFR14 0x0148
-#define HMATRIX2_SFR15 0x014c
-#define HMATRIX2_VERSION 0x01fc
-
-/* Bitfields in MCFG0 */
-#define HMATRIX2_ULBT_OFFSET 0
-#define HMATRIX2_ULBT_SIZE 3
-
-/* Bitfields in SCFG0 */
-#define HMATRIX2_SLOT_CYCLE_OFFSET 0
-#define HMATRIX2_SLOT_CYCLE_SIZE 8
-#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16
-#define HMATRIX2_DEFMSTR_TYPE_SIZE 2
-#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18
-#define HMATRIX2_FIXED_DEFMSTR_SIZE 4
-#define HMATRIX2_ARBT_OFFSET 24
-#define HMATRIX2_ARBT_SIZE 2
-
-/* Bitfields in PRAS0 */
-#define HMATRIX2_M0PR_OFFSET 0
-#define HMATRIX2_M0PR_SIZE 4
-#define HMATRIX2_M1PR_OFFSET 4
-#define HMATRIX2_M1PR_SIZE 4
-#define HMATRIX2_M2PR_OFFSET 8
-#define HMATRIX2_M2PR_SIZE 4
-#define HMATRIX2_M3PR_OFFSET 12
-#define HMATRIX2_M3PR_SIZE 4
-#define HMATRIX2_M4PR_OFFSET 16
-#define HMATRIX2_M4PR_SIZE 4
-#define HMATRIX2_M5PR_OFFSET 20
-#define HMATRIX2_M5PR_SIZE 4
-#define HMATRIX2_M6PR_OFFSET 24
-#define HMATRIX2_M6PR_SIZE 4
-#define HMATRIX2_M7PR_OFFSET 28
-#define HMATRIX2_M7PR_SIZE 4
-
-/* Bitfields in PRBS0 */
-#define HMATRIX2_M8PR_OFFSET 0
-#define HMATRIX2_M8PR_SIZE 4
-#define HMATRIX2_M9PR_OFFSET 4
-#define HMATRIX2_M9PR_SIZE 4
-#define HMATRIX2_M10PR_OFFSET 8
-#define HMATRIX2_M10PR_SIZE 4
-#define HMATRIX2_M11PR_OFFSET 12
-#define HMATRIX2_M11PR_SIZE 4
-#define HMATRIX2_M12PR_OFFSET 16
-#define HMATRIX2_M12PR_SIZE 4
-#define HMATRIX2_M13PR_OFFSET 20
-#define HMATRIX2_M13PR_SIZE 4
-#define HMATRIX2_M14PR_OFFSET 24
-#define HMATRIX2_M14PR_SIZE 4
-#define HMATRIX2_M15PR_OFFSET 28
-#define HMATRIX2_M15PR_SIZE 4
-
-/* Bitfields in MRCR */
-#define HMATRIX2_RBC0_OFFSET 0
-#define HMATRIX2_RBC0_SIZE 1
-#define HMATRIX2_RBC1_OFFSET 1
-#define HMATRIX2_RBC1_SIZE 1
-#define HMATRIX2_RBC2_OFFSET 2
-#define HMATRIX2_RBC2_SIZE 1
-#define HMATRIX2_RBC3_OFFSET 3
-#define HMATRIX2_RBC3_SIZE 1
-#define HMATRIX2_RBC4_OFFSET 4
-#define HMATRIX2_RBC4_SIZE 1
-#define HMATRIX2_RBC5_OFFSET 5
-#define HMATRIX2_RBC5_SIZE 1
-#define HMATRIX2_RBC6_OFFSET 6
-#define HMATRIX2_RBC6_SIZE 1
-#define HMATRIX2_RBC7_OFFSET 7
-#define HMATRIX2_RBC7_SIZE 1
-#define HMATRIX2_RBC8_OFFSET 8
-#define HMATRIX2_RBC8_SIZE 1
-#define HMATRIX2_RBC9_OFFSET 9
-#define HMATRIX2_RBC9_SIZE 1
-#define HMATRIX2_RBC10_OFFSET 10
-#define HMATRIX2_RBC10_SIZE 1
-#define HMATRIX2_RBC11_OFFSET 11
-#define HMATRIX2_RBC11_SIZE 1
-#define HMATRIX2_RBC12_OFFSET 12
-#define HMATRIX2_RBC12_SIZE 1
-#define HMATRIX2_RBC13_OFFSET 13
-#define HMATRIX2_RBC13_SIZE 1
-#define HMATRIX2_RBC14_OFFSET 14
-#define HMATRIX2_RBC14_SIZE 1
-#define HMATRIX2_RBC15_OFFSET 15
-#define HMATRIX2_RBC15_SIZE 1
-
-/* Bitfields in SFR0 */
-#define HMATRIX2_SFR_OFFSET 0
-#define HMATRIX2_SFR_SIZE 32
-
-/* Bitfields in SFR4 */
-#define HMATRIX2_CS1A_OFFSET 1
-#define HMATRIX2_CS1A_SIZE 1
-#define HMATRIX2_CS3A_OFFSET 3
-#define HMATRIX2_CS3A_SIZE 1
-#define HMATRIX2_CS4A_OFFSET 4
-#define HMATRIX2_CS4A_SIZE 1
-#define HMATRIX2_CS5A_OFFSET 5
-#define HMATRIX2_CS5A_SIZE 1
-#define HMATRIX2_DBPUC_OFFSET 8
-#define HMATRIX2_DBPUC_SIZE 1
-
-/* Bitfields in VERSION */
-#define HMATRIX2_VERSION_OFFSET 0
-#define HMATRIX2_VERSION_SIZE 12
-#define HMATRIX2_MFN_OFFSET 16
-#define HMATRIX2_MFN_SIZE 3
-
-/* Constants for ULBT */
-#define HMATRIX2_ULBT_INFINITE 0
-#define HMATRIX2_ULBT_SINGLE 1
-#define HMATRIX2_ULBT_FOUR_BEAT 2
-#define HMATRIX2_ULBT_SIXTEEN_BEAT 4
-
-/* Constants for DEFMSTR_TYPE */
-#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0
-#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1
-#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2
-
-/* Constants for ARBT */
-#define HMATRIX2_ARBT_ROUND_ROBIN 0
-#define HMATRIX2_ARBT_FIXED_PRIORITY 1
-
-/* Bit manipulation macros */
-#define HMATRIX2_BIT(name) \
- (1 << HMATRIX2_##name##_OFFSET)
-#define HMATRIX2_BF(name,value) \
- (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \
- << HMATRIX2_##name##_OFFSET)
-#define HMATRIX2_BFEXT(name,value) \
- (((value) >> HMATRIX2_##name##_OFFSET) \
- & ((1 << HMATRIX2_##name##_SIZE) - 1))
-#define HMATRIX2_BFINS(name,value,old) \
- (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \
- << HMATRIX2_##name##_OFFSET)) \
- | HMATRIX2_BF(name,value))
-
-/* Register access macros */
-#define hmatrix2_readl(reg) \
- readl((void *)HMATRIX_BASE + HMATRIX2_##reg)
-#define hmatrix2_writel(reg,value) \
- writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg)
-
-#endif /* __ASM_AVR32_HMATRIX2_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/memory-map.h b/include/asm-avr32/arch-at32ap700x/memory-map.h
index 5513e88..6592c03 100644
--- a/include/asm-avr32/arch-at32ap700x/memory-map.h
+++ b/include/asm-avr32/arch-at32ap700x/memory-map.h
@@ -22,6 +22,26 @@
#ifndef __AT32AP7000_MEMORY_MAP_H__
#define __AT32AP7000_MEMORY_MAP_H__
+/* Internal and external memories */
+#define EBI_SRAM_CS0_BASE 0x00000000
+#define EBI_SRAM_CS0_SIZE 0x04000000
+#define EBI_SRAM_CS4_BASE 0x04000000
+#define EBI_SRAM_CS4_SIZE 0x04000000
+#define EBI_SRAM_CS2_BASE 0x08000000
+#define EBI_SRAM_CS2_SIZE 0x04000000
+#define EBI_SRAM_CS3_BASE 0x0c000000
+#define EBI_SRAM_CS3_SIZE 0x04000000
+#define EBI_SRAM_CS1_BASE 0x10000000
+#define EBI_SRAM_CS1_SIZE 0x10000000
+#define EBI_SRAM_CS5_BASE 0x20000000
+#define EBI_SRAM_CS5_SIZE 0x04000000
+
+#define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE
+#define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE
+
+#define INTERNAL_SRAM_BASE 0x24000000
+#define INTERNAL_SRAM_SIZE 0x00008000
+
/* Devices on the High Speed Bus (HSB) */
#define LCDC_BASE 0xFF000000
#define DMAC_BASE 0xFF200000
diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h
index fcfbbb3..6a33fef 100644
--- a/include/asm-avr32/arch-at32ap700x/mmc.h
+++ b/include/asm-avr32/arch-at32ap700x/mmc.h
@@ -74,13 +74,13 @@ struct mmc_csd
/* MMC Command numbers */
#define MMC_CMD_GO_IDLE_STATE 0
#define MMC_CMD_SEND_OP_COND 1
-#define MMC_CMD_ALL_SEND_CID 2
+#define MMC_CMD_ALL_SEND_CID 2
#define MMC_CMD_SET_RELATIVE_ADDR 3
#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3
#define MMC_CMD_SET_DSR 4
#define MMC_CMD_SELECT_CARD 7
-#define MMC_CMD_SEND_CSD 9
-#define MMC_CMD_SEND_CID 10
+#define MMC_CMD_SEND_CSD 9
+#define MMC_CMD_SEND_CID 10
#define MMC_CMD_SEND_STATUS 13
#define MMC_CMD_SET_BLOCKLEN 16
#define MMC_CMD_READ_SINGLE_BLOCK 17
diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h
index daf64bc..007cfe4 100644
--- a/include/asm-avr32/global_data.h
+++ b/include/asm-avr32/global_data.h
@@ -52,6 +52,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
diff --git a/include/asm-avr32/hmatrix-common.h b/include/asm-avr32/hmatrix-common.h
new file mode 100644
index 0000000..4b7e610
--- /dev/null
+++ b/include/asm-avr32/hmatrix-common.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_HMATRIX_COMMON_H__
+#define __ASM_AVR32_HMATRIX_COMMON_H__
+
+/* HMATRIX register offsets */
+struct hmatrix_regs {
+ u32 MCFG[16];
+ u32 SCFG[16];
+ struct {
+ u32 A;
+ u32 B;
+ } PRS[16];
+ u32 MRCR;
+ u32 __reserved[3];
+ u32 SFR[16];
+};
+
+/* Bitfields in MCFG */
+#define HMATRIX_ULBT_OFFSET 0
+#define HMATRIX_ULBT_SIZE 3
+
+/* Bitfields in SCFG */
+#define HMATRIX_SLOT_CYCLE_OFFSET 0
+#define HMATRIX_SLOT_CYCLE_SIZE 8
+#define HMATRIX_DEFMSTR_TYPE_OFFSET 16
+#define HMATRIX_DEFMSTR_TYPE_SIZE 2
+#define HMATRIX_FIXED_DEFMSTR_OFFSET 18
+#define HMATRIX_FIXED_DEFMSTR_SIZE 4
+#define HMATRIX_ARBT_OFFSET 24
+#define HMATRIX_ARBT_SIZE 1
+
+/* Bitfields in PRS.A */
+#define HMATRIX_M0PR_OFFSET 0
+#define HMATRIX_M0PR_SIZE 4
+#define HMATRIX_M1PR_OFFSET 4
+#define HMATRIX_M1PR_SIZE 4
+#define HMATRIX_M2PR_OFFSET 8
+#define HMATRIX_M2PR_SIZE 4
+#define HMATRIX_M3PR_OFFSET 12
+#define HMATRIX_M3PR_SIZE 4
+#define HMATRIX_M4PR_OFFSET 16
+#define HMATRIX_M4PR_SIZE 4
+#define HMATRIX_M5PR_OFFSET 20
+#define HMATRIX_M5PR_SIZE 4
+#define HMATRIX_M6PR_OFFSET 24
+#define HMATRIX_M6PR_SIZE 4
+#define HMATRIX_M7PR_OFFSET 28
+#define HMATRIX_M7PR_SIZE 4
+
+/* Bitfields in PRS.B */
+#define HMATRIX_M8PR_OFFSET 0
+#define HMATRIX_M8PR_SIZE 4
+#define HMATRIX_M9PR_OFFSET 4
+#define HMATRIX_M9PR_SIZE 4
+#define HMATRIX_M10PR_OFFSET 8
+#define HMATRIX_M10PR_SIZE 4
+#define HMATRIX_M11PR_OFFSET 12
+#define HMATRIX_M11PR_SIZE 4
+#define HMATRIX_M12PR_OFFSET 16
+#define HMATRIX_M12PR_SIZE 4
+#define HMATRIX_M13PR_OFFSET 20
+#define HMATRIX_M13PR_SIZE 4
+#define HMATRIX_M14PR_OFFSET 24
+#define HMATRIX_M14PR_SIZE 4
+#define HMATRIX_M15PR_OFFSET 28
+#define HMATRIX_M15PR_SIZE 4
+
+/* Constants for ULBT */
+#define HMATRIX_ULBT_INFINITE 0
+#define HMATRIX_ULBT_SINGLE 1
+#define HMATRIX_ULBT_FOUR_BEAT 2
+#define HMATRIX_ULBT_EIGHT_BEAT 3
+#define HMATRIX_ULBT_SIXTEEN_BEAT 4
+
+/* Constants for DEFMSTR_TYPE */
+#define HMATRIX_DEFMSTR_TYPE_NO_DEFAULT 0
+#define HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT 1
+#define HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT 2
+
+/* Constants for ARBT */
+#define HMATRIX_ARBT_ROUND_ROBIN 0
+#define HMATRIX_ARBT_FIXED_PRIORITY 1
+
+/* Bit manipulation macros */
+#define HMATRIX_BIT(name) \
+ (1 << HMATRIX_##name##_OFFSET)
+#define HMATRIX_BF(name,value) \
+ (((value) & ((1 << HMATRIX_##name##_SIZE) - 1)) \
+ << HMATRIX_##name##_OFFSET)
+#define HMATRIX_BFEXT(name,value) \
+ (((value) >> HMATRIX_##name##_OFFSET) \
+ & ((1 << HMATRIX_##name##_SIZE) - 1))
+#define HMATRIX_BFINS(name,value,old) \
+ (((old) & ~(((1 << HMATRIX_##name##_SIZE) - 1) \
+ << HMATRIX_##name##_OFFSET)) \
+ | HMATRIX_BF(name,value))
+
+/* Register access macros */
+#define __hmatrix_reg(reg) \
+ (((volatile struct hmatrix_regs *)HMATRIX_BASE)->reg)
+#define hmatrix_read(reg) \
+ (__hmatrix_reg(reg))
+#define hmatrix_write(reg, value) \
+ do { __hmatrix_reg(reg) = (value); } while (0)
+
+#define hmatrix_slave_read(slave, reg) \
+ hmatrix_read(reg[HMATRIX_SLAVE_##slave])
+#define hmatrix_slave_write(slave, reg, value) \
+ hmatrix_write(reg[HMATRIX_SLAVE_##slave], value)
+
+#endif /* __ASM_AVR32_HMATRIX_COMMON_H__ */
diff --git a/include/asm-avr32/sdram.h b/include/asm-avr32/sdram.h
index 833af6e..7bdefc1 100644
--- a/include/asm-avr32/sdram.h
+++ b/include/asm-avr32/sdram.h
@@ -22,15 +22,32 @@
#ifndef __ASM_AVR32_SDRAM_H
#define __ASM_AVR32_SDRAM_H
-struct sdram_info {
- unsigned long phys_addr;
- unsigned int row_bits, col_bits, bank_bits;
- unsigned int cas, twr, trc, trp, trcd, tras, txsr;
+struct sdram_config {
+ /* Number of data bits. */
+ enum {
+ SDRAM_DATA_16BIT,
+ SDRAM_DATA_32BIT,
+ } data_bits;
+
+ /* Number of address bits */
+ uint8_t row_bits, col_bits, bank_bits;
+
+ /* SDRAM timings in cycles */
+ uint8_t cas, twr, trc, trp, trcd, tras, txsr;
/* SDRAM refresh period in cycles */
unsigned long refresh_period;
};
-extern unsigned long sdram_init(const struct sdram_info *info);
+/*
+ * Attempt to initialize the SDRAM controller using the specified
+ * parameters. Return the expected size of the memory area based on
+ * the number of address and data bits.
+ *
+ * The caller should verify that the configuration is correct by
+ * running a memory test, e.g. get_ram_size().
+ */
+extern unsigned long sdram_init(void *sdram_base,
+ const struct sdram_config *config);
#endif /* __ASM_AVR32_SDRAM_H */
diff --git a/include/asm-avr32/sections.h b/include/asm-avr32/sections.h
index 75373ab..fe819b2 100644
--- a/include/asm-avr32/sections.h
+++ b/include/asm-avr32/sections.h
@@ -25,15 +25,8 @@
/* References to section boundaries */
extern char _text[], _etext[];
-extern char __flashprog_start[], __flashprog_end[];
extern char _data[], __data_lma[], _edata[], __edata_lma[];
extern char __got_start[], __got_lma[], __got_end[];
extern char _end[];
-/*
- * Everything in .flashprog will be locked in the icache so it doesn't
- * get disturbed when executing flash commands.
- */
-#define __flashprog __attribute__((section(".flashprog"), __noinline__))
-
#endif /* __ASM_AVR32_SECTIONS_H */
diff --git a/include/asm-avr32/u-boot.h b/include/asm-avr32/u-boot.h
index 71dfcaf..85ef008 100644
--- a/include/asm-avr32/u-boot.h
+++ b/include/asm-avr32/u-boot.h
@@ -42,15 +42,4 @@ typedef struct bd_info {
#define bi_memstart bi_dram[0].start
#define bi_memsize bi_dram[0].size
-/**
- * container_of - cast a member of a structure out to the containing structure
- *
- * @ptr: the pointer to the member.
- * @type: the type of the container struct this is embedded in.
- * @member: the name of the member within the struct.
- */
-#define container_of(ptr, type, member) ({ \
- const typeof( ((type *)0)->member ) *__mptr = (ptr); \
- (type *)( (char *)__mptr - offsetof(type,member) );})
-
#endif /* __ASM_U_BOOT_H__ */
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index 7aa712f..e36af2d 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -42,8 +42,8 @@
#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
+#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
+#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
/* Data Attibutes*/
diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h
index 6debfc7..4c88639 100644
--- a/include/asm-blackfin/global_data.h
+++ b/include/asm-blackfin/global_data.h
@@ -62,6 +62,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P5")
diff --git a/include/asm-blackfin/shared_resources.h b/include/asm-blackfin/shared_resources.h
index d280ffe..2ac8990 100644
--- a/include/asm-blackfin/shared_resources.h
+++ b/include/asm-blackfin/shared_resources.h
@@ -27,7 +27,7 @@
void swap_to(int device_id);
-#define FLASH 0
+#define FLASH 0
#define ETHERNET 1
#endif /* _SHARED_RESOURCES_H_ */
diff --git a/include/asm-i386/global_data.h b/include/asm-i386/global_data.h
index 68a9ad6..3235063 100644
--- a/include/asm-i386/global_data.h
+++ b/include/asm-i386/global_data.h
@@ -55,6 +55,8 @@ typedef struct {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
extern gd_t *global_data;
diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h
index d5abbbe..0f7e7a5 100644
--- a/include/asm-i386/ic/sc520.h
+++ b/include/asm-i386/ic/sc520.h
@@ -25,209 +25,209 @@
#define _ASM_IC_SC520_H_ 1
/* Memory mapped configuration registers, MMCR */
-#define SC520_REVID 0x0000 /* ElanSC520 Microcontroller Revision ID Register */
-#define SC520_CPUCTL 0x0002 /* Am5x86 CPU Control Register */
-#define SC520_DRCCTL 0x0010 /* SDRAM Control Register */
-#define SC520_DRCTMCTL 0x0012 /* SDRAM Timing Control Register */
-#define SC520_DRCCFG 0x0014 /* SDRAM Bank Configuration Register*/
-#define SC520_DRCBENDADR 0x0018 /* SDRAM Bank 0-3 Ending Address Register*/
-#define SC520_ECCCTL 0x0020 /* ECC Control Register */
-#define SC520_ECCSTA 0x0021 /* ECC Status Register */
-#define SC520_ECCCKBPOS 0x0022 /* ECC Check Bit Position Register */
-#define SC520_ECCSBADD 0x0024 /* ECC Single-Bit Error Address Register */
-#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */
-#define SC520_BOOTCSCTL 0x0050 /* /BOOTCS Control Register */
-#define SC520_ROMCS1CTL 0x0054 /* /ROMCS1 Control Register */
-#define SC520_ROMCS2CTL 0x0056 /* /ROMCS2 Control Register */
-#define SC520_HBCTL 0x0060 /* Host Bridge Control Register */
-#define SC520_HBTGTIRQCTL 0x0062 /* Host Bridge Target Interrupt Control Register */
-#define SC520_HBTGTIRQSTA 0x0064 /* Host Bridge Target Interrupt Status Register */
-#define SC520_HBMSTIRQCTL 0x0066 /* Host Bridge Target Interrupt Control Register */
-#define SC520_HBMSTIRQSTA 0x0068 /* Host Bridge Master Interrupt Status Register */
-#define SC520_MSTINTADD 0x006c /* Host Bridge Master Interrupt Address Register */
-#define SC520_SYSARBCTL 0x0070 /* System Arbiter Control Register */
-#define SC520_PCIARBSTA 0x0071 /* PCI Bus Arbiter Status Register */
-#define SC520_SYSARBMENB 0x0072 /* System Arbiter Master Enable Register */
-#define SC520_ARBPRICTL 0x0074 /* Arbiter Priority Control Register */
-#define SC520_ADDDECCTL 0x0080 /* Address Decode Control Register */
-#define SC520_WPVSTA 0x0082 /* Write-Protect Violation Status Register */
-#define SC520_PAR0 0x0088 /* Programmable Address Region 0 Register */
-#define SC520_PAR1 0x008c /* Programmable Address Region 1 Register */
-#define SC520_PAR2 0x0090 /* Programmable Address Region 2 Register */
-#define SC520_PAR3 0x0094 /* Programmable Address Region 3 Register */
-#define SC520_PAR4 0x0098 /* Programmable Address Region 4 Register */
-#define SC520_PAR5 0x009c /* Programmable Address Region 5 Register */
-#define SC520_PAR6 0x00a0 /* Programmable Address Region 6 Register */
-#define SC520_PAR7 0x00a4 /* Programmable Address Region 7 Register */
-#define SC520_PAR8 0x00a8 /* Programmable Address Region 8 Register */
-#define SC520_PAR9 0x00ac /* Programmable Address Region 9 Register */
-#define SC520_PAR10 0x00b0 /* Programmable Address Region 10 Register */
-#define SC520_PAR11 0x00b4 /* Programmable Address Region 11 Register */
-#define SC520_PAR12 0x00b8 /* Programmable Address Region 12 Register */
-#define SC520_PAR13 0x00bc /* Programmable Address Region 13 Register */
-#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */
-#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */
-#define SC520_GPECHO 0x0c00 /* GP Echo Mode Register */
-#define SC520_GPCSDW 0x0c01 /* GP Chip Select Data Width Register */
-#define SC520_GPCSQUAL 0x0c02 /* GP Chip Select Qualification Register */
-#define SC520_GPCSRT 0x0c08 /* GP Chip Select Recovery Time Register */
-#define SC520_GPCSPW 0x0c09 /* GP Chip Select Pulse Width Register */
-#define SC520_GPCSOFF 0x0c0a /* GP Chip Select Offset Register */
-#define SC520_GPRDW 0x0c0b /* GP Read Pulse Width Register */
-#define SC520_GPRDOFF 0x0c0c /* GP Read Offset Register */
-#define SC520_GPWRW 0x0c0d /* GP Write Pulse Width Register */
-#define SC520_GPWROFF 0x0c0e /* GP Write Offset Register */
-#define SC520_GPALEW 0x0c0f /* GP ALE Pulse Width Register */
-#define SC520_GPALEOFF 0x0c10 /* GP ALE Offset Register */
-#define SC520_PIOPFS15_0 0x0c20 /* PIO15-PIO0 Pin Function Select */
-#define SC520_PIOPFS31_16 0x0c22 /* PIO31-PIO16 Pin Function Select */
-#define SC520_CSPFS 0x0c24 /* Chip Select Pin Function Select */
-#define SC520_CLKSEL 0x0c26 /* Clock Select */
-#define SC520_DSCTL 0x0c28 /* Drive Strength Control */
-#define SC520_PIODIR15_0 0x0c2a /* PIO15-PIO0 Direction */
-#define SC520_PIODIR31_16 0x0c2c /* PIO31-PIO16 Direction */
-#define SC520_PIODATA15_0 0x0c30 /* PIO15-PIO0 Data */
-#define SC520_PIODATA31_16 0x0c32 /* PIO31-PIO16 Data */
-#define SC520_PIOSET15_0 0x0c34 /* PIO15-PIO0 Set */
-#define SC520_PIOSET31_16 0x0c36 /* PIO31-PIO16 Set */
-#define SC520_PIOCLR15_0 0x0c38 /* PIO15-PIO0 Clear */
-#define SC520_PIOCLR31_16 0x0c3a /* PIO31-PIO16 Clear */
-#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */
-#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */
-#define SC520_SWTMRCFG 0x0c64 /* Software Timer Configuration */
-#define SC520_GPTMRSTA 0x0c70 /* GP Timers Status Register */
-#define SC520_GPTMR0CTL 0x0c72 /* GP Timer 0 Mode/Control Register */
-#define SC520_GPTMR0CNT 0x0c74 /* GP Timer 0 Count Register */
-#define SC520_GPTMR0MAXCMPA 0x0c76 /* GP Timer 0 Maxcount Compare A Register */
-#define SC520_GPTMR0MAXCMPB 0x0c78 /* GP Timer 0 Maxcount Compare B Register */
-#define SC520_GPTMR1CTL 0x0c7a /* GP Timer 1 Mode/Control Register */
-#define SC520_GPTMR1CNT 0x0c7c /* GP Timer 1 Count Register */
-#define SC520_GPTMR1MAXCMPA 0x0c7e /* GP Timer 1 Maxcount Compare Register A */
-#define SC520_GPTMR1MAXCMPB 0x0c80 /* GP Timer 1 Maxcount Compare B Register */
-#define SC520_GPTMR2CTL 0x0c82 /* GP Timer 2 Mode/Control Register */
-#define SC520_GPTMR2CNT 0x0c84 /* GP Timer 2 Count Register */
-#define SC520_GPTMR2MAXCMPA 0x0c8e /* GP Timer 2 Maxcount Compare A Register */
-#define SC520_WDTMRCTL 0x0cb0 /* Watchdog Timer Control Register */
-#define SC520_WDTMRCNTL 0x0cb2 /* Watchdog Timer Count Low Register */
-#define SC520_WDTMRCNTH 0x0cb4 /* Watchdog Timer Count High Register */
-#define SC520_UART1CTL 0x0cc0 /* UART 1 General Control Register */
-#define SC520_UART1STA 0x0cc1 /* UART 1 General Status Register */
-#define SC520_UART1FCRSHAD 0x0cc2 /* UART 1 FIFO Control Shadow Register */
-#define SC520_UART2CTL 0x0cc4 /* UART 2 General Control Register */
-#define SC520_UART2STA 0x0cc5 /* UART 2 General Status Register */
-#define SC520_UART2FCRSHAD 0x0cc6 /* UART 2 FIFO Control Shadow Register */
-#define SC520_SSICTL 0x0cd0 /* SSI Control */
-#define SC520_SSIXMIT 0x0cd1 /* SSI Transmit */
-#define SC520_SSICMD 0x0cd2 /* SSI Command */
-#define SC520_SSISTA 0x0cd3 /* SSI Status */
-#define SC520_SSIRCV 0x0cd4 /* SSI Receive */
-#define SC520_PICICR 0x0d00 /* Interrupt Control Register */
-#define SC520_MPICMODE 0x0d02 /* Master PIC Interrupt Mode Register */
-#define SC520_SL1PICMODE 0x0d03 /* Slave 1 PIC Interrupt Mode Register */
-#define SC520_SL2PICMODE 0x0d04 /* Slave 2 PIC Interrupt Mode Register */
-#define SC520_SWINT16_1 0x0d08 /* Software Interrupt 16-1 Control Register */
-#define SC520_SWINT22_17 0x0d0a /* Software Interrupt 22-17/NMI Control Register */
-#define SC520_INTPINPOL 0x0d10 /* Interrupt Pin Polarity Register */
-#define SC520_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mappin Register */
-#define SC520_ECCMAP 0x0d18 /* ECC Interrupt Mapping Register */
-#define SC520_GPTMR0MAP 0x0d1a /* GP Timer 0 Interrupt Mapping Register */
-#define SC520_GPTMR1MAP 0x0d1b /* GP Timer 1 Interrupt Mapping Register */
-#define SC520_GPTMR2MAP 0x0d1c /* GP Timer 2 Interrupt Mapping Register */
-#define SC520_PIT0MAP 0x0d20 /* PIT0 Interrupt Mapping Register */
-#define SC520_PIT1MAP 0x0d21 /* PIT1 Interrupt Mapping Register */
-#define SC520_PIT2MAP 0x0d22 /* PIT2 Interrupt Mapping Register */
-#define SC520_UART1MAP 0x0d28 /* UART 1 Interrupt Mapping Register */
-#define SC520_UART2MAP 0x0d29 /* UART 2 Interrupt Mapping Register */
-#define SC520_PCIINTAMAP 0x0d30 /* PCI Interrupt A Mapping Register */
-#define SC520_PCIINTBMAP 0x0d31 /* PCI Interrupt B Mapping Register */
-#define SC520_PCIINTCMAP 0x0d32 /* PCI Interrupt C Mapping Register */
-#define SC520_PCIINTDMAP 0x0d33 /* PCI Interrupt D Mapping Register */
-#define SC520_DMABCINTMAP 0x0d40 /* DMA Buffer Chaining Interrupt Mapping Register */
-#define SC520_SSIMAP 0x0d41 /* SSI Interrupt Mapping Register */
-#define SC520_WDTMAP 0x0d42 /* Watchdog Timer Interrupt Mapping Register */
-#define SC520_RTCMAP 0x0d43 /* RTC Interrupt Mapping Register */
-#define SC520_WPVMAP 0x0d44 /* Write-Protect Interrupt Mapping Register */
-#define SC520_ICEMAP 0x0d45 /* AMDebug JTAG RX/TX Interrupt Mapping Register */
-#define SC520_FERRMAP 0x0d46 /* Floating Point Error Interrupt Mapping Register */
-#define SC520_GP0IMAP 0x0d50 /* GPIRQ0 Interrupt Mapping Register */
-#define SC520_GP1IMAP 0x0d51 /* GPIRQ1 Interrupt Mapping Register */
-#define SC520_GP2IMAP 0x0d52 /* GPIRQ2 Interrupt Mapping Register */
-#define SC520_GP3IMAP 0x0d53 /* GPIRQ3 Interrupt Mapping Register */
-#define SC520_GP4IMAP 0x0d54 /* GPIRQ4 Interrupt Mapping Register */
-#define SC520_GP5IMAP 0x0d55 /* GPIRQ5 Interrupt Mapping Register */
-#define SC520_GP6IMAP 0x0d56 /* GPIRQ6 Interrupt Mapping Register */
-#define SC520_GP7IMAP 0x0d57 /* GPIRQ7 Interrupt Mapping Register */
-#define SC520_GP8IMAP 0x0d58 /* GPIRQ8 Interrupt Mapping Register */
-#define SC520_GP9IMAP 0x0d59 /* GPIRQ9 Interrupt Mapping Register */
-#define SC520_GP10IMAP 0x0d5a /* GPIRQ10 Interrupt Mapping Register */
-#define SC520_SYSINFO 0x0d70 /* System Board Information Register */
-#define SC520_RESCFG 0x0d72 /* Reset Configuration Register */
-#define SC520_RESSTA 0x0d74 /* Reset Status Register */
-#define SC520_GPDMAMMIO 0x0d81 /* GP-DMA Memory-Mapped I/O Register */
-#define SC520_GPDMAEXTCHMAPA 0x0d82 /* GP-DMA Resource Channel Map A */
-#define SC520_GPDMAEXTCHMAPB 0x0d84 /* GP-DMA Resource Channel Map B */
-#define SC520_GPDMAEXTPG0 0x0d86 /* GP-DMA Channel 0 Extended Page */
-#define SC520_GPDMAEXTPG1 0x0d87 /* GP-DMA Channel 1 Extended Page */
-#define SC520_GPDMAEXTPG2 0x0d88 /* GP-DMA Channel 2 Extended Page */
-#define SC520_GPDMAEXTPG3 0x0d89 /* GP-DMA Channel 3 Extended Page */
-#define SC520_GPDMAEXTPG5 0x0d8a /* GP-DMA Channel 5 Extended Page */
-#define SC520_GPDMAEXTPG6 0x0d8b /* GP-DMA Channel 6 Extended Page */
-#define SC520_GPDMAEXTPG7 0x0d8c /* GP-DMA Channel 7 Extended Page */
-#define SC520_GPDMAEXTTC3 0x0d90 /* GP-DMA Channel 3 Extender Transfer count */
-#define SC520_GPDMAEXTTC5 0x0d91 /* GP-DMA Channel 5 Extender Transfer count */
-#define SC520_GPDMAEXTTC6 0x0d92 /* GP-DMA Channel 6 Extender Transfer count */
-#define SC520_GPDMAEXTTC7 0x0d93 /* GP-DMA Channel 7 Extender Transfer count */
-#define SC520_GPDMABCCTL 0x0d98 /* Buffer Chaining Control */
-#define SC520_GPDMABCSTA 0x0d99 /* Buffer Chaining Status */
-#define SC520_GPDMABSINTENB 0x0d9a /* Buffer Chaining Interrupt Enable */
-#define SC520_GPDMABCVAL 0x0d9b /* Buffer Chaining Valid */
-#define SC520_GPDMANXTADDL3 0x0da0 /* GP-DMA Channel 3 Next Address Low */
-#define SC520_GPDMANXTADDH3 0x0da2 /* GP-DMA Channel 3 Next Address High */
-#define SC520_GPDMANXTADDL5 0x0da4 /* GP-DMA Channel 5 Next Address Low */
-#define SC520_GPDMANXTADDH5 0x0da6 /* GP-DMA Channel 5 Next Address High */
-#define SC520_GPDMANXTADDL6 0x0da8 /* GP-DMA Channel 6 Next Address Low */
-#define SC520_GPDMANXTADDH6 0x0daa /* GP-DMA Channel 6 Next Address High */
-#define SC520_GPDMANXTADDL7 0x0dac /* GP-DMA Channel 7 Next Address Low */
-#define SC520_GPDMANXTADDH7 0x0dae /* GP-DMA Channel 7 Next Address High */
-#define SC520_GPDMANXTTCL3 0x0db0 /* GP-DMA Channel 3 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH3 0x0db2 /* GP-DMA Channel 3 Next Transfer Count High */
-#define SC520_GPDMANXTTCL5 0x0db4 /* GP-DMA Channel 5 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH5 0x0db6 /* GP-DMA Channel 5 Next Transfer Count High */
-#define SC520_GPDMANXTTCL6 0x0db8 /* GP-DMA Channel 6 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH6 0x0dba /* GP-DMA Channel 6 Next Transfer Count High */
-#define SC520_GPDMANXTTCL7 0x0dbc /* GP-DMA Channel 7 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH7 0x0dbe /* GP-DMA Channel 7 Next Transfer Count High */
+#define SC520_REVID 0x0000 /* ElanSC520 Microcontroller Revision ID Register */
+#define SC520_CPUCTL 0x0002 /* Am5x86 CPU Control Register */
+#define SC520_DRCCTL 0x0010 /* SDRAM Control Register */
+#define SC520_DRCTMCTL 0x0012 /* SDRAM Timing Control Register */
+#define SC520_DRCCFG 0x0014 /* SDRAM Bank Configuration Register*/
+#define SC520_DRCBENDADR 0x0018 /* SDRAM Bank 0-3 Ending Address Register*/
+#define SC520_ECCCTL 0x0020 /* ECC Control Register */
+#define SC520_ECCSTA 0x0021 /* ECC Status Register */
+#define SC520_ECCCKBPOS 0x0022 /* ECC Check Bit Position Register */
+#define SC520_ECCSBADD 0x0024 /* ECC Single-Bit Error Address Register */
+#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */
+#define SC520_BOOTCSCTL 0x0050 /* /BOOTCS Control Register */
+#define SC520_ROMCS1CTL 0x0054 /* /ROMCS1 Control Register */
+#define SC520_ROMCS2CTL 0x0056 /* /ROMCS2 Control Register */
+#define SC520_HBCTL 0x0060 /* Host Bridge Control Register */
+#define SC520_HBTGTIRQCTL 0x0062 /* Host Bridge Target Interrupt Control Register */
+#define SC520_HBTGTIRQSTA 0x0064 /* Host Bridge Target Interrupt Status Register */
+#define SC520_HBMSTIRQCTL 0x0066 /* Host Bridge Target Interrupt Control Register */
+#define SC520_HBMSTIRQSTA 0x0068 /* Host Bridge Master Interrupt Status Register */
+#define SC520_MSTINTADD 0x006c /* Host Bridge Master Interrupt Address Register */
+#define SC520_SYSARBCTL 0x0070 /* System Arbiter Control Register */
+#define SC520_PCIARBSTA 0x0071 /* PCI Bus Arbiter Status Register */
+#define SC520_SYSARBMENB 0x0072 /* System Arbiter Master Enable Register */
+#define SC520_ARBPRICTL 0x0074 /* Arbiter Priority Control Register */
+#define SC520_ADDDECCTL 0x0080 /* Address Decode Control Register */
+#define SC520_WPVSTA 0x0082 /* Write-Protect Violation Status Register */
+#define SC520_PAR0 0x0088 /* Programmable Address Region 0 Register */
+#define SC520_PAR1 0x008c /* Programmable Address Region 1 Register */
+#define SC520_PAR2 0x0090 /* Programmable Address Region 2 Register */
+#define SC520_PAR3 0x0094 /* Programmable Address Region 3 Register */
+#define SC520_PAR4 0x0098 /* Programmable Address Region 4 Register */
+#define SC520_PAR5 0x009c /* Programmable Address Region 5 Register */
+#define SC520_PAR6 0x00a0 /* Programmable Address Region 6 Register */
+#define SC520_PAR7 0x00a4 /* Programmable Address Region 7 Register */
+#define SC520_PAR8 0x00a8 /* Programmable Address Region 8 Register */
+#define SC520_PAR9 0x00ac /* Programmable Address Region 9 Register */
+#define SC520_PAR10 0x00b0 /* Programmable Address Region 10 Register */
+#define SC520_PAR11 0x00b4 /* Programmable Address Region 11 Register */
+#define SC520_PAR12 0x00b8 /* Programmable Address Region 12 Register */
+#define SC520_PAR13 0x00bc /* Programmable Address Region 13 Register */
+#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */
+#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */
+#define SC520_GPECHO 0x0c00 /* GP Echo Mode Register */
+#define SC520_GPCSDW 0x0c01 /* GP Chip Select Data Width Register */
+#define SC520_GPCSQUAL 0x0c02 /* GP Chip Select Qualification Register */
+#define SC520_GPCSRT 0x0c08 /* GP Chip Select Recovery Time Register */
+#define SC520_GPCSPW 0x0c09 /* GP Chip Select Pulse Width Register */
+#define SC520_GPCSOFF 0x0c0a /* GP Chip Select Offset Register */
+#define SC520_GPRDW 0x0c0b /* GP Read Pulse Width Register */
+#define SC520_GPRDOFF 0x0c0c /* GP Read Offset Register */
+#define SC520_GPWRW 0x0c0d /* GP Write Pulse Width Register */
+#define SC520_GPWROFF 0x0c0e /* GP Write Offset Register */
+#define SC520_GPALEW 0x0c0f /* GP ALE Pulse Width Register */
+#define SC520_GPALEOFF 0x0c10 /* GP ALE Offset Register */
+#define SC520_PIOPFS15_0 0x0c20 /* PIO15-PIO0 Pin Function Select */
+#define SC520_PIOPFS31_16 0x0c22 /* PIO31-PIO16 Pin Function Select */
+#define SC520_CSPFS 0x0c24 /* Chip Select Pin Function Select */
+#define SC520_CLKSEL 0x0c26 /* Clock Select */
+#define SC520_DSCTL 0x0c28 /* Drive Strength Control */
+#define SC520_PIODIR15_0 0x0c2a /* PIO15-PIO0 Direction */
+#define SC520_PIODIR31_16 0x0c2c /* PIO31-PIO16 Direction */
+#define SC520_PIODATA15_0 0x0c30 /* PIO15-PIO0 Data */
+#define SC520_PIODATA31_16 0x0c32 /* PIO31-PIO16 Data */
+#define SC520_PIOSET15_0 0x0c34 /* PIO15-PIO0 Set */
+#define SC520_PIOSET31_16 0x0c36 /* PIO31-PIO16 Set */
+#define SC520_PIOCLR15_0 0x0c38 /* PIO15-PIO0 Clear */
+#define SC520_PIOCLR31_16 0x0c3a /* PIO31-PIO16 Clear */
+#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */
+#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */
+#define SC520_SWTMRCFG 0x0c64 /* Software Timer Configuration */
+#define SC520_GPTMRSTA 0x0c70 /* GP Timers Status Register */
+#define SC520_GPTMR0CTL 0x0c72 /* GP Timer 0 Mode/Control Register */
+#define SC520_GPTMR0CNT 0x0c74 /* GP Timer 0 Count Register */
+#define SC520_GPTMR0MAXCMPA 0x0c76 /* GP Timer 0 Maxcount Compare A Register */
+#define SC520_GPTMR0MAXCMPB 0x0c78 /* GP Timer 0 Maxcount Compare B Register */
+#define SC520_GPTMR1CTL 0x0c7a /* GP Timer 1 Mode/Control Register */
+#define SC520_GPTMR1CNT 0x0c7c /* GP Timer 1 Count Register */
+#define SC520_GPTMR1MAXCMPA 0x0c7e /* GP Timer 1 Maxcount Compare Register A */
+#define SC520_GPTMR1MAXCMPB 0x0c80 /* GP Timer 1 Maxcount Compare B Register */
+#define SC520_GPTMR2CTL 0x0c82 /* GP Timer 2 Mode/Control Register */
+#define SC520_GPTMR2CNT 0x0c84 /* GP Timer 2 Count Register */
+#define SC520_GPTMR2MAXCMPA 0x0c8e /* GP Timer 2 Maxcount Compare A Register */
+#define SC520_WDTMRCTL 0x0cb0 /* Watchdog Timer Control Register */
+#define SC520_WDTMRCNTL 0x0cb2 /* Watchdog Timer Count Low Register */
+#define SC520_WDTMRCNTH 0x0cb4 /* Watchdog Timer Count High Register */
+#define SC520_UART1CTL 0x0cc0 /* UART 1 General Control Register */
+#define SC520_UART1STA 0x0cc1 /* UART 1 General Status Register */
+#define SC520_UART1FCRSHAD 0x0cc2 /* UART 1 FIFO Control Shadow Register */
+#define SC520_UART2CTL 0x0cc4 /* UART 2 General Control Register */
+#define SC520_UART2STA 0x0cc5 /* UART 2 General Status Register */
+#define SC520_UART2FCRSHAD 0x0cc6 /* UART 2 FIFO Control Shadow Register */
+#define SC520_SSICTL 0x0cd0 /* SSI Control */
+#define SC520_SSIXMIT 0x0cd1 /* SSI Transmit */
+#define SC520_SSICMD 0x0cd2 /* SSI Command */
+#define SC520_SSISTA 0x0cd3 /* SSI Status */
+#define SC520_SSIRCV 0x0cd4 /* SSI Receive */
+#define SC520_PICICR 0x0d00 /* Interrupt Control Register */
+#define SC520_MPICMODE 0x0d02 /* Master PIC Interrupt Mode Register */
+#define SC520_SL1PICMODE 0x0d03 /* Slave 1 PIC Interrupt Mode Register */
+#define SC520_SL2PICMODE 0x0d04 /* Slave 2 PIC Interrupt Mode Register */
+#define SC520_SWINT16_1 0x0d08 /* Software Interrupt 16-1 Control Register */
+#define SC520_SWINT22_17 0x0d0a /* Software Interrupt 22-17/NMI Control Register */
+#define SC520_INTPINPOL 0x0d10 /* Interrupt Pin Polarity Register */
+#define SC520_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mappin Register */
+#define SC520_ECCMAP 0x0d18 /* ECC Interrupt Mapping Register */
+#define SC520_GPTMR0MAP 0x0d1a /* GP Timer 0 Interrupt Mapping Register */
+#define SC520_GPTMR1MAP 0x0d1b /* GP Timer 1 Interrupt Mapping Register */
+#define SC520_GPTMR2MAP 0x0d1c /* GP Timer 2 Interrupt Mapping Register */
+#define SC520_PIT0MAP 0x0d20 /* PIT0 Interrupt Mapping Register */
+#define SC520_PIT1MAP 0x0d21 /* PIT1 Interrupt Mapping Register */
+#define SC520_PIT2MAP 0x0d22 /* PIT2 Interrupt Mapping Register */
+#define SC520_UART1MAP 0x0d28 /* UART 1 Interrupt Mapping Register */
+#define SC520_UART2MAP 0x0d29 /* UART 2 Interrupt Mapping Register */
+#define SC520_PCIINTAMAP 0x0d30 /* PCI Interrupt A Mapping Register */
+#define SC520_PCIINTBMAP 0x0d31 /* PCI Interrupt B Mapping Register */
+#define SC520_PCIINTCMAP 0x0d32 /* PCI Interrupt C Mapping Register */
+#define SC520_PCIINTDMAP 0x0d33 /* PCI Interrupt D Mapping Register */
+#define SC520_DMABCINTMAP 0x0d40 /* DMA Buffer Chaining Interrupt Mapping Register */
+#define SC520_SSIMAP 0x0d41 /* SSI Interrupt Mapping Register */
+#define SC520_WDTMAP 0x0d42 /* Watchdog Timer Interrupt Mapping Register */
+#define SC520_RTCMAP 0x0d43 /* RTC Interrupt Mapping Register */
+#define SC520_WPVMAP 0x0d44 /* Write-Protect Interrupt Mapping Register */
+#define SC520_ICEMAP 0x0d45 /* AMDebug JTAG RX/TX Interrupt Mapping Register */
+#define SC520_FERRMAP 0x0d46 /* Floating Point Error Interrupt Mapping Register */
+#define SC520_GP0IMAP 0x0d50 /* GPIRQ0 Interrupt Mapping Register */
+#define SC520_GP1IMAP 0x0d51 /* GPIRQ1 Interrupt Mapping Register */
+#define SC520_GP2IMAP 0x0d52 /* GPIRQ2 Interrupt Mapping Register */
+#define SC520_GP3IMAP 0x0d53 /* GPIRQ3 Interrupt Mapping Register */
+#define SC520_GP4IMAP 0x0d54 /* GPIRQ4 Interrupt Mapping Register */
+#define SC520_GP5IMAP 0x0d55 /* GPIRQ5 Interrupt Mapping Register */
+#define SC520_GP6IMAP 0x0d56 /* GPIRQ6 Interrupt Mapping Register */
+#define SC520_GP7IMAP 0x0d57 /* GPIRQ7 Interrupt Mapping Register */
+#define SC520_GP8IMAP 0x0d58 /* GPIRQ8 Interrupt Mapping Register */
+#define SC520_GP9IMAP 0x0d59 /* GPIRQ9 Interrupt Mapping Register */
+#define SC520_GP10IMAP 0x0d5a /* GPIRQ10 Interrupt Mapping Register */
+#define SC520_SYSINFO 0x0d70 /* System Board Information Register */
+#define SC520_RESCFG 0x0d72 /* Reset Configuration Register */
+#define SC520_RESSTA 0x0d74 /* Reset Status Register */
+#define SC520_GPDMAMMIO 0x0d81 /* GP-DMA Memory-Mapped I/O Register */
+#define SC520_GPDMAEXTCHMAPA 0x0d82 /* GP-DMA Resource Channel Map A */
+#define SC520_GPDMAEXTCHMAPB 0x0d84 /* GP-DMA Resource Channel Map B */
+#define SC520_GPDMAEXTPG0 0x0d86 /* GP-DMA Channel 0 Extended Page */
+#define SC520_GPDMAEXTPG1 0x0d87 /* GP-DMA Channel 1 Extended Page */
+#define SC520_GPDMAEXTPG2 0x0d88 /* GP-DMA Channel 2 Extended Page */
+#define SC520_GPDMAEXTPG3 0x0d89 /* GP-DMA Channel 3 Extended Page */
+#define SC520_GPDMAEXTPG5 0x0d8a /* GP-DMA Channel 5 Extended Page */
+#define SC520_GPDMAEXTPG6 0x0d8b /* GP-DMA Channel 6 Extended Page */
+#define SC520_GPDMAEXTPG7 0x0d8c /* GP-DMA Channel 7 Extended Page */
+#define SC520_GPDMAEXTTC3 0x0d90 /* GP-DMA Channel 3 Extender Transfer count */
+#define SC520_GPDMAEXTTC5 0x0d91 /* GP-DMA Channel 5 Extender Transfer count */
+#define SC520_GPDMAEXTTC6 0x0d92 /* GP-DMA Channel 6 Extender Transfer count */
+#define SC520_GPDMAEXTTC7 0x0d93 /* GP-DMA Channel 7 Extender Transfer count */
+#define SC520_GPDMABCCTL 0x0d98 /* Buffer Chaining Control */
+#define SC520_GPDMABCSTA 0x0d99 /* Buffer Chaining Status */
+#define SC520_GPDMABSINTENB 0x0d9a /* Buffer Chaining Interrupt Enable */
+#define SC520_GPDMABCVAL 0x0d9b /* Buffer Chaining Valid */
+#define SC520_GPDMANXTADDL3 0x0da0 /* GP-DMA Channel 3 Next Address Low */
+#define SC520_GPDMANXTADDH3 0x0da2 /* GP-DMA Channel 3 Next Address High */
+#define SC520_GPDMANXTADDL5 0x0da4 /* GP-DMA Channel 5 Next Address Low */
+#define SC520_GPDMANXTADDH5 0x0da6 /* GP-DMA Channel 5 Next Address High */
+#define SC520_GPDMANXTADDL6 0x0da8 /* GP-DMA Channel 6 Next Address Low */
+#define SC520_GPDMANXTADDH6 0x0daa /* GP-DMA Channel 6 Next Address High */
+#define SC520_GPDMANXTADDL7 0x0dac /* GP-DMA Channel 7 Next Address Low */
+#define SC520_GPDMANXTADDH7 0x0dae /* GP-DMA Channel 7 Next Address High */
+#define SC520_GPDMANXTTCL3 0x0db0 /* GP-DMA Channel 3 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH3 0x0db2 /* GP-DMA Channel 3 Next Transfer Count High */
+#define SC520_GPDMANXTTCL5 0x0db4 /* GP-DMA Channel 5 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH5 0x0db6 /* GP-DMA Channel 5 Next Transfer Count High */
+#define SC520_GPDMANXTTCL6 0x0db8 /* GP-DMA Channel 6 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH6 0x0dba /* GP-DMA Channel 6 Next Transfer Count High */
+#define SC520_GPDMANXTTCL7 0x0dbc /* GP-DMA Channel 7 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH7 0x0dbe /* GP-DMA Channel 7 Next Transfer Count High */
/* MMCR Register bits (not all of them :) ) */
/* SSI Stuff */
-#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */
-#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */
-#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */
-#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */
-#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */
-#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */
-#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */
-#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */
+#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */
+#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */
+#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */
+#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */
+#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */
+#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */
+#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */
+#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */
-#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */
-#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */
-#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */
-#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */
+#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */
+#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */
+#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */
+#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */
-#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */
-#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */
-#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */
-#define SSISTA_BSY 0x02 /* SSI Busy */
-#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */
+#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */
+#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */
+#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */
+#define SSISTA_BSY 0x02 /* SSI Busy */
+#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */
/* BITS for SC520_ADDDECCTL: */
-#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */
-#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */
-#define RTC_DIS 0x04 /* RTC Disable */
-#define UART2_DIS 0x02 /* UART2 Disable */
-#define UART1_DIS 0x01 /* UART1 Disable */
+#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */
+#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */
+#define RTC_DIS 0x04 /* RTC Disable */
+#define UART2_DIS 0x02 /* UART2 Disable */
+#define UART1_DIS 0x01 /* UART1 Disable */
/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */
#define SC520_REG_ADDR 0x00000cf8
@@ -256,7 +256,7 @@
/* PCI bus memory from 0x10000000 to 0x26ffffff
* (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
#define SC520_PCI_MEM_PHYS 0x10000000
-#define SC520_PCI_MEM_BUS 0x10000000
+#define SC520_PCI_MEM_BUS 0x10000000
#define SC520_PCI_MEM_SIZE 0x17000000
/* 0x28000000 - 0x3fffffff is used by the flash banks */
diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h
index c897f2b..7377d31 100644
--- a/include/asm-m68k/global_data.h
+++ b/include/asm-m68k/global_data.h
@@ -73,6 +73,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#if 0
extern gd_t *global_data;
diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h
index 5ed3cbc..facf0c9 100644
--- a/include/asm-m68k/m5249.h
+++ b/include/asm-m68k/m5249.h
@@ -58,7 +58,7 @@
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
-#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
+#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h
index 7473bb9..f6a6b04 100644
--- a/include/asm-m68k/m5282.h
+++ b/include/asm-m68k/m5282.h
@@ -382,15 +382,15 @@
#define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A))
/* Bit level definitions and macros */
-#define MCFCCM_CCR_LOAD (0x8000)
-#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8)
-#define MCFCCM_CCR_SZEN (0x0040)
-#define MCFCCM_CCR_PSTEN (0x0020)
-#define MCFCCM_CCR_BME (0x0008)
-#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
+#define MCFCCM_CCR_LOAD (0x8000)
+#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8)
+#define MCFCCM_CCR_SZEN (0x0040)
+#define MCFCCM_CCR_PSTEN (0x0020)
+#define MCFCCM_CCR_BME (0x0008)
+#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
-#define MCFCCM_CIR_PIN_MASK (0xFF00)
-#define MCFCCM_CIR_PRN_MASK (0x00FF)
+#define MCFCCM_CIR_PIN_MASK (0xFF00)
+#define MCFCCM_CIR_PRN_MASK (0x00FF)
/* Clock Module */
@@ -554,7 +554,7 @@
#define MCFGPT_GPTIE_C1I (0x02)
#define MCFGPT_GPTIE_C0I (0x01)
-#define MCFGPT_GPTSCR2_TOI (0x80)
+#define MCFGPT_GPTSCR2_TOI (0x80)
#define MCFGPT_GPTSCR2_PUPT (0x20)
#define MCFGPT_GPTSCR2_RDPT (0x10)
#define MCFGPT_GPTSCR2_TCRE (0x08)
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
index f10f89c..deb23e0 100644
--- a/include/asm-microblaze/asm.h
+++ b/include/asm-microblaze/asm.h
@@ -74,7 +74,7 @@
{ \
register unsigned tmp; \
__asm__ __volatile__ (" \
- mfs %0, rmsr; \
+ mfs %0, rmsr; \
ori %0, %0, "#val"; \
mts rmsr, %0; \
nop;" \
@@ -87,7 +87,7 @@
{ \
register unsigned tmp; \
__asm__ __volatile__ (" \
- mfs %0, rmsr; \
+ mfs %0, rmsr; \
andi %0, %0, ~"#val"; \
mts rmsr, %0; \
nop;" \
diff --git a/include/asm-microblaze/global_data.h b/include/asm-microblaze/global_data.h
index 91243b2..376786f 100644
--- a/include/asm-microblaze/global_data.h
+++ b/include/asm-microblaze/global_data.h
@@ -53,6 +53,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31")
diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h
index a4e9947..6a33197 100644
--- a/include/asm-mips/au1x00.h
+++ b/include/asm-mips/au1x00.h
@@ -5,7 +5,7 @@
*
* Copyright 2000,2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
+ * ppopov@mvista.com or source@mvista.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
index 256ad2c..70bcad7 100644
--- a/include/asm-mips/cacheops.h
+++ b/include/asm-mips/cacheops.h
@@ -21,7 +21,7 @@
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I 0x00
+#define Hit_Invalidate_I 0x00
#else
#define Hit_Invalidate_I 0x10
#endif
diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h
new file mode 100644
index 0000000..1665a63
--- /dev/null
+++ b/include/asm-mips/errno.h
@@ -0,0 +1,143 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle
+ */
+#ifndef _ASM_MIPS_ERRNO_H
+#define _ASM_MIPS_ERRNO_H
+
+/*
+ * These first 34 error codes are from Linux 2.6, <asm-generic/errno-base.h>
+ */
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Argument list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+
+/*
+ * These error numbers are intended to be MIPS ABI compatible
+ */
+#define ENOMSG 35 /* No message of desired type */
+#define EIDRM 36 /* Identifier removed */
+#define ECHRNG 37 /* Channel number out of range */
+#define EL2NSYNC 38 /* Level 2 not synchronized */
+#define EL3HLT 39 /* Level 3 halted */
+#define EL3RST 40 /* Level 3 reset */
+#define ELNRNG 41 /* Link number out of range */
+#define EUNATCH 42 /* Protocol driver not attached */
+#define ENOCSI 43 /* No CSI structure available */
+#define EL2HLT 44 /* Level 2 halted */
+#define EDEADLK 45 /* Resource deadlock would occur */
+#define ENOLCK 46 /* No record locks available */
+#define EBADE 50 /* Invalid exchange */
+#define EBADR 51 /* Invalid request descriptor */
+#define EXFULL 52 /* Exchange full */
+#define ENOANO 53 /* No anode */
+#define EBADRQC 54 /* Invalid request code */
+#define EBADSLT 55 /* Invalid slot */
+#define EDEADLOCK 56 /* File locking deadlock error */
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EDOTDOT 73 /* RFS specific error */
+#define EMULTIHOP 74 /* Multihop attempted */
+#define EBADMSG 77 /* Not a data message */
+#define ENAMETOOLONG 78 /* File name too long */
+#define EOVERFLOW 79 /* Value too large for defined data type */
+#define ENOTUNIQ 80 /* Name not unique on network */
+#define EBADFD 81 /* File descriptor in bad state */
+#define EREMCHG 82 /* Remote address changed */
+#define ELIBACC 83 /* Can not access a needed shared library */
+#define ELIBBAD 84 /* Accessing a corrupted shared library */
+#define ELIBSCN 85 /* .lib section in a.out corrupted */
+#define ELIBMAX 86 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 87 /* Cannot exec a shared library directly */
+#define EILSEQ 88 /* Illegal byte sequence */
+#define ENOSYS 89 /* Function not implemented */
+#define ELOOP 90 /* Too many symbolic links encountered */
+#define ERESTART 91 /* Interrupted system call should be restarted */
+#define ESTRPIPE 92 /* Streams pipe error */
+#define ENOTEMPTY 93 /* Directory not empty */
+#define EUSERS 94 /* Too many users */
+#define ENOTSOCK 95 /* Socket operation on non-socket */
+#define EDESTADDRREQ 96 /* Destination address required */
+#define EMSGSIZE 97 /* Message too long */
+#define EPROTOTYPE 98 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 99 /* Protocol not available */
+#define EPROTONOSUPPORT 120 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 121 /* Socket type not supported */
+#define EOPNOTSUPP 122 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 123 /* Protocol family not supported */
+#define EAFNOSUPPORT 124 /* Address family not supported by protocol */
+#define EADDRINUSE 125 /* Address already in use */
+#define EADDRNOTAVAIL 126 /* Cannot assign requested address */
+#define ENETDOWN 127 /* Network is down */
+#define ENETUNREACH 128 /* Network is unreachable */
+#define ENETRESET 129 /* Network dropped connection because of reset */
+#define ECONNABORTED 130 /* Software caused connection abort */
+#define ECONNRESET 131 /* Connection reset by peer */
+#define ENOBUFS 132 /* No buffer space available */
+#define EISCONN 133 /* Transport endpoint is already connected */
+#define ENOTCONN 134 /* Transport endpoint is not connected */
+#define EUCLEAN 135 /* Structure needs cleaning */
+#define ENOTNAM 137 /* Not a XENIX named type file */
+#define ENAVAIL 138 /* No XENIX semaphores available */
+#define EISNAM 139 /* Is a named type file */
+#define EREMOTEIO 140 /* Remote I/O error */
+#define EINIT 141 /* Reserved */
+#define EREMDEV 142 /* Error 142 */
+#define ESHUTDOWN 143 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 144 /* Too many references: cannot splice */
+#define ETIMEDOUT 145 /* Connection timed out */
+#define ECONNREFUSED 146 /* Connection refused */
+#define EHOSTDOWN 147 /* Host is down */
+#define EHOSTUNREACH 148 /* No route to host */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define EALREADY 149 /* Operation already in progress */
+#define EINPROGRESS 150 /* Operation now in progress */
+#define ESTALE 151 /* Stale NFS file handle */
+#define ECANCELED 158 /* AIO operation canceled */
+
+#endif /* _ASM_MIPS_ERRNO_H */
diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h
index bd9e4dd..0c0ba50 100644
--- a/include/asm-mips/global_data.h
+++ b/include/asm-mips/global_data.h
@@ -55,6 +55,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0")
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 0586c53..be7e5c6 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -7,8 +7,8 @@
* Copyright (C) 2000 Silicon Graphics, Inc.
* Modified for further R[236]000 support by Paul M. Antoine, 1996.
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
- * Copyright (C) 2003 Maciej W. Rozycki
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
+ * Copyright (C) 2003, 2004 Maciej W. Rozycki
*/
#ifndef _ASM_MIPSREGS_H
#define _ASM_MIPSREGS_H
@@ -29,6 +29,15 @@
#endif
/*
+ * Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ULCAST_
+#else
+#define _ULCAST_ (unsigned long)
+#endif
+
+/*
* Coprocessor 0 register names
*/
#define CP0_INDEX $0
@@ -55,12 +64,15 @@
#define CP0_XCONTEXT $20
#define CP0_FRAMEMASK $21
#define CP0_DIAGNOSTIC $22
+#define CP0_DEBUG $23
+#define CP0_DEPC $24
#define CP0_PERFORMANCE $25
#define CP0_ECC $26
#define CP0_CACHEERR $27
#define CP0_TAGLO $28
#define CP0_TAGHI $29
#define CP0_ERROREPC $30
+#define CP0_DESAVE $31
/*
* R4640/R4650 cp0 register names. These registers are listed
@@ -82,11 +94,27 @@
#define CP0_S1_DERRADDR0 $26
#define CP0_S1_DERRADDR1 $27
#define CP0_S1_INTCONTROL $20
+
+/*
+ * Coprocessor 0 Set 2 register names
+ */
+#define CP0_S2_SRSCTL $12 /* MIPSR2 */
+
+/*
+ * Coprocessor 0 Set 3 register names
+ */
+#define CP0_S3_SRSMAP $12 /* MIPSR2 */
+
+/*
+ * TX39 Series
+ */
+#define CP0_TX39_CACHE $7
+
/*
* Coprocessor 1 (FPU) register names
*/
-#define CP1_REVISION $0
-#define CP1_STATUS $31
+#define CP1_REVISION $0
+#define CP1_STATUS $31
/*
* FPU Status Register Values
@@ -95,230 +123,113 @@
* Status Register Values
*/
-#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
-#define FPU_CSR_COND 0x00800000 /* $fcc0 */
-#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
-#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
-#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
-#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
-#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
-#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
-#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
-#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
+#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
+#define FPU_CSR_COND 0x00800000 /* $fcc0 */
+#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
+#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
+#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
+#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
+#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
+#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
+#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
+#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
/*
* X the exception cause indicator
* E the exception enable
* S the sticky/flag bit
-*/
-#define FPU_CSR_ALL_X 0x0003f000
-#define FPU_CSR_UNI_X 0x00020000
-#define FPU_CSR_INV_X 0x00010000
-#define FPU_CSR_DIV_X 0x00008000
-#define FPU_CSR_OVF_X 0x00004000
-#define FPU_CSR_UDF_X 0x00002000
-#define FPU_CSR_INE_X 0x00001000
-
-#define FPU_CSR_ALL_E 0x00000f80
-#define FPU_CSR_INV_E 0x00000800
-#define FPU_CSR_DIV_E 0x00000400
-#define FPU_CSR_OVF_E 0x00000200
-#define FPU_CSR_UDF_E 0x00000100
-#define FPU_CSR_INE_E 0x00000080
-
-#define FPU_CSR_ALL_S 0x0000007c
-#define FPU_CSR_INV_S 0x00000040
-#define FPU_CSR_DIV_S 0x00000020
-#define FPU_CSR_OVF_S 0x00000010
-#define FPU_CSR_UDF_S 0x00000008
-#define FPU_CSR_INE_S 0x00000004
+ */
+#define FPU_CSR_ALL_X 0x0003f000
+#define FPU_CSR_UNI_X 0x00020000
+#define FPU_CSR_INV_X 0x00010000
+#define FPU_CSR_DIV_X 0x00008000
+#define FPU_CSR_OVF_X 0x00004000
+#define FPU_CSR_UDF_X 0x00002000
+#define FPU_CSR_INE_X 0x00001000
-/* rounding mode */
-#define FPU_CSR_RN 0x0 /* nearest */
-#define FPU_CSR_RZ 0x1 /* towards zero */
-#define FPU_CSR_RU 0x2 /* towards +Infinity */
-#define FPU_CSR_RD 0x3 /* towards -Infinity */
+#define FPU_CSR_ALL_E 0x00000f80
+#define FPU_CSR_INV_E 0x00000800
+#define FPU_CSR_DIV_E 0x00000400
+#define FPU_CSR_OVF_E 0x00000200
+#define FPU_CSR_UDF_E 0x00000100
+#define FPU_CSR_INE_E 0x00000080
+#define FPU_CSR_ALL_S 0x0000007c
+#define FPU_CSR_INV_S 0x00000040
+#define FPU_CSR_DIV_S 0x00000020
+#define FPU_CSR_OVF_S 0x00000010
+#define FPU_CSR_UDF_S 0x00000008
+#define FPU_CSR_INE_S 0x00000004
+
+/* rounding mode */
+#define FPU_CSR_RN 0x0 /* nearest */
+#define FPU_CSR_RZ 0x1 /* towards zero */
+#define FPU_CSR_RU 0x2 /* towards +Infinity */
+#define FPU_CSR_RD 0x3 /* towards -Infinity */
/*
* Values for PageMask register
*/
-#include <linux/config.h>
#ifdef CONFIG_CPU_VR41XX
-#define PM_1K 0x00000000
-#define PM_4K 0x00001800
-#define PM_16K 0x00007800
-#define PM_64K 0x0001f800
-#define PM_256K 0x0007f800
-#else
-#define PM_4K 0x00000000
-#define PM_16K 0x00006000
-#define PM_64K 0x0001e000
-#define PM_256K 0x0007e000
-#define PM_1M 0x001fe000
-#define PM_4M 0x007fe000
-#define PM_16M 0x01ffe000
-#endif
-/*
- * Values used for computation of new tlb entries
- */
-#define PL_4K 12
-#define PL_16K 14
-#define PL_64K 16
-#define PL_256K 18
-#define PL_1M 20
-#define PL_4M 22
-#define PL_16M 24
+/* Why doesn't stupidity hurt ... */
-/*
- * Macros to access the system control coprocessor
- */
-#define read_32bit_cp0_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- "mfc0\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
+#define PM_1K 0x00000000
+#define PM_4K 0x00001800
+#define PM_16K 0x00007800
+#define PM_64K 0x0001f800
+#define PM_256K 0x0007f800
-#define read_32bit_cp0_set1_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- "cfc0\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
+#else
-/*
- * For now use this only with interrupts disabled!
- */
-#define read_64bit_cp0_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmfc0\t%0,"STR(source)"\n\t" \
- ".set\tmips0" \
- : "=r" (__res)); \
- __res;})
+#define PM_4K 0x00000000
+#define PM_16K 0x00006000
+#define PM_64K 0x0001e000
+#define PM_256K 0x0007e000
+#define PM_1M 0x001fe000
+#define PM_4M 0x007fe000
+#define PM_16M 0x01ffe000
+#define PM_64M 0x07ffe000
+#define PM_256M 0x1fffe000
-#define write_32bit_cp0_register(register,value) \
- __asm__ __volatile__( \
- "mtc0\t%0,"STR(register)"\n\t" \
- "nop" \
- : : "r" (value));
-
-#define write_32bit_cp0_set1_register(register,value) \
- __asm__ __volatile__( \
- "ctc0\t%0,"STR(register)"\n\t" \
- "nop" \
- : : "r" (value));
-
-#define write_64bit_cp0_register(register,value) \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmtc0\t%0,"STR(register)"\n\t" \
- ".set\tmips0" \
- : : "r" (value))
-
-/*
- * This should be changed when we get a compiler that support the MIPS32 ISA.
- */
-#define read_mips32_cp0_config1() \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n\t" \
- ".word\t0x40018001\n\t" \
- "move\t%0,$1\n\t" \
- ".set\tat\n\t" \
- ".set\treorder" \
- :"=r" (__res)); \
- __res;})
+#endif
-#define tlb_write_indexed() \
- __asm__ __volatile__( \
- ".set noreorder\n\t" \
- "tlbwi\n\t" \
-".set reorder")
+/*
+ * Values used for computation of new tlb entries
+ */
+#define PL_4K 12
+#define PL_16K 14
+#define PL_64K 16
+#define PL_256K 18
+#define PL_1M 20
+#define PL_4M 22
+#define PL_16M 24
+#define PL_64M 26
+#define PL_256M 28
/*
* R4x00 interrupt enable / cause bits
*/
-#define IE_SW0 (1<< 8)
-#define IE_SW1 (1<< 9)
-#define IE_IRQ0 (1<<10)
-#define IE_IRQ1 (1<<11)
-#define IE_IRQ2 (1<<12)
-#define IE_IRQ3 (1<<13)
-#define IE_IRQ4 (1<<14)
-#define IE_IRQ5 (1<<15)
+#define IE_SW0 (_ULCAST_(1) << 8)
+#define IE_SW1 (_ULCAST_(1) << 9)
+#define IE_IRQ0 (_ULCAST_(1) << 10)
+#define IE_IRQ1 (_ULCAST_(1) << 11)
+#define IE_IRQ2 (_ULCAST_(1) << 12)
+#define IE_IRQ3 (_ULCAST_(1) << 13)
+#define IE_IRQ4 (_ULCAST_(1) << 14)
+#define IE_IRQ5 (_ULCAST_(1) << 15)
/*
* R4x00 interrupt cause bits
*/
-#define C_SW0 (1<< 8)
-#define C_SW1 (1<< 9)
-#define C_IRQ0 (1<<10)
-#define C_IRQ1 (1<<11)
-#define C_IRQ2 (1<<12)
-#define C_IRQ3 (1<<13)
-#define C_IRQ4 (1<<14)
-#define C_IRQ5 (1<<15)
-
-#ifndef _LANGUAGE_ASSEMBLY
-/*
- * Manipulate the status register.
- * Mostly used to access the interrupt bits.
- */
-#define __BUILD_SET_CP0(name,register) \
-extern __inline__ unsigned int \
-set_cp0_##name(unsigned int set) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res |= set; \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-} \
- \
-extern __inline__ unsigned int \
-clear_cp0_##name(unsigned int clear) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res &= ~clear; \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-} \
- \
-extern __inline__ unsigned int \
-change_cp0_##name(unsigned int change, unsigned int new) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res &= ~change; \
- res |= (new & change); \
- if(change) \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-}
-
-__BUILD_SET_CP0(status,CP0_STATUS)
-__BUILD_SET_CP0(cause,CP0_CAUSE)
-__BUILD_SET_CP0(config,CP0_CONFIG)
-
-#endif /* defined (_LANGUAGE_ASSEMBLY) */
+#define C_SW0 (_ULCAST_(1) << 8)
+#define C_SW1 (_ULCAST_(1) << 9)
+#define C_IRQ0 (_ULCAST_(1) << 10)
+#define C_IRQ1 (_ULCAST_(1) << 11)
+#define C_IRQ2 (_ULCAST_(1) << 12)
+#define C_IRQ3 (_ULCAST_(1) << 13)
+#define C_IRQ4 (_ULCAST_(1) << 14)
+#define C_IRQ5 (_ULCAST_(1) << 15)
/*
* Bitfields in the R4xx0 cp0 status register
@@ -332,14 +243,21 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
# define KSU_KERNEL 0x00000000
#define ST0_UX 0x00000020
#define ST0_SX 0x00000040
-#define ST0_KX 0x00000080
+#define ST0_KX 0x00000080
#define ST0_DE 0x00010000
#define ST0_CE 0x00020000
/*
+ * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
+ * cacheops in userspace. This bit exists only on RM7000 and RM9000
+ * processors.
+ */
+#define ST0_CO 0x08000000
+
+/*
* Bitfields in the R[23]000 cp0 status register.
*/
-#define ST0_IEC 0x00000001
+#define ST0_IEC 0x00000001
#define ST0_KUC 0x00000002
#define ST0_IEP 0x00000004
#define ST0_KUP 0x00000008
@@ -353,31 +271,36 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
/*
* Bits specific to the R4640/R4650
*/
-#define ST0_UM (1 << 4)
-#define ST0_IL (1 << 23)
-#define ST0_DL (1 << 24)
+#define ST0_UM (_ULCAST_(1) << 4)
+#define ST0_IL (_ULCAST_(1) << 23)
+#define ST0_DL (_ULCAST_(1) << 24)
+
+/*
+ * Enable the MIPS MDMX and DSP ASEs
+ */
+#define ST0_MX 0x01000000
/*
* Bitfields in the TX39 family CP0 Configuration Register 3
*/
#define TX39_CONF_ICS_SHIFT 19
#define TX39_CONF_ICS_MASK 0x00380000
-#define TX39_CONF_ICS_1KB 0x00000000
-#define TX39_CONF_ICS_2KB 0x00080000
-#define TX39_CONF_ICS_4KB 0x00100000
-#define TX39_CONF_ICS_8KB 0x00180000
-#define TX39_CONF_ICS_16KB 0x00200000
+#define TX39_CONF_ICS_1KB 0x00000000
+#define TX39_CONF_ICS_2KB 0x00080000
+#define TX39_CONF_ICS_4KB 0x00100000
+#define TX39_CONF_ICS_8KB 0x00180000
+#define TX39_CONF_ICS_16KB 0x00200000
#define TX39_CONF_DCS_SHIFT 16
#define TX39_CONF_DCS_MASK 0x00070000
-#define TX39_CONF_DCS_1KB 0x00000000
-#define TX39_CONF_DCS_2KB 0x00010000
-#define TX39_CONF_DCS_4KB 0x00020000
-#define TX39_CONF_DCS_8KB 0x00030000
-#define TX39_CONF_DCS_16KB 0x00040000
-
-#define TX39_CONF_CWFON 0x00004000
-#define TX39_CONF_WBON 0x00002000
+#define TX39_CONF_DCS_1KB 0x00000000
+#define TX39_CONF_DCS_2KB 0x00010000
+#define TX39_CONF_DCS_4KB 0x00020000
+#define TX39_CONF_DCS_8KB 0x00030000
+#define TX39_CONF_DCS_16KB 0x00040000
+
+#define TX39_CONF_CWFON 0x00004000
+#define TX39_CONF_WBON 0x00002000
#define TX39_CONF_RF_SHIFT 10
#define TX39_CONF_RF_MASK 0x00000c00
#define TX39_CONF_DOZE 0x00000200
@@ -395,39 +318,40 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
*/
#define ST0_IM 0x0000ff00
#define STATUSB_IP0 8
-#define STATUSF_IP0 (1 << 8)
+#define STATUSF_IP0 (_ULCAST_(1) << 8)
#define STATUSB_IP1 9
-#define STATUSF_IP1 (1 << 9)
+#define STATUSF_IP1 (_ULCAST_(1) << 9)
#define STATUSB_IP2 10
-#define STATUSF_IP2 (1 << 10)
+#define STATUSF_IP2 (_ULCAST_(1) << 10)
#define STATUSB_IP3 11
-#define STATUSF_IP3 (1 << 11)
+#define STATUSF_IP3 (_ULCAST_(1) << 11)
#define STATUSB_IP4 12
-#define STATUSF_IP4 (1 << 12)
+#define STATUSF_IP4 (_ULCAST_(1) << 12)
#define STATUSB_IP5 13
-#define STATUSF_IP5 (1 << 13)
+#define STATUSF_IP5 (_ULCAST_(1) << 13)
#define STATUSB_IP6 14
-#define STATUSF_IP6 (1 << 14)
+#define STATUSF_IP6 (_ULCAST_(1) << 14)
#define STATUSB_IP7 15
-#define STATUSF_IP7 (1 << 15)
+#define STATUSF_IP7 (_ULCAST_(1) << 15)
#define STATUSB_IP8 0
-#define STATUSF_IP8 (1 << 0)
+#define STATUSF_IP8 (_ULCAST_(1) << 0)
#define STATUSB_IP9 1
-#define STATUSF_IP9 (1 << 1)
+#define STATUSF_IP9 (_ULCAST_(1) << 1)
#define STATUSB_IP10 2
-#define STATUSF_IP10 (1 << 2)
+#define STATUSF_IP10 (_ULCAST_(1) << 2)
#define STATUSB_IP11 3
-#define STATUSF_IP11 (1 << 3)
+#define STATUSF_IP11 (_ULCAST_(1) << 3)
#define STATUSB_IP12 4
-#define STATUSF_IP12 (1 << 4)
+#define STATUSF_IP12 (_ULCAST_(1) << 4)
#define STATUSB_IP13 5
-#define STATUSF_IP13 (1 << 5)
+#define STATUSF_IP13 (_ULCAST_(1) << 5)
#define STATUSB_IP14 6
-#define STATUSF_IP14 (1 << 6)
+#define STATUSF_IP14 (_ULCAST_(1) << 6)
#define STATUSB_IP15 7
-#define STATUSF_IP15 (1 << 7)
+#define STATUSF_IP15 (_ULCAST_(1) << 7)
#define ST0_CH 0x00040000
#define ST0_SR 0x00100000
+#define ST0_TS 0x00200000
#define ST0_BEV 0x00400000
#define ST0_RE 0x02000000
#define ST0_FR 0x04000000
@@ -444,35 +368,36 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
*/
#define CAUSEB_EXCCODE 2
-#define CAUSEF_EXCCODE (31 << 2)
+#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
#define CAUSEB_IP 8
-#define CAUSEF_IP (255 << 8)
+#define CAUSEF_IP (_ULCAST_(255) << 8)
#define CAUSEB_IP0 8
-#define CAUSEF_IP0 (1 << 8)
+#define CAUSEF_IP0 (_ULCAST_(1) << 8)
#define CAUSEB_IP1 9
-#define CAUSEF_IP1 (1 << 9)
+#define CAUSEF_IP1 (_ULCAST_(1) << 9)
#define CAUSEB_IP2 10
-#define CAUSEF_IP2 (1 << 10)
+#define CAUSEF_IP2 (_ULCAST_(1) << 10)
#define CAUSEB_IP3 11
-#define CAUSEF_IP3 (1 << 11)
+#define CAUSEF_IP3 (_ULCAST_(1) << 11)
#define CAUSEB_IP4 12
-#define CAUSEF_IP4 (1 << 12)
+#define CAUSEF_IP4 (_ULCAST_(1) << 12)
#define CAUSEB_IP5 13
-#define CAUSEF_IP5 (1 << 13)
+#define CAUSEF_IP5 (_ULCAST_(1) << 13)
#define CAUSEB_IP6 14
-#define CAUSEF_IP6 (1 << 14)
+#define CAUSEF_IP6 (_ULCAST_(1) << 14)
#define CAUSEB_IP7 15
-#define CAUSEF_IP7 (1 << 15)
+#define CAUSEF_IP7 (_ULCAST_(1) << 15)
#define CAUSEB_IV 23
-#define CAUSEF_IV (1 << 23)
+#define CAUSEF_IV (_ULCAST_(1) << 23)
#define CAUSEB_CE 28
-#define CAUSEF_CE (3 << 28)
+#define CAUSEF_CE (_ULCAST_(3) << 28)
#define CAUSEB_BD 31
-#define CAUSEF_BD (1 << 31)
+#define CAUSEF_BD (_ULCAST_(1) << 31)
/*
- * Bits in the coprozessor 0 config register.
+ * Bits in the coprocessor 0 config register.
*/
+/* Generic bits. */
#define CONF_CM_CACHABLE_NO_WA 0
#define CONF_CM_CACHABLE_WA 1
#define CONF_CM_UNCACHED 2
@@ -482,66 +407,958 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
#define CONF_CM_CACHABLE_CUW 6
#define CONF_CM_CACHABLE_ACCELERATED 7
#define CONF_CM_CMASK 7
-#define CONF_DB (1 << 4)
-#define CONF_IB (1 << 5)
-#define CONF_SC (1 << 17)
-#define CONF_AC (1 << 23)
-#define CONF_HALT (1 << 25)
+#define CONF_BE (_ULCAST_(1) << 15)
+
+/* Bits common to various processors. */
+#define CONF_CU (_ULCAST_(1) << 3)
+#define CONF_DB (_ULCAST_(1) << 4)
+#define CONF_IB (_ULCAST_(1) << 5)
+#define CONF_DC (_ULCAST_(7) << 6)
+#define CONF_IC (_ULCAST_(7) << 9)
+#define CONF_EB (_ULCAST_(1) << 13)
+#define CONF_EM (_ULCAST_(1) << 14)
+#define CONF_SM (_ULCAST_(1) << 16)
+#define CONF_SC (_ULCAST_(1) << 17)
+#define CONF_EW (_ULCAST_(3) << 18)
+#define CONF_EP (_ULCAST_(15)<< 24)
+#define CONF_EC (_ULCAST_(7) << 28)
+#define CONF_CM (_ULCAST_(1) << 31)
+
+/* Bits specific to the R4xx0. */
+#define R4K_CONF_SW (_ULCAST_(1) << 20)
+#define R4K_CONF_SS (_ULCAST_(1) << 21)
+#define R4K_CONF_SB (_ULCAST_(3) << 22)
+
+/* Bits specific to the R5000. */
+#define R5K_CONF_SE (_ULCAST_(1) << 12)
+#define R5K_CONF_SS (_ULCAST_(3) << 20)
+
+/* Bits specific to the RM7000. */
+#define RM7K_CONF_SE (_ULCAST_(1) << 3)
+#define RM7K_CONF_TE (_ULCAST_(1) << 12)
+#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
+#define RM7K_CONF_TC (_ULCAST_(1) << 17)
+#define RM7K_CONF_SI (_ULCAST_(3) << 20)
+#define RM7K_CONF_SC (_ULCAST_(1) << 31)
+
+/* Bits specific to the R10000. */
+#define R10K_CONF_DN (_ULCAST_(3) << 3)
+#define R10K_CONF_CT (_ULCAST_(1) << 5)
+#define R10K_CONF_PE (_ULCAST_(1) << 6)
+#define R10K_CONF_PM (_ULCAST_(3) << 7)
+#define R10K_CONF_EC (_ULCAST_(15)<< 9)
+#define R10K_CONF_SB (_ULCAST_(1) << 13)
+#define R10K_CONF_SK (_ULCAST_(1) << 14)
+#define R10K_CONF_SS (_ULCAST_(7) << 16)
+#define R10K_CONF_SC (_ULCAST_(7) << 19)
+#define R10K_CONF_DC (_ULCAST_(7) << 26)
+#define R10K_CONF_IC (_ULCAST_(7) << 29)
+
+/* Bits specific to the VR41xx. */
+#define VR41_CONF_CS (_ULCAST_(1) << 12)
+#define VR41_CONF_P4K (_ULCAST_(1) << 13)
+#define VR41_CONF_BP (_ULCAST_(1) << 16)
+#define VR41_CONF_M16 (_ULCAST_(1) << 20)
+#define VR41_CONF_AD (_ULCAST_(1) << 23)
+
+/* Bits specific to the R30xx. */
+#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
+#define R30XX_CONF_REV (_ULCAST_(1) << 22)
+#define R30XX_CONF_AC (_ULCAST_(1) << 23)
+#define R30XX_CONF_RF (_ULCAST_(1) << 24)
+#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
+#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
+#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
+#define R30XX_CONF_SB (_ULCAST_(1) << 30)
+#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
+
+/* Bits specific to the TX49. */
+#define TX49_CONF_DC (_ULCAST_(1) << 16)
+#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
+#define TX49_CONF_HALT (_ULCAST_(1) << 18)
+#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
+
+/* Bits specific to the MIPS32/64 PRA. */
+#define MIPS_CONF_MT (_ULCAST_(7) << 7)
+#define MIPS_CONF_AR (_ULCAST_(7) << 10)
+#define MIPS_CONF_AT (_ULCAST_(3) << 13)
+#define MIPS_CONF_M (_ULCAST_(1) << 31)
+
+/*
+ * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
+ */
+#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
+#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
+#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
+#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
+#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
+#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
+#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
+#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
+#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
+#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
+
+#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
+#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
+#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
+#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
+#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
+#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
+#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
+#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
+
+#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
+#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
+#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
+#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
+#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
+#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
+#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
+#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
+#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
+
+#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
+
+#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
+ */
+#define MIPS_FPIR_S (_ULCAST_(1) << 16)
+#define MIPS_FPIR_D (_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
+#define MIPS_FPIR_W (_ULCAST_(1) << 20)
+#define MIPS_FPIR_L (_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Functions to access the R10000 performance counters. These are basically
+ * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
+ * performance counter number encoded into bits 1 ... 5 of the instruction.
+ * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
+ * disassembler these will look like an access to sel 0 or 1.
+ */
+#define read_r10k_perf_cntr(counter) \
+({ \
+ unsigned int __res; \
+ __asm__ __volatile__( \
+ "mfpc\t%0, %1" \
+ : "=r" (__res) \
+ : "i" (counter)); \
+ \
+ __res; \
+})
+
+#define write_r10k_perf_cntr(counter,val) \
+do { \
+ __asm__ __volatile__( \
+ "mtpc\t%0, %1" \
+ : \
+ : "r" (val), "i" (counter)); \
+} while (0)
+
+#define read_r10k_perf_event(counter) \
+({ \
+ unsigned int __res; \
+ __asm__ __volatile__( \
+ "mfps\t%0, %1" \
+ : "=r" (__res) \
+ : "i" (counter)); \
+ \
+ __res; \
+})
+
+#define write_r10k_perf_cntl(counter,val) \
+do { \
+ __asm__ __volatile__( \
+ "mtps\t%0, %1" \
+ : \
+ : "r" (val), "i" (counter)); \
+} while (0)
/*
- * R10000 performance counter definitions.
+ * Macros to access the system control coprocessor
+ */
+
+#define __read_32bit_c0_register(source, sel) \
+({ int __res; \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ "mfc0\t%0, " #source "\n\t" \
+ : "=r" (__res)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips32\n\t" \
+ "mfc0\t%0, " #source ", " #sel "\n\t" \
+ ".set\tmips0\n\t" \
+ : "=r" (__res)); \
+ __res; \
+})
+
+#define __read_64bit_c0_register(source, sel) \
+({ unsigned long long __res; \
+ if (sizeof(unsigned long) == 4) \
+ __res = __read_64bit_c0_split(source, sel); \
+ else if (sel == 0) \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmfc0\t%0, " #source "\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dmfc0\t%0, " #source ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ __res; \
+})
+
+#define __write_32bit_c0_register(register, sel, value) \
+do { \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ "mtc0\t%z0, " #register "\n\t" \
+ : : "Jr" ((unsigned int)(value))); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips32\n\t" \
+ "mtc0\t%z0, " #register ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : : "Jr" ((unsigned int)(value))); \
+} while (0)
+
+#define __write_64bit_c0_register(register, sel, value) \
+do { \
+ if (sizeof(unsigned long) == 4) \
+ __write_64bit_c0_split(register, sel, value); \
+ else if (sel == 0) \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmtc0\t%z0, " #register "\n\t" \
+ ".set\tmips0" \
+ : : "Jr" (value)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dmtc0\t%z0, " #register ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : : "Jr" (value)); \
+} while (0)
+
+#define __read_ulong_c0_register(reg, sel) \
+ ((sizeof(unsigned long) == 4) ? \
+ (unsigned long) __read_32bit_c0_register(reg, sel) : \
+ (unsigned long) __read_64bit_c0_register(reg, sel))
+
+#define __write_ulong_c0_register(reg, sel, val) \
+do { \
+ if (sizeof(unsigned long) == 4) \
+ __write_32bit_c0_register(reg, sel, val); \
+ else \
+ __write_64bit_c0_register(reg, sel, val); \
+} while (0)
+
+/*
+ * On RM7000/RM9000 these are uses to access cop0 set 1 registers
+ */
+#define __read_32bit_c0_ctrl_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ "cfc0\t%0, " #source "\n\t" \
+ : "=r" (__res)); \
+ __res; \
+})
+
+#define __write_32bit_c0_ctrl_register(register, value) \
+do { \
+ __asm__ __volatile__( \
+ "ctc0\t%z0, " #register "\n\t" \
+ : : "Jr" ((unsigned int)(value))); \
+} while (0)
+
+/*
+ * These versions are only needed for systems with more than 38 bits of
+ * physical address space running the 32-bit kernel. That's none atm :-)
+ */
+#define __read_64bit_c0_split(source, sel) \
+({ \
+ unsigned long long __val; \
+ unsigned long __flags; \
+ \
+ local_irq_save(__flags); \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dmfc0\t%M0, " #source "\n\t" \
+ "dsll\t%L0, %M0, 32\n\t" \
+ "dsrl\t%M0, %M0, 32\n\t" \
+ "dsrl\t%L0, %L0, 32\n\t" \
+ ".set\tmips0" \
+ : "=r" (__val)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dmfc0\t%M0, " #source ", " #sel "\n\t" \
+ "dsll\t%L0, %M0, 32\n\t" \
+ "dsrl\t%M0, %M0, 32\n\t" \
+ "dsrl\t%L0, %L0, 32\n\t" \
+ ".set\tmips0" \
+ : "=r" (__val)); \
+ local_irq_restore(__flags); \
+ \
+ __val; \
+})
+
+#define __write_64bit_c0_split(source, sel, val) \
+do { \
+ unsigned long __flags; \
+ \
+ local_irq_save(__flags); \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dsll\t%L0, %L0, 32\n\t" \
+ "dsrl\t%L0, %L0, 32\n\t" \
+ "dsll\t%M0, %M0, 32\n\t" \
+ "or\t%L0, %L0, %M0\n\t" \
+ "dmtc0\t%L0, " #source "\n\t" \
+ ".set\tmips0" \
+ : : "r" (val)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "dsll\t%L0, %L0, 32\n\t" \
+ "dsrl\t%L0, %L0, 32\n\t" \
+ "dsll\t%M0, %M0, 32\n\t" \
+ "or\t%L0, %L0, %M0\n\t" \
+ "dmtc0\t%L0, " #source ", " #sel "\n\t" \
+ ".set\tmips0" \
+ : : "r" (val)); \
+ local_irq_restore(__flags); \
+} while (0)
+
+#define read_c0_index() __read_32bit_c0_register($0, 0)
+#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
+
+#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
+#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
+
+#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
+#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
+
+#define read_c0_conf() __read_32bit_c0_register($3, 0)
+#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
+
+#define read_c0_context() __read_ulong_c0_register($4, 0)
+#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
+
+#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
+#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
+
+#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
+
+#define read_c0_wired() __read_32bit_c0_register($6, 0)
+#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
+
+#define read_c0_info() __read_32bit_c0_register($7, 0)
+
+#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
+#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
+
+#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
+#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
+
+#define read_c0_count() __read_32bit_c0_register($9, 0)
+#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
+
+#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
+#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
+
+#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
+#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
+
+#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
+#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
+
+#define read_c0_compare() __read_32bit_c0_register($11, 0)
+#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
+
+#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
+#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
+
+#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
+#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
+
+#define read_c0_status() __read_32bit_c0_register($12, 0)
+#ifdef CONFIG_MIPS_MT_SMTC
+#define write_c0_status(val) \
+do { \
+ __write_32bit_c0_register($12, 0, val); \
+ __ehb(); \
+} while (0)
+#else
+/*
+ * Legacy non-SMTC code, which may be hazardous
+ * but which might not support EHB
+ */
+#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
+#endif /* CONFIG_MIPS_MT_SMTC */
+
+#define read_c0_cause() __read_32bit_c0_register($13, 0)
+#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
+
+#define read_c0_epc() __read_ulong_c0_register($14, 0)
+#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
+
+#define read_c0_prid() __read_32bit_c0_register($15, 0)
+
+#define read_c0_config() __read_32bit_c0_register($16, 0)
+#define read_c0_config1() __read_32bit_c0_register($16, 1)
+#define read_c0_config2() __read_32bit_c0_register($16, 2)
+#define read_c0_config3() __read_32bit_c0_register($16, 3)
+#define read_c0_config4() __read_32bit_c0_register($16, 4)
+#define read_c0_config5() __read_32bit_c0_register($16, 5)
+#define read_c0_config6() __read_32bit_c0_register($16, 6)
+#define read_c0_config7() __read_32bit_c0_register($16, 7)
+#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
+#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
+#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
+#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
+#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
+#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
+#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
+#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
+
+/*
+ * The WatchLo register. There may be upto 8 of them.
+ */
+#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
+#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
+#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
+#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
+#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
+#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
+#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
+#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
+#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
+#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
+#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
+#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
+#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
+#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
+#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
+#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
+
+/*
+ * The WatchHi register. There may be upto 8 of them.
+ */
+#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
+#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
+#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
+#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
+#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
+#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
+#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
+#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
+
+#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
+#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
+#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
+#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
+#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
+#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
+#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
+#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
+
+#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
+#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
+
+#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
+#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
+
+#define read_c0_framemask() __read_32bit_c0_register($21, 0)
+#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
+
+/* RM9000 PerfControl performance counter control register */
+#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
+#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_diag() __read_32bit_c0_register($22, 0)
+#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_diag1() __read_32bit_c0_register($22, 1)
+#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_diag2() __read_32bit_c0_register($22, 2)
+#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_diag3() __read_32bit_c0_register($22, 3)
+#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_diag4() __read_32bit_c0_register($22, 4)
+#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_diag5() __read_32bit_c0_register($22, 5)
+#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
+
+#define read_c0_debug() __read_32bit_c0_register($23, 0)
+#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
+
+#define read_c0_depc() __read_ulong_c0_register($24, 0)
+#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
+
+/*
+ * MIPS32 / MIPS64 performance counters
+ */
+#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
+#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
+#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
+#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
+#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
+#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
+#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
+#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
+#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
+#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
+#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
+#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
+#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
+#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
+#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
+#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
+
+/* RM9000 PerfCount performance counter register */
+#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
+#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
+
+#define read_c0_ecc() __read_32bit_c0_register($26, 0)
+#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
+
+#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
+#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
+
+#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
+
+#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
+#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
+
+#define read_c0_taglo() __read_32bit_c0_register($28, 0)
+#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
+
+#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
+#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
+
+#define read_c0_taghi() __read_32bit_c0_register($29, 0)
+#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
+
+#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
+#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
+
+/* MIPSR2 */
+#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
+#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
+
+#define read_c0_intctl() __read_32bit_c0_register($12, 1)
+#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
+
+#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
+#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
+
+#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
+#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
+
+#define read_c0_ebase() __read_32bit_c0_register($15, 1)
+#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
+
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define read_32bit_cp1_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ "cfc1\t%0,"STR(source)"\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
+#define rddsp(mask) \
+({ \
+ unsigned int __res; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " # rddsp $1, %x1 \n" \
+ " .word 0x7c000cb8 | (%x1 << 16) \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__res) \
+ : "i" (mask)); \
+ __res; \
+})
+
+#define wrdsp(val, mask) \
+do { \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " move $1, %0 \n" \
+ " # wrdsp $1, %x1 \n" \
+ " .word 0x7c2004f8 | (%x1 << 11) \n" \
+ " .set pop \n" \
+ : \
+ : "r" (val), "i" (mask)); \
+} while (0)
+
+#define mfhi0() \
+({ \
+ unsigned long __treg; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " # mfhi %0, $ac0 \n" \
+ " .word 0x00000810 \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__treg)); \
+ __treg; \
+})
+
+#define mfhi1() \
+({ \
+ unsigned long __treg; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " # mfhi %0, $ac1 \n" \
+ " .word 0x00200810 \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__treg)); \
+ __treg; \
+})
+
+#define mfhi2() \
+({ \
+ unsigned long __treg; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " # mfhi %0, $ac2 \n" \
+ " .word 0x00400810 \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__treg)); \
+ __treg; \
+})
+
+#define mfhi3() \
+({ \
+ unsigned long __treg; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " # mfhi %0, $ac3 \n" \
+ " .word 0x00600810 \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__treg)); \
+ __treg; \
+})
+
+#define mflo0() \
+({ \
+ unsigned long __treg; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " # mflo %0, $ac0 \n" \
+ " .word 0x00000812 \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__treg)); \
+ __treg; \
+})
+
+#define mflo1() \
+({ \
+ unsigned long __treg; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " # mflo %0, $ac1 \n" \
+ " .word 0x00200812 \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__treg)); \
+ __treg; \
+})
+
+#define mflo2() \
+({ \
+ unsigned long __treg; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " # mflo %0, $ac2 \n" \
+ " .word 0x00400812 \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__treg)); \
+ __treg; \
+})
+
+#define mflo3() \
+({ \
+ unsigned long __treg; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " # mflo %0, $ac3 \n" \
+ " .word 0x00600812 \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__treg)); \
+ __treg; \
+})
+
+#define mthi0(x) \
+do { \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " move $1, %0 \n" \
+ " # mthi $1, $ac0 \n" \
+ " .word 0x00200011 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+} while (0)
+
+#define mthi1(x) \
+do { \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " move $1, %0 \n" \
+ " # mthi $1, $ac1 \n" \
+ " .word 0x00200811 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+} while (0)
+
+#define mthi2(x) \
+do { \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " move $1, %0 \n" \
+ " # mthi $1, $ac2 \n" \
+ " .word 0x00201011 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+} while (0)
+
+#define mthi3(x) \
+do { \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " move $1, %0 \n" \
+ " # mthi $1, $ac3 \n" \
+ " .word 0x00201811 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+} while (0)
+
+#define mtlo0(x) \
+do { \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " move $1, %0 \n" \
+ " # mtlo $1, $ac0 \n" \
+ " .word 0x00200013 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+} while (0)
+
+#define mtlo1(x) \
+do { \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " move $1, %0 \n" \
+ " # mtlo $1, $ac1 \n" \
+ " .word 0x00200813 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+} while (0)
+
+#define mtlo2(x) \
+do { \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " move $1, %0 \n" \
+ " # mtlo $1, $ac2 \n" \
+ " .word 0x00201013 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+} while (0)
+
+#define mtlo3(x) \
+do { \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " move $1, %0 \n" \
+ " # mtlo $1, $ac3 \n" \
+ " .word 0x00201813 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+} while (0)
+
+/*
+ * TLB operations.
*
- * FIXME: The R10000 performance counter opens a nice way to implement CPU
- * time accounting with a precission of one cycle. I don't have
- * R10000 silicon but just a manual, so ...
- */
-
-/*
- * Events counted by counter #0
- */
-#define CE0_CYCLES 0
-#define CE0_INSN_ISSUED 1
-#define CE0_LPSC_ISSUED 2
-#define CE0_S_ISSUED 3
-#define CE0_SC_ISSUED 4
-#define CE0_SC_FAILED 5
-#define CE0_BRANCH_DECODED 6
-#define CE0_QW_WB_SECONDARY 7
-#define CE0_CORRECTED_ECC_ERRORS 8
-#define CE0_ICACHE_MISSES 9
-#define CE0_SCACHE_I_MISSES 10
-#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
-#define CE0_EXT_INTERVENTIONS_REQ 12
-#define CE0_EXT_INVALIDATE_REQ 13
-#define CE0_VIRTUAL_COHERENCY_COND 14
-#define CE0_INSN_GRADUATED 15
-
-/*
- * Events counted by counter #1
- */
-#define CE1_CYCLES 0
-#define CE1_INSN_GRADUATED 1
-#define CE1_LPSC_GRADUATED 2
-#define CE1_S_GRADUATED 3
-#define CE1_SC_GRADUATED 4
-#define CE1_FP_INSN_GRADUATED 5
-#define CE1_QW_WB_PRIMARY 6
-#define CE1_TLB_REFILL 7
-#define CE1_BRANCH_MISSPREDICTED 8
-#define CE1_DCACHE_MISS 9
-#define CE1_SCACHE_D_MISSES 10
-#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
-#define CE1_EXT_INTERVENTION_HITS 12
-#define CE1_EXT_INVALIDATE_REQ 13
-#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
-#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
-
-/*
- * These flags define in which priviledge mode the counters count events
- */
-#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
-#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
-#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
-#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
+ * It is responsibility of the caller to take care of any TLB hazards.
+ */
+static inline void tlb_probe(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbp\n\t"
+ ".set reorder");
+}
+
+static inline void tlb_read(void)
+{
+#if MIPS34K_MISSED_ITLB_WAR
+ int res = 0;
+
+ __asm__ __volatile__(
+ " .set push \n"
+ " .set noreorder \n"
+ " .set noat \n"
+ " .set mips32r2 \n"
+ " .word 0x41610001 # dvpe $1 \n"
+ " move %0, $1 \n"
+ " ehb \n"
+ " .set pop \n"
+ : "=r" (res));
+
+ instruction_hazard();
+#endif
+
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbr\n\t"
+ ".set reorder");
+
+#if MIPS34K_MISSED_ITLB_WAR
+ if ((res & _ULCAST_(1)))
+ __asm__ __volatile__(
+ " .set push \n"
+ " .set noreorder \n"
+ " .set noat \n"
+ " .set mips32r2 \n"
+ " .word 0x41600021 # evpe \n"
+ " ehb \n"
+ " .set pop \n");
+#endif
+}
+
+static inline void tlb_write_indexed(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbwi\n\t"
+ ".set reorder");
+}
+
+static inline void tlb_write_random(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbwr\n\t"
+ ".set reorder");
+}
+
+/*
+ * Manipulate bits in a c0 register.
+ */
+#define __BUILD_SET_C0(name) \
+static inline unsigned int \
+set_c0_##name(unsigned int set) \
+{ \
+ unsigned int res; \
+ \
+ res = read_c0_##name(); \
+ res |= set; \
+ write_c0_##name(res); \
+ \
+ return res; \
+} \
+ \
+static inline unsigned int \
+clear_c0_##name(unsigned int clear) \
+{ \
+ unsigned int res; \
+ \
+ res = read_c0_##name(); \
+ res &= ~clear; \
+ write_c0_##name(res); \
+ \
+ return res; \
+} \
+ \
+static inline unsigned int \
+change_c0_##name(unsigned int change, unsigned int new) \
+{ \
+ unsigned int res; \
+ \
+ res = read_c0_##name(); \
+ res &= ~change; \
+ res |= (new & change); \
+ write_c0_##name(res); \
+ \
+ return res; \
+}
+
+__BUILD_SET_C0(status)
+__BUILD_SET_C0(cause)
+__BUILD_SET_C0(config)
+__BUILD_SET_C0(intcontrol)
+__BUILD_SET_C0(intctl)
+__BUILD_SET_C0(srsmap)
+
+#endif /* !__ASSEMBLY__ */
#endif /* _ASM_MIPSREGS_H */
diff --git a/include/asm-nios/global_data.h b/include/asm-nios/global_data.h
index ddd66cf..a8cc987 100644
--- a/include/asm-nios/global_data.h
+++ b/include/asm-nios/global_data.h
@@ -46,6 +46,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("%g7")
diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h
index 12a0bd9..8b78806 100644
--- a/include/asm-nios/io.h
+++ b/include/asm-nios/io.h
@@ -34,21 +34,21 @@
#define readb(addr)\
({unsigned char val;\
asm volatile( " pfxio 0 \n"\
- " ld %0, [%1] \n"\
+ " ld %0, [%1] \n"\
" ext8d %0, %1 \n"\
:"=r"(val) : "r" (addr)); val;})
#define readw(addr)\
({unsigned short val;\
asm volatile( " pfxio 0 \n"\
- " ld %0, [%1] \n"\
+ " ld %0, [%1] \n"\
" ext16d %0, %1 \n"\
:"=r"(val) : "r" (addr)); val;})
#define readl(addr)\
({unsigned long val;\
asm volatile( " pfxio 0 \n"\
- " ld %0, [%1] \n"\
+ " ld %0, [%1] \n"\
:"=r"(val) : "r" (addr)); val;})
#define writeb(addr,val)\
diff --git a/include/asm-nios2/global_data.h b/include/asm-nios2/global_data.h
index ae5f617..7290489 100644
--- a/include/asm-nios2/global_data.h
+++ b/include/asm-nios2/global_data.h
@@ -45,6 +45,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r15")
diff --git a/include/asm-ppc/4xx_pci.h b/include/asm-ppc/4xx_pci.h
index 3c1adec..30125a1 100644
--- a/include/asm-ppc/4xx_pci.h
+++ b/include/asm-ppc/4xx_pci.h
@@ -47,6 +47,6 @@
#define PTM2MS 0xEF400038
#define PTM2LA 0xEF40003C
-#define PCIDEVID_405GP 0x0
+#define PCIDEVID_405GP 0x0
#endif
diff --git a/include/asm-ppc/5xx_immap.h b/include/asm-ppc/5xx_immap.h
index 8e57057..72cbab4 100644
--- a/include/asm-ppc/5xx_immap.h
+++ b/include/asm-ppc/5xx_immap.h
@@ -408,31 +408,31 @@ typedef struct uimb {
/* Internal Memory Map MPC555
*/
typedef struct immap {
- char res1[262144]; /* CMF Flash A 256 Kbytes */
- char res2[196608]; /* CMF Flash B 192 Kbytes */
- char res3[2670592]; /* Reserved for Flash */
- sysconf5xx_t im_siu_conf; /* SIU Configuration */
+ char res1[262144]; /* CMF Flash A 256 Kbytes */
+ char res2[196608]; /* CMF Flash B 192 Kbytes */
+ char res3[2670592]; /* Reserved for Flash */
+ sysconf5xx_t im_siu_conf; /* SIU Configuration */
memctl5xx_t im_memctl; /* Memory Controller */
sit5xx_t im_sit; /* System Integration Timers */
car5xx_t im_clkrst; /* Clocks and Reset */
- sitk5xx_t im_sitk; /* System Integration Timer Keys*/
- cark8xx_t im_clkrstk; /* Clocks and Resert Keys */
+ sitk5xx_t im_sitk; /* System Integration Timer Keys*/
+ cark8xx_t im_clkrstk; /* Clocks and Resert Keys */
fl5xx_t im_fla; /* Flash Module A */
fl5xx_t im_flb; /* Flash Module B */
- char res4[14208]; /* Reserved for SIU */
- dprc5xx_t im_dprc; /* Dpram Control Register */
- char res5[8180]; /* Reserved */
- char dptram[6144]; /* Dptram */
- char res6[2048]; /* Reserved */
+ char res4[14208]; /* Reserved for SIU */
+ dprc5xx_t im_dprc; /* Dpram Control Register */
+ char res5[8180]; /* Reserved */
+ char dptram[6144]; /* Dptram */
+ char res6[2048]; /* Reserved */
tpu5xx_t im_tpua; /* Time Proessing Unit A */
- tpu5xx_t im_tpub; /* Time Processing Unit B */
- qadc5xx_t im_qadca; /* QADC A */
- qadc5xx_t im_qadcb; /* QADC B */
+ tpu5xx_t im_tpub; /* Time Processing Unit B */
+ qadc5xx_t im_qadca; /* QADC A */
+ qadc5xx_t im_qadcb; /* QADC B */
qsmcm5xx_t im_qsmcm; /* SCI and SPI */
- mios5xx_t im_mios; /* MIOS */
- tcan5xx_t im_tcana; /* Toucan A */
- tcan5xx_t im_tcanb; /* Toucan B */
- char res7[1792]; /* Reserved */
+ mios5xx_t im_mios; /* MIOS */
+ tcan5xx_t im_tcana; /* Toucan A */
+ tcan5xx_t im_tcanb; /* Toucan B */
+ char res7[1792]; /* Reserved */
uimb5xx_t im_uimb; /* UIMB */
} immap_t;
diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h
index 3264915..4e9c608 100644
--- a/include/asm-ppc/bitops.h
+++ b/include/asm-ppc/bitops.h
@@ -287,7 +287,7 @@ extern __inline__ int ext2_test_bit(int nr, __const__ void * addr)
#define ext2_find_first_zero_bit(addr, size) \
ext2_find_next_zero_bit((addr), (size), 0)
-extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
+static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
unsigned long size, unsigned long offset)
{
unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
index de82399..05db0de 100644
--- a/include/asm-ppc/e300.h
+++ b/include/asm-ppc/e300.h
@@ -16,59 +16,59 @@
*/
/* #define HID0 1008 already defined in processor.h */
-#define HID0_MASK_MACHINE_CHECK 0x00000000
-#define HID0_ENABLE_MACHINE_CHECK 0x80000000
+#define HID0_MASK_MACHINE_CHECK 0x00000000
+#define HID0_ENABLE_MACHINE_CHECK 0x80000000
-#define HID0_DISABLE_CACHE_PARITY 0x00000000
-#define HID0_ENABLE_CACHE_PARITY 0x40000000
+#define HID0_DISABLE_CACHE_PARITY 0x00000000
+#define HID0_ENABLE_CACHE_PARITY 0x40000000
-#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */
-#define HID0_ENABLE_ADDRESS_PARITY 0x20000000
+#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_ADDRESS_PARITY 0x20000000
-#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */
-#define HID0_ENABLE_DATE_PARITY 0x10000000
+#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_DATE_PARITY 0x10000000
-#define HID0_CORE_CLK_OUT 0x00000000
-#define HID0_CORE_CLK_OUT_DIV_2 0x08000000
+#define HID0_CORE_CLK_OUT 0x00000000
+#define HID0_CORE_CLK_OUT_DIV_2 0x08000000
#define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */
#define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000
-#define HID0_DISABLE_DOSE_MODE 0x00000000
-#define HID0_ENABLE_DOSE_MODE 0x00800000
+#define HID0_DISABLE_DOSE_MODE 0x00000000
+#define HID0_ENABLE_DOSE_MODE 0x00800000
-#define HID0_DISABLE_NAP_MODE 0x00000000
-#define HID0_ENABLE_NAP_MODE 0x00400000
+#define HID0_DISABLE_NAP_MODE 0x00000000
+#define HID0_ENABLE_NAP_MODE 0x00400000
-#define HID0_DISABLE_SLEEP_MODE 0x00000000
-#define HID0_ENABLE_SLEEP_MODE 0x00200000
+#define HID0_DISABLE_SLEEP_MODE 0x00000000
+#define HID0_ENABLE_SLEEP_MODE 0x00200000
#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000
-#define HID0_SOFT_RESET 0x00010000
+#define HID0_SOFT_RESET 0x00010000
-#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000
-#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000
+#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000
+#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000
-#define HID0_DISABLE_DATA_CACHE 0x00000000
-#define HID0_ENABLE_DATA_CACHE 0x00004000
+#define HID0_DISABLE_DATA_CACHE 0x00000000
+#define HID0_ENABLE_DATA_CACHE 0x00004000
-#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000
+#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000
-#define HID0_LOCK_DATA_CACHE 0x00001000
+#define HID0_LOCK_DATA_CACHE 0x00001000
#define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800
-#define HID0_INVALIDATE_DATA_CACHE 0x00000400
+#define HID0_INVALIDATE_DATA_CACHE 0x00000400
-#define HID0_DISABLE_M_BIT 0x00000000
-#define HID0_ENABLE_M_BIT 0x00000080
+#define HID0_DISABLE_M_BIT 0x00000000
+#define HID0_ENABLE_M_BIT 0x00000080
-#define HID0_FBIOB 0x00000010
+#define HID0_FBIOB 0x00000010
-#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000
-#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008
+#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000
+#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008
#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000
#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
@@ -90,37 +90,37 @@
/* BAT (block address translation */
-#define BATU_BEPI_MSK 0xfffe0000
-#define BATU_BL_MSK 0x00001ffc
-
-#define BATU_BL_128K 0x00000000
-#define BATU_BL_256K 0x00000004
-#define BATU_BL_512K 0x0000000c
-#define BATU_BL_1M 0x0000001c
-#define BATU_BL_2M 0x0000003c
-#define BATU_BL_4M 0x0000007c
-#define BATU_BL_8M 0x000000fc
-#define BATU_BL_16M 0x000001fc
-#define BATU_BL_32M 0x000003fc
-#define BATU_BL_64M 0x000007fc
-#define BATU_BL_128M 0x00000ffc
-#define BATU_BL_256M 0x00001ffc
-
-#define BATU_VS 0x00000002
-#define BATU_VP 0x00000001
-
-#define BATL_BRPN_MSK 0xfffe0000
-#define BATL_WIMG_MSK 0x00000078
-
-#define BATL_WRITETHROUGH 0x00000040
-#define BATL_CACHEINHIBIT 0x00000020
-#define BATL_MEMCOHERENCE 0x00000010
-#define BATL_GUARDEDSTORAGE 0x00000008
-
-#define BATL_PP_MSK 0x00000003
-#define BATL_PP_00 0x00000000 /* No access */
-#define BATL_PP_01 0x00000001 /* Read-only */
-#define BATL_PP_10 0x00000002 /* Read-write */
-#define BATL_PP_11 0x00000003
+#define BATU_BEPI_MSK 0xfffe0000
+#define BATU_BL_MSK 0x00001ffc
+
+#define BATU_BL_128K 0x00000000
+#define BATU_BL_256K 0x00000004
+#define BATU_BL_512K 0x0000000c
+#define BATU_BL_1M 0x0000001c
+#define BATU_BL_2M 0x0000003c
+#define BATU_BL_4M 0x0000007c
+#define BATU_BL_8M 0x000000fc
+#define BATU_BL_16M 0x000001fc
+#define BATU_BL_32M 0x000003fc
+#define BATU_BL_64M 0x000007fc
+#define BATU_BL_128M 0x00000ffc
+#define BATU_BL_256M 0x00001ffc
+
+#define BATU_VS 0x00000002
+#define BATU_VP 0x00000001
+
+#define BATL_BRPN_MSK 0xfffe0000
+#define BATL_WIMG_MSK 0x00000078
+
+#define BATL_WRITETHROUGH 0x00000040
+#define BATL_CACHEINHIBIT 0x00000020
+#define BATL_MEMCOHERENCE 0x00000010
+#define BATL_GUARDEDSTORAGE 0x00000008
+
+#define BATL_PP_MSK 0x00000003
+#define BATL_PP_00 0x00000000 /* No access */
+#define BATL_PP_01 0x00000001 /* Read-only */
+#define BATL_PP_10 0x00000002 /* Read-write */
+#define BATL_PP_11 0x00000003
#endif /* __E300_H__ */
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 202c844..ea70266 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -168,6 +168,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 2d07625..113ba48 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1054,7 +1054,7 @@ typedef struct ccsr_cpm {
* 0x9000-0x90bff: General SIU
*/
typedef struct ccsr_cpm_siu {
- char res1[80];
+ char res1[80];
uint smaer;
uint smser;
uint smevr;
@@ -1143,9 +1143,9 @@ typedef struct ccsr_cpm_timer {
/* 0x91018-0x912ff: SDMA */
typedef struct ccsr_cpm_sdma {
uchar sdsr;
- char res1[3];
- uchar sdmr;
- char res2[739];
+ char res1[3];
+ uchar sdmr;
+ char res2[739];
} ccsr_cpm_sdma_t;
/* 0x91300-0x9131f: FCC1 */
@@ -1228,7 +1228,7 @@ typedef struct ccsr_cpm_fcc3_ext {
/* 0x91400-0x915ef: TC layers */
typedef struct ccsr_cpm_tmp1 {
- char res[496];
+ char res[496];
} ccsr_cpm_tmp1_t;
/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
@@ -1296,7 +1296,7 @@ typedef struct ccsr_cpm_scc {
/* 0x91a80-0x91a9f */
typedef struct ccsr_cpm_tmp2 {
- char res[32];
+ char res[32];
} ccsr_cpm_tmp2_t;
/* 0x91aa0-0x91aff: SPI */
@@ -1338,16 +1338,16 @@ typedef struct ccsr_cpm {
/* Some references are into the unique and known dpram spaces,
* others are from the generic base.
*/
-#define im_dprambase im_dpram1
- u_char im_dpram1[16*1024];
- char res1[16*1024];
- u_char im_dpram2[16*1024];
- char res2[16*1024];
- ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
- ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
- ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
- ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
- ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
+#define im_dprambase im_dpram1
+ u_char im_dpram1[16*1024];
+ char res1[16*1024];
+ u_char im_dpram2[16*1024];
+ char res2[16*1024];
+ ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
+ ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
+ ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
+ ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
+ ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
ccsr_cpm_fcc1_t im_cpm_fcc1;
ccsr_cpm_fcc2_t im_cpm_fcc2;
ccsr_cpm_fcc3_t im_cpm_fcc3;
@@ -1553,7 +1553,7 @@ typedef struct par_io {
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
-#define MPC85xx_PORBMSR_HA 0x00070000
+#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
@@ -1561,13 +1561,13 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
-#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
-#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
-#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
-#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
-#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
+#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
+#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
+#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
+#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
+#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
-#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
+#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */
@@ -1593,13 +1593,13 @@ typedef struct ccsr_gur {
#define MPC85xx_DEVDISR_SEC 0x01000000
#define MPC85xx_DEVDISR_SRIO 0x00080000
#define MPC85xx_DEVDISR_RMSG 0x00040000
-#define MPC85xx_DEVDISR_DDR 0x00010000
-#define MPC85xx_DEVDISR_CPU 0x00008000
-#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
-#define MPC85xx_DEVDISR_TB 0x00004000
-#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
-#define MPC85xx_DEVDISR_CPU1 0x00002000
-#define MPC85xx_DEVDISR_TB1 0x00001000
+#define MPC85xx_DEVDISR_DDR 0x00010000
+#define MPC85xx_DEVDISR_CPU 0x00008000
+#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
+#define MPC85xx_DEVDISR_TB 0x00004000
+#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
+#define MPC85xx_DEVDISR_CPU1 0x00002000
+#define MPC85xx_DEVDISR_TB1 0x00001000
#define MPC85xx_DEVDISR_DMA 0x00000400
#define MPC85xx_DEVDISR_TSEC1 0x00000080
#define MPC85xx_DEVDISR_TSEC2 0x00000040
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 0b78c94..c03b4b8 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -119,7 +119,7 @@ typedef struct ccsr_ddr {
uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
- uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */
+ uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */
char res8[4];
uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
char res9[12];
@@ -464,7 +464,7 @@ typedef struct ccsr_dma {
/* tsec1-4: 24000-28000 */
typedef struct ccsr_tsec {
- uint id; /* 0x24000 - Controller ID Register */
+ uint id; /* 0x24000 - Controller ID Register */
char res1[12];
uint ievent; /* 0x24010 - Interrupt Event Register */
uint imask; /* 0x24014 - Interrupt Mask Register */
@@ -538,7 +538,7 @@ typedef struct ccsr_tsec {
uint rbifx; /* 0x24330 - Receive bit field extract control Register */
uint rqfar; /* 0x24334 - Receive queue filing table address Register */
uint rqfcr; /* 0x24338 - Receive queue filing table control Register */
- uint rqfpr; /* 0x2433c - Receive queue filing table property Register */
+ uint rqfpr; /* 0x2433c - Receive queue filing table property Register */
uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
char res28[56];
uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 49d6860..050a7b6 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -140,11 +140,16 @@ extern void _tlbia(void); /* invalidate all TLB entries */
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
- DBAT0, DBAT1, DBAT2, DBAT3
+ DBAT0, DBAT1, DBAT2, DBAT3,
+#ifdef CONFIG_HIGH_BATS
+ IBAT4, IBAT5, IBAT6, IBAT7,
+ DBAT4, DBAT5, DBAT6, DBAT7
+#endif
} ppc_bat_t;
extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
+extern void print_bats(void);
#endif /* __ASSEMBLY__ */
@@ -343,7 +348,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
#define MAS0_NV(x) ((x) & 0x00000FFF)
-#define MAS1_VALID 0x80000000
+#define MAS1_VALID 0x80000000
#define MAS1_IPROT 0x40000000
#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
#define MAS1_TS 0x00001000
@@ -685,7 +690,7 @@ extern int num_tlb_entries;
#define MSYNC .long 0x7c000000|\
(598<<1)
-#define MBAR_INST .long 0x7c000000|\
+#define MBAR_INST .long 0x7c000000|\
(854<<1)
#ifndef __ASSEMBLY__
diff --git a/include/asm-ppc/ppc4xx-intvec.h b/include/asm-ppc/ppc4xx-intvec.h
index e218119..5b45de4 100644
--- a/include/asm-ppc/ppc4xx-intvec.h
+++ b/include/asm-ppc/ppc4xx-intvec.h
@@ -323,9 +323,9 @@
#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */
#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */
-#define VECNUM_MS 18 /* MAL_SERR_INT */
-#define VECNUM_TXDE 18 /* MAL_TXDE_INT */
-#define VECNUM_RXDE 18 /* MAL_RXDE_INT */
+#define VECNUM_MS 18 /* MAL_SERR_INT */
+#define VECNUM_TXDE 18 /* MAL_TXDE_INT */
+#define VECNUM_RXDE 18 /* MAL_RXDE_INT */
#define VECNUM_MTE 19 /* MAL TXEOB */
#define VECNUM_MTE1 20 /* MAL TXEOB1 */
diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h
index 3c2f4e6..196613b 100644
--- a/include/asm-ppc/ptrace.h
+++ b/include/asm-ppc/ptrace.h
@@ -39,7 +39,7 @@ struct pt_regs {
PPC_REG trap; /* Reason for being here */
PPC_REG dar; /* Fault registers */
PPC_REG dsisr;
- PPC_REG result; /* Result of a system call */
+ PPC_REG result; /* Result of a system call */
};
#endif
diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h
index 4bd66a7..715c868 100644
--- a/include/asm-ppc/sigcontext.h
+++ b/include/asm-ppc/sigcontext.h
@@ -9,7 +9,7 @@ struct sigcontext_struct {
int signal;
unsigned long handler;
unsigned long oldmask;
- struct pt_regs *regs;
+ struct pt_regs *regs;
};
#endif
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index 786ba03..83af2f5 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -126,14 +126,14 @@ typedef struct bd_info {
#if defined(CONFIG_4xx)
#if defined(CONFIG_440GX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
- int bi_phynum[4]; /* Determines phy mapping */
- int bi_phymode[4]; /* Determines phy mode */
+ int bi_phynum[4]; /* Determines phy mapping */
+ int bi_phymode[4]; /* Determines phy mode */
#elif defined(CONFIG_405EP) || defined(CONFIG_440)
- int bi_phynum[2]; /* Determines phy mapping */
- int bi_phymode[2]; /* Determines phy mode */
+ int bi_phynum[2]; /* Determines phy mapping */
+ int bi_phymode[2]; /* Determines phy mode */
#else
- int bi_phynum[1]; /* Determines phy mapping */
- int bi_phymode[1]; /* Determines phy mode */
+ int bi_phynum[1]; /* Determines phy mapping */
+ int bi_phymode[1]; /* Determines phy mode */
#endif
#endif /* defined(CONFIG_4xx) */
} bd_t;
diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h
index 3c3c309..4e43a46 100644
--- a/include/asm-sh/cpu_sh7750.h
+++ b/include/asm-sh/cpu_sh7750.h
@@ -32,108 +32,108 @@
#endif
/* OCN */
-#define PTEH 0xFF000000
-#define PTEL 0xFF000004
-#define TTB 0xFF000008
-#define TEA 0xFF00000C
-#define MMUCR 0xFF000010
-#define BASRA 0xFF000014
+#define PTEH 0xFF000000
+#define PTEL 0xFF000004
+#define TTB 0xFF000008
+#define TEA 0xFF00000C
+#define MMUCR 0xFF000010
+#define BASRA 0xFF000014
#define BASRB 0xFF000018
#define CCR 0xFF00001C
-#define TRA 0xFF000020
-#define EXPEVT 0xFF000024
-#define INTEVT 0xFF000028
-#define PTEA 0xFF000034
-#define QACR0 0xFF000038
-#define QACR1 0xFF00003C
+#define TRA 0xFF000020
+#define EXPEVT 0xFF000024
+#define INTEVT 0xFF000028
+#define PTEA 0xFF000034
+#define QACR0 0xFF000038
+#define QACR1 0xFF00003C
/* UBC */
-#define BARA 0xFF200000
-#define BAMRA 0xFF200004
-#define BBRA 0xFF200008
-#define BARB 0xFF20000C
-#define BAMRB 0xFF200010
-#define BBRB 0xFF200014
-#define BDRB 0xFF200018
-#define BDMRB 0xFF20001C
-#define BRCR 0xFF200020
+#define BARA 0xFF200000
+#define BAMRA 0xFF200004
+#define BBRA 0xFF200008
+#define BARB 0xFF20000C
+#define BAMRB 0xFF200010
+#define BBRB 0xFF200014
+#define BDRB 0xFF200018
+#define BDMRB 0xFF20001C
+#define BRCR 0xFF200020
/* BSC */
#define BCR1 0xFF800000
#define BCR2 0xFF800004
-#define BCR3 0xFF800050
+#define BCR3 0xFF800050
#define BCR4 0xFE0A00F0
-#define WCR1 0xFF800008
-#define WCR2 0xFF80000C
-#define WCR3 0xFF800010
-#define MCR 0xFF800014
-#define PCR 0xFF800018
-#define RTCSR 0xFF80001C
-#define RTCNT 0xFF800020
-#define RTCOR 0xFF800024
-#define RFCR 0xFF800028
-#define PCTRA 0xFF80002C
-#define PDTRA 0xFF800030
-#define PCTRB 0xFF800040
-#define PDTRB 0xFF800044
-#define GPIOIC 0xFF800048
+#define WCR1 0xFF800008
+#define WCR2 0xFF80000C
+#define WCR3 0xFF800010
+#define MCR 0xFF800014
+#define PCR 0xFF800018
+#define RTCSR 0xFF80001C
+#define RTCNT 0xFF800020
+#define RTCOR 0xFF800024
+#define RFCR 0xFF800028
+#define PCTRA 0xFF80002C
+#define PDTRA 0xFF800030
+#define PCTRB 0xFF800040
+#define PDTRB 0xFF800044
+#define GPIOIC 0xFF800048
/* DMAC */
-#define SAR0 0xFFA00000
-#define DAR0 0xFFA00004
+#define SAR0 0xFFA00000
+#define DAR0 0xFFA00004
#define DMATCR0 0xFFA00008
#define CHCR0 0xFFA0000C
-#define SAR1 0xFFA00010
-#define DAR1 0xFFA00014
+#define SAR1 0xFFA00010
+#define DAR1 0xFFA00014
#define DMATCR1 0xFFA00018
-#define CHCR1 0xFFA0001C
-#define SAR2 0xFFA00020
-#define DAR2 0xFFA00024
+#define CHCR1 0xFFA0001C
+#define SAR2 0xFFA00020
+#define DAR2 0xFFA00024
#define DMATCR2 0xFFA00028
-#define CHCR2 0xFFA0002C
-#define SAR3 0xFFA00030
-#define DAR3 0xFFA00034
+#define CHCR2 0xFFA0002C
+#define SAR3 0xFFA00030
+#define DAR3 0xFFA00034
#define DMATCR3 0xFFA00038
-#define CHCR3 0xFFA0003C
-#define DMAOR 0xFFA00040
+#define CHCR3 0xFFA0003C
+#define DMAOR 0xFFA00040
#define SAR4 0xFFA00050
-#define DAR4 0xFFA00054
+#define DAR4 0xFFA00054
#define DMATCR4 0xFFA00058
/* CPG */
-#define FRQCR 0xFFC00000
-#define STBCR 0xFFC00004
-#define WTCNT 0xFFC00008
-#define WTCSR 0xFFC0000C
-#define STBCR2 0xFFC00010
+#define FRQCR 0xFFC00000
+#define STBCR 0xFFC00004
+#define WTCNT 0xFFC00008
+#define WTCSR 0xFFC0000C
+#define STBCR2 0xFFC00010
/* RTC */
#define R64CNT 0xFFC80000
#define RSECCNT 0xFFC80004
#define RMINCNT 0xFFC80008
-#define RHRCNT 0xFFC8000C
-#define RWKCNT 0xFFC80010
+#define RHRCNT 0xFFC8000C
+#define RWKCNT 0xFFC80010
#define RDAYCNT 0xFFC80014
#define RMONCNT 0xFFC80018
-#define RYRCNT 0xFFC8001C
-#define RSECAR 0xFFC80020
-#define RMINAR 0xFFC80024
-#define RHRAR 0xFFC80028
-#define RWKAR 0xFFC8002C
-#define RDAYAR 0xFFC80030
-#define RMONAR 0xFFC80034
-#define RCR1 0xFFC80038
-#define RCR2 0xFFC8003C
-#define RCR3 0xFFC80050
-#define RYRAR 0xFFC80054
+#define RYRCNT 0xFFC8001C
+#define RSECAR 0xFFC80020
+#define RMINAR 0xFFC80024
+#define RHRAR 0xFFC80028
+#define RWKAR 0xFFC8002C
+#define RDAYAR 0xFFC80030
+#define RMONAR 0xFFC80034
+#define RCR1 0xFFC80038
+#define RCR2 0xFFC8003C
+#define RCR3 0xFFC80050
+#define RYRAR 0xFFC80054
/* ICR */
-#define ICR 0xFFD00000
-#define IPRA 0xFFD00004
-#define IPRB 0xFFD00008
+#define ICR 0xFFD00000
+#define IPRA 0xFFD00004
+#define IPRB 0xFFD00008
#define IPRC 0xFFD0000C
-#define IPRD 0xFFD00010
-#define INTPRI 0xFE080000
+#define IPRD 0xFFD00010
+#define INTPRI 0xFE080000
#define INTREQ 0xFE080020
#define INTMSK 0xFE080040
#define INTMSKCL 0xFE080060
@@ -143,54 +143,54 @@
#define CLKSTPCLR 0xFE0A0008
/* TMU */
-#define TSTR2 0xFE100004
-#define TCOR3 0xFE100008
-#define TCNT3 0xFE10000C
-#define TCR3 0xFE100010
-#define TCOR4 0xFE100014
-#define TCNT4 0xFE100018
-#define TCR4 0xFE10001C
-#define TOCR 0xFFD80000
-#define TSTR0 0xFFD80004
+#define TSTR2 0xFE100004
+#define TCOR3 0xFE100008
+#define TCNT3 0xFE10000C
+#define TCR3 0xFE100010
+#define TCOR4 0xFE100014
+#define TCNT4 0xFE100018
+#define TCR4 0xFE10001C
+#define TOCR 0xFFD80000
+#define TSTR0 0xFFD80004
#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR0 0xFFD80010
-#define TCOR1 0xFFD80014
-#define TCNT1 0xFFD80018
-#define TCR1 0xFFD8001C
-#define TCOR2 0xFFD80020
-#define TCNT2 0xFFD80024
-#define TCR2 0xFFD80028
-#define TCPR2 0xFFD8002C
+#define TCNT0 0xFFD8000C
+#define TCR0 0xFFD80010
+#define TCOR1 0xFFD80014
+#define TCNT1 0xFFD80018
+#define TCR1 0xFFD8001C
+#define TCOR2 0xFFD80020
+#define TCNT2 0xFFD80024
+#define TCR2 0xFFD80028
+#define TCPR2 0xFFD8002C
#define TSTR TSTR0
/* SCI */
-#define SCSMR1 0xFFE00000
-#define SCBRR1 0xFFE00004
-#define SCSCR1 0xFFE00008
-#define SCTDR1 0xFFE0000C
-#define SCSSR1 0xFFE00010
-#define SCRDR1 0xFFE00014
+#define SCSMR1 0xFFE00000
+#define SCBRR1 0xFFE00004
+#define SCSCR1 0xFFE00008
+#define SCTDR1 0xFFE0000C
+#define SCSSR1 0xFFE00010
+#define SCRDR1 0xFFE00014
#define SCSCMR1 0xFFE00018
#define SCSPTR1 0xFFE0001C
#define SCF0_BASE SCSMR1
/* SCIF */
-#define SCSMR2 0xFFE80000
-#define SCBRR2 0xFFE80004
-#define SCSCR2 0xFFE80008
+#define SCSMR2 0xFFE80000
+#define SCBRR2 0xFFE80004
+#define SCSCR2 0xFFE80008
#define SCFTDR2 0xFFE8000C
-#define SCFSR2 0xFFE80010
+#define SCFSR2 0xFFE80010
#define SCFRDR2 0xFFE80014
-#define SCFCR2 0xFFE80018
-#define SCFDR2 0xFFE8001C
+#define SCFCR2 0xFFE80018
+#define SCFDR2 0xFFE8001C
#define SCSPTR2 0xFFE80020
-#define SCLSR2 0xFFE80024
+#define SCLSR2 0xFFE80024
#define SCIF1_BASE SCSMR2
/* H-UDI */
-#define SDIR 0xFFF00000
-#define SDDR 0xFFF00008
-#define SDINT 0xFFF00014
+#define SDIR 0xFFF00000
+#define SDDR 0xFFF00008
+#define SDINT 0xFFF00014
#endif /* _ASM_CPU_SH7750_H_ */
diff --git a/include/asm-sh/global_data.h b/include/asm-sh/global_data.h
index 521a66f..69af24a 100644
--- a/include/asm-sh/global_data.h
+++ b/include/asm-sh/global_data.h
@@ -45,6 +45,8 @@ typedef struct global_data
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13")
diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h
index 14cc1ac..16252cc 100644
--- a/include/asm-sh/ptrace.h
+++ b/include/asm-sh/ptrace.h
@@ -28,7 +28,7 @@
#define REG_PR 17
#define REG_SR 18
-#define REG_GBR 19
+#define REG_GBR 19
#define REG_MACH 20
#define REG_MACL 21
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index b353bc5..a62c422 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -23,21 +23,21 @@
register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
- __asm__ __volatile__ (".balign 4\n\t" \
- "stc.l gbr, @-r15\n\t" \
- "sts.l pr, @-r15\n\t" \
- "mov.l r8, @-r15\n\t" \
- "mov.l r9, @-r15\n\t" \
- "mov.l r10, @-r15\n\t" \
- "mov.l r11, @-r15\n\t" \
- "mov.l r12, @-r15\n\t" \
- "mov.l r13, @-r15\n\t" \
- "mov.l r14, @-r15\n\t" \
+ __asm__ __volatile__ (".balign 4\n\t" \
+ "stc.l gbr, @-r15\n\t" \
+ "sts.l pr, @-r15\n\t" \
+ "mov.l r8, @-r15\n\t" \
+ "mov.l r9, @-r15\n\t" \
+ "mov.l r10, @-r15\n\t" \
+ "mov.l r11, @-r15\n\t" \
+ "mov.l r12, @-r15\n\t" \
+ "mov.l r13, @-r15\n\t" \
+ "mov.l r14, @-r15\n\t" \
"mov.l r15, @r1 ! save SP\n\t" \
"mov.l @r6, r15 ! change to new stack\n\t" \
- "mova 1f, %0\n\t" \
- "mov.l %0, @r2 ! save PC\n\t" \
- "mov.l 2f, %0\n\t" \
+ "mova 1f, %0\n\t" \
+ "mov.l %0, @r2 ! save PC\n\t" \
+ "mov.l 2f, %0\n\t" \
"jmp @%0 ! call __switch_to\n\t" \
" lds r7, pr ! with return to new PC\n\t" \
".balign 4\n" \
@@ -54,8 +54,8 @@
"lds.l @r15+, pr\n\t" \
"ldc.l @r15+, gbr\n\t" \
: "=z" (__last) \
- : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
- "r" (__ts5), "r" (__ts6), "r" (__ts7) \
+ : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
+ "r" (__ts5), "r" (__ts6), "r" (__ts7) \
: "r3", "t"); \
last = __last; \
} while (0)
@@ -145,7 +145,7 @@ do { \
"mov.l 1f, %0\n\t" \
"or %1, %0\n\t" \
"jmp @%0\n\t" \
- " nop\n\t" \
+ " nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
diff --git a/include/asm-sparc/global_data.h b/include/asm-sparc/global_data.h
index 7c29fc6..de2c84b 100644
--- a/include/asm-sparc/global_data.h
+++ b/include/asm-sparc/global_data.h
@@ -79,6 +79,9 @@ typedef struct global_data {
#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
+#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("%g7")
diff --git a/include/atmel_lcdc.h b/include/atmel_lcdc.h
new file mode 100644
index 0000000..73dd8f7
--- /dev/null
+++ b/include/atmel_lcdc.h
@@ -0,0 +1,177 @@
+/*
+ * Header file for AT91/AT32 LCD Controller
+ *
+ * Data structure and register user interface
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ATMEL_LCDC_H__
+#define __ATMEL_LCDC_H__
+
+#define ATMEL_LCDC_DMABADDR1 0x00
+#define ATMEL_LCDC_DMABADDR2 0x04
+#define ATMEL_LCDC_DMAFRMPT1 0x08
+#define ATMEL_LCDC_DMAFRMPT2 0x0c
+#define ATMEL_LCDC_DMAFRMADD1 0x10
+#define ATMEL_LCDC_DMAFRMADD2 0x14
+
+#define ATMEL_LCDC_DMAFRMCFG 0x18
+#define ATMEL_LCDC_FRSIZE (0x7fffff << 0)
+#define ATMEL_LCDC_BLENGTH_OFFSET 24
+#define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET)
+
+#define ATMEL_LCDC_DMACON 0x1c
+#define ATMEL_LCDC_DMAEN (0x1 << 0)
+#define ATMEL_LCDC_DMARST (0x1 << 1)
+#define ATMEL_LCDC_DMABUSY (0x1 << 2)
+#define ATMEL_LCDC_DMAUPDT (0x1 << 3)
+#define ATMEL_LCDC_DMA2DEN (0x1 << 4)
+
+#define ATMEL_LCDC_DMA2DCFG 0x20
+#define ATMEL_LCDC_ADDRINC_OFFSET 0
+#define ATMEL_LCDC_ADDRINC (0xffff)
+#define ATMEL_LCDC_PIXELOFF_OFFSET 24
+#define ATMEL_LCDC_PIXELOFF (0x1f << 24)
+
+#define ATMEL_LCDC_LCDCON1 0x0800
+#define ATMEL_LCDC_BYPASS (1 << 0)
+#define ATMEL_LCDC_CLKVAL_OFFSET 12
+#define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
+#define ATMEL_LCDC_LINCNT (0x7ff << 21)
+
+#define ATMEL_LCDC_LCDCON2 0x0804
+#define ATMEL_LCDC_DISTYPE (3 << 0)
+#define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0)
+#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0)
+#define ATMEL_LCDC_DISTYPE_TFT (2 << 0)
+#define ATMEL_LCDC_SCANMOD (1 << 2)
+#define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2)
+#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2)
+#define ATMEL_LCDC_IFWIDTH (3 << 3)
+#define ATMEL_LCDC_IFWIDTH_4 (0 << 3)
+#define ATMEL_LCDC_IFWIDTH_8 (1 << 3)
+#define ATMEL_LCDC_IFWIDTH_16 (2 << 3)
+#define ATMEL_LCDC_PIXELSIZE (7 << 5)
+#define ATMEL_LCDC_PIXELSIZE_1 (0 << 5)
+#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5)
+#define ATMEL_LCDC_PIXELSIZE_4 (2 << 5)
+#define ATMEL_LCDC_PIXELSIZE_8 (3 << 5)
+#define ATMEL_LCDC_PIXELSIZE_16 (4 << 5)
+#define ATMEL_LCDC_PIXELSIZE_24 (5 << 5)
+#define ATMEL_LCDC_PIXELSIZE_32 (6 << 5)
+#define ATMEL_LCDC_INVVD (1 << 8)
+#define ATMEL_LCDC_INVVD_NORMAL (0 << 8)
+#define ATMEL_LCDC_INVVD_INVERTED (1 << 8)
+#define ATMEL_LCDC_INVFRAME (1 << 9 )
+#define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9)
+#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9)
+#define ATMEL_LCDC_INVLINE (1 << 10)
+#define ATMEL_LCDC_INVLINE_NORMAL (0 << 10)
+#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10)
+#define ATMEL_LCDC_INVCLK (1 << 11)
+#define ATMEL_LCDC_INVCLK_NORMAL (0 << 11)
+#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11)
+#define ATMEL_LCDC_INVDVAL (1 << 12)
+#define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12)
+#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12)
+#define ATMEL_LCDC_CLKMOD (1 << 15)
+#define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
+#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
+#define ATMEL_LCDC_MEMOR (1 << 31)
+#define ATMEL_LCDC_MEMOR_BIG (0 << 31)
+#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31)
+
+#define ATMEL_LCDC_TIM1 0x0808
+#define ATMEL_LCDC_VFP (0xffU << 0)
+#define ATMEL_LCDC_VBP_OFFSET 8
+#define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET)
+#define ATMEL_LCDC_VPW_OFFSET 16
+#define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET)
+#define ATMEL_LCDC_VHDLY_OFFSET 24
+#define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET)
+
+#define ATMEL_LCDC_TIM2 0x080c
+#define ATMEL_LCDC_HBP (0xffU << 0)
+#define ATMEL_LCDC_HPW_OFFSET 8
+#define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET)
+#define ATMEL_LCDC_HFP_OFFSET 21
+#define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET)
+
+#define ATMEL_LCDC_LCDFRMCFG 0x0810
+#define ATMEL_LCDC_LINEVAL (0x7ff << 0)
+#define ATMEL_LCDC_HOZVAL_OFFSET 21
+#define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
+
+#define ATMEL_LCDC_FIFO 0x0814
+#define ATMEL_LCDC_FIFOTH (0xffff)
+
+#define ATMEL_LCDC_MVAL 0x0818
+
+#define ATMEL_LCDC_DP1_2 0x081c
+#define ATMEL_LCDC_DP4_7 0x0820
+#define ATMEL_LCDC_DP3_5 0x0824
+#define ATMEL_LCDC_DP2_3 0x0828
+#define ATMEL_LCDC_DP5_7 0x082c
+#define ATMEL_LCDC_DP3_4 0x0830
+#define ATMEL_LCDC_DP4_5 0x0834
+#define ATMEL_LCDC_DP6_7 0x0838
+#define ATMEL_LCDC_DP1_2_VAL (0xff)
+#define ATMEL_LCDC_DP4_7_VAL (0xfffffff)
+#define ATMEL_LCDC_DP3_5_VAL (0xfffff)
+#define ATMEL_LCDC_DP2_3_VAL (0xfff)
+#define ATMEL_LCDC_DP5_7_VAL (0xfffffff)
+#define ATMEL_LCDC_DP3_4_VAL (0xffff)
+#define ATMEL_LCDC_DP4_5_VAL (0xfffff)
+#define ATMEL_LCDC_DP6_7_VAL (0xfffffff)
+
+#define ATMEL_LCDC_PWRCON 0x083c
+#define ATMEL_LCDC_PWR (1 << 0)
+#define ATMEL_LCDC_GUARDT_OFFSET 1
+#define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET)
+#define ATMEL_LCDC_BUSY (1 << 31)
+
+#define ATMEL_LCDC_CONTRAST_CTR 0x0840
+#define ATMEL_LCDC_PS (3 << 0)
+#define ATMEL_LCDC_PS_DIV1 (0 << 0)
+#define ATMEL_LCDC_PS_DIV2 (1 << 0)
+#define ATMEL_LCDC_PS_DIV4 (2 << 0)
+#define ATMEL_LCDC_PS_DIV8 (3 << 0)
+#define ATMEL_LCDC_POL (1 << 2)
+#define ATMEL_LCDC_POL_NEGATIVE (0 << 2)
+#define ATMEL_LCDC_POL_POSITIVE (1 << 2)
+#define ATMEL_LCDC_ENA (1 << 3)
+#define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3)
+#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3)
+
+#define ATMEL_LCDC_CONTRAST_VAL 0x0844
+#define ATMEL_LCDC_CVAL (0xff)
+
+#define ATMEL_LCDC_IER 0x0848
+#define ATMEL_LCDC_IDR 0x084c
+#define ATMEL_LCDC_IMR 0x0850
+#define ATMEL_LCDC_ISR 0x0854
+#define ATMEL_LCDC_ICR 0x0858
+#define ATMEL_LCDC_LNI (1 << 0)
+#define ATMEL_LCDC_LSTLNI (1 << 1)
+#define ATMEL_LCDC_EOFI (1 << 2)
+#define ATMEL_LCDC_UFLWI (1 << 4)
+#define ATMEL_LCDC_OWRI (1 << 5)
+#define ATMEL_LCDC_MERI (1 << 6)
+
+#define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4))
+
+#endif /* __ATMEL_LCDC_H__ */
diff --git a/include/bcm5221.h b/include/bcm5221.h
index 6fb94aa..61424b1 100644
--- a/include/bcm5221.h
+++ b/include/bcm5221.h
@@ -23,7 +23,7 @@
* MA 02111-1307 USA
*/
-#define BCM5221_BMCR 0 /* Basic Mode Control Register */
+#define BCM5221_BMCR 0 /* Basic Mode Control Register */
#define BCM5221_BMSR 1 /* Basic Mode Status Register */
#define BCM5221_PHYID1 2 /* PHY Identifier Register 1 */
#define BCM5221_PHYID2 3 /* PHY Identifier Register 2 */
diff --git a/include/bedbug/ppc.h b/include/bedbug/ppc.h
index 9cc8f9f..46bf8db 100644
--- a/include/bedbug/ppc.h
+++ b/include/bedbug/ppc.h
@@ -321,7 +321,7 @@ struct opcode {
array are the operand identifiers */
int (*hfunc)(struct ppc_ctx *);
- /* Address of a function to handle the given
+ /* Address of a function to handle the given
mnemonic */
char * name; /* The symbolic name of this opcode */
diff --git a/include/bedbug/tables.h b/include/bedbug/tables.h
index 66cf8ea..e675de3 100644
--- a/include/bedbug/tables.h
+++ b/include/bedbug/tables.h
@@ -12,43 +12,43 @@
*/
struct operand operands[] = {
- /*Field Name Bits Shift Hint Position */
- /*----- ------ ----- ----- ---- ------------ */
- { O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */
+ /*Field Name Bits Shift Hint Position */
+ /*----- ------ ----- ----- ---- ------------ */
+ { O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */
{ O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */
- { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */
- { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */
- { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */
- { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */
- { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */
- { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */
+ { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */
+ { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */
+ { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */
+ { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */
+ { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */
+ { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */
{ O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */
- { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */
- { O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */
- { O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */
- { O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */
+ { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */
+ { O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */
+ { O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */
+ { O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */
{ O_LI, "O_LI", 24, 2, OH_ADDR }, /* 6-29 */
- { O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */
- { O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */
- { O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */
- { O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */
- { O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */
- { O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */
- { O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */
- { O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */
- { O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */
- { O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */
- { O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */
+ { O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */
+ { O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */
+ { O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */
+ { O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */
+ { O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */
+ { O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */
+ { O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */
+ { O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */
+ { O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */
+ { O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */
+ { O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */
{ O_SIMM, "O_SIMM", 16, 0, 0 }, /* 16-31 */
- { O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */
- { O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */
+ { O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */
+ { O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */
{ O_UIMM, "O_UIMM", 16, 0, 0 }, /* 16-31 */
- { O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */
- { O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */
- { O_L, "O_L", 1, 21, 0 }, /* 10 */
+ { O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */
+ { O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */
+ { O_L, "O_L", 1, 21, 0 }, /* 10 */
{ O_spr, "O_spr", 10, 11, OH_SPR }, /* 11-20 */
{ O_tbr, "O_tbr", 10, 11, OH_TBR }, /* 11-20 */
- { O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */
+ { O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */
};
const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
@@ -64,418 +64,418 @@ const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
bit locations */
struct opcode opcodes[] = {
- { D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0},
- 0, "twi", 0 },
- { D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "mulli", 0 },
- { D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "subfic", 0 },
- { D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0},
- 0, "cmpli", 0 },
- { D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0},
- 0, "cmpi", 0 },
- { D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "addic", 0 },
- { D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "addic.", 0 },
- { D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "addi", H_RA0_IS_0 },
- { D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "addis", H_RA0_IS_0|H_IMM_HIGH },
- { B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
- handle_bc, "bc", H_RELATIVE },
- { B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
- 0, "bcl", H_RELATIVE },
- { B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
- 0, "bca", 0 },
- { B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
- 0, "bcla", 0 },
- { SC_OPCODE(17), SC_MASK, {0},
- 0, "sc", 0 },
- { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0},
- 0, "b", H_RELATIVE },
- { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0},
- 0, "bl", H_RELATIVE },
- { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0},
- 0, "ba", 0 },
- { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0},
- 0, "bla", 0 },
- { XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS},
- 0, "mcrf", 0 },
+ { D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0},
+ 0, "twi", 0 },
+ { D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0},
+ 0, "mulli", 0 },
+ { D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0},
+ 0, "subfic", 0 },
+ { D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0},
+ 0, "cmpli", 0 },
+ { D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0},
+ 0, "cmpi", 0 },
+ { D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0},
+ 0, "addic", 0 },
+ { D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0},
+ 0, "addic.", 0 },
+ { D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0},
+ 0, "addi", H_RA0_IS_0 },
+ { D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0},
+ 0, "addis", H_RA0_IS_0|H_IMM_HIGH },
+ { B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+ handle_bc, "bc", H_RELATIVE },
+ { B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+ 0, "bcl", H_RELATIVE },
+ { B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+ 0, "bca", 0 },
+ { B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+ 0, "bcla", 0 },
+ { SC_OPCODE(17), SC_MASK, {0},
+ 0, "sc", 0 },
+ { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0},
+ 0, "b", H_RELATIVE },
+ { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0},
+ 0, "bl", H_RELATIVE },
+ { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0},
+ 0, "ba", 0 },
+ { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0},
+ 0, "bla", 0 },
+ { XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS},
+ 0, "mcrf", 0 },
{ XL_OPCODE(19,16,0), XL_MASK, {O_BO, O_BI, O_LK, 0},
- 0, "bclr", 0 },
+ 0, "bclr", 0 },
{ XL_OPCODE(19,16,1), XL_MASK, {O_BO, O_BI, O_LK, 0},
- 0, "bclrl", 0 },
+ 0, "bclrl", 0 },
{ XL_OPCODE(19,33,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crnor", 0 },
+ 0, "crnor", 0 },
{ XL_OPCODE(19,50,0), XL_MASK, {0},
- 0, "rfi", 0 },
+ 0, "rfi", 0 },
{ XL_OPCODE(19,129,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crandc", 0 },
+ 0, "crandc", 0 },
{ XL_OPCODE(19,150,0), XL_MASK, {0},
- 0, "isync", 0 },
+ 0, "isync", 0 },
{ XL_OPCODE(19,193,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crxor", 0 },
+ 0, "crxor", 0 },
{ XL_OPCODE(19,225,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crnand", 0 },
+ 0, "crnand", 0 },
{ XL_OPCODE(19,257,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crand", 0 },
+ 0, "crand", 0 },
{ XL_OPCODE(19,289,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "creqv", 0 },
+ 0, "creqv", 0 },
{ XL_OPCODE(19,417,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crorc", 0 },
+ 0, "crorc", 0 },
{ XL_OPCODE(19,449,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "cror", 0 },
+ 0, "cror", 0 },
{ XL_OPCODE(19,528,0), XL_MASK, {O_BO, O_BI, O_LK, 0},
- 0, "bcctr", 0 },
+ 0, "bcctr", 0 },
{ XL_OPCODE(19,528,1), XL_MASK, {O_BO, O_BI, O_LK, 0},
- 0, "bcctrl", 0 },
- { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
- 0, "rlwimi", 0 },
- { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
- 0, "rlwimi.", 0 },
- { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
- 0, "rlwinm", 0 },
- { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
- 0, "rlwinm.", 0 },
- { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
- 0, "rlwnm", 0 },
- { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
- 0, "rlwnm.", 0 },
- { D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "ori", 0 },
- { D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "oris", H_IMM_HIGH },
- { D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "xori", 0 },
- { D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "xoris", H_IMM_HIGH },
- { D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "andi.", 0 },
- { D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "andis.", H_IMM_HIGH },
- { X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0},
- 0, "cmp", 0 },
- { X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0},
- 0, "tw", 0 },
+ 0, "bcctrl", 0 },
+ { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+ 0, "rlwimi", 0 },
+ { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+ 0, "rlwimi.", 0 },
+ { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+ 0, "rlwinm", 0 },
+ { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+ 0, "rlwinm.", 0 },
+ { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
+ 0, "rlwnm", 0 },
+ { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
+ 0, "rlwnm.", 0 },
+ { D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0},
+ 0, "ori", 0 },
+ { D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0},
+ 0, "oris", H_IMM_HIGH },
+ { D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0},
+ 0, "xori", 0 },
+ { D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0},
+ 0, "xoris", H_IMM_HIGH },
+ { D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0},
+ 0, "andi.", 0 },
+ { D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0},
+ 0, "andis.", H_IMM_HIGH },
+ { X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0},
+ 0, "cmp", 0 },
+ { X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0},
+ 0, "tw", 0 },
{ XO_OPCODE(31,8,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfc", 0 },
+ 0, "subfc", 0 },
{ XO_OPCODE(31,8,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfc.", 0 },
+ 0, "subfc.", 0 },
{ XO_OPCODE(31,10,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addc", 0 },
+ 0, "addc", 0 },
{ XO_OPCODE(31,10,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addc.", 0 },
+ 0, "addc.", 0 },
{ XO_OPCODE(31,11,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
- 0, "mulhwu", 0 },
+ 0, "mulhwu", 0 },
{ XO_OPCODE(31,11,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
- 0, "mulhwu.", 0 },
- { X_OPCODE(31,19,0), X_MASK, {O_rD, 0},
- 0, "mfcr", 0 },
- { X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lwarx", H_RA0_IS_0 },
- { X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lwzx", H_RA0_IS_0 },
- { X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "slw", 0 },
- { X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "slw.", 0 },
- { X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 },
- 0, "cntlzw", 0 },
- { X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "cntlzw.", 0 },
- { X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "and", 0 },
- { X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "and.", 0 },
- { X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0},
- 0, "cmpl", 0 },
+ 0, "mulhwu.", 0 },
+ { X_OPCODE(31,19,0), X_MASK, {O_rD, 0},
+ 0, "mfcr", 0 },
+ { X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0},
+ 0, "lwarx", H_RA0_IS_0 },
+ { X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0},
+ 0, "lwzx", H_RA0_IS_0 },
+ { X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
+ 0, "slw", 0 },
+ { X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
+ 0, "slw.", 0 },
+ { X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 },
+ 0, "cntlzw", 0 },
+ { X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
+ 0, "cntlzw.", 0 },
+ { X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
+ 0, "and", 0 },
+ { X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
+ 0, "and.", 0 },
+ { X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0},
+ 0, "cmpl", 0 },
{ XO_OPCODE(31,40,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subf", 0 },
+ 0, "subf", 0 },
{ XO_OPCODE(31,40,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subf.", 0 },
- { X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbst", H_RA0_IS_0 },
- { X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lwzux", 0 },
- { X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "andc", 0 },
- { X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "andc.", 0 },
+ 0, "subf.", 0 },
+ { X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0},
+ 0, "dcbst", H_RA0_IS_0 },
+ { X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0},
+ 0, "lwzux", 0 },
+ { X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
+ 0, "andc", 0 },
+ { X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
+ 0, "andc.", 0 },
{ XO_OPCODE(31,75,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
- 0, "mulhw", 0 },
+ 0, "mulhw", 0 },
{ XO_OPCODE(31,75,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
- 0, "mulhw.", 0 },
- { X_OPCODE(31,83,0), X_MASK, {O_rD, 0},
- 0, "mfmsr", 0 },
- { X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbf", H_RA0_IS_0 },
- { X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lbzx", H_RA0_IS_0 },
+ 0, "mulhw.", 0 },
+ { X_OPCODE(31,83,0), X_MASK, {O_rD, 0},
+ 0, "mfmsr", 0 },
+ { X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0},
+ 0, "dcbf", H_RA0_IS_0 },
+ { X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0},
+ 0, "lbzx", H_RA0_IS_0 },
{ XO_OPCODE(31,104,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "neg", 0 },
+ 0, "neg", 0 },
{ XO_OPCODE(31,104,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "neg.", 0 },
+ 0, "neg.", 0 },
{ X_OPCODE(31,119,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lbzux", 0 },
+ 0, "lbzux", 0 },
{ X_OPCODE(31,124,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "nor", 0 },
+ 0, "nor", 0 },
{ X_OPCODE(31,124,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "nor.", 0 },
+ 0, "nor.", 0 },
{ XO_OPCODE(31,136,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfe", 0 },
+ 0, "subfe", 0 },
{ XO_OPCODE(31,136,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfe.", 0 },
+ 0, "subfe.", 0 },
{ XO_OPCODE(31,138,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "adde", 0 },
+ 0, "adde", 0 },
{ XO_OPCODE(31,138,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "adde.", 0 },
+ 0, "adde.", 0 },
{ XFX_OPCODE(31,144,0), XFX_MASK, {O_CRM, O_rS, 0},
- 0, "mtcrf", 0 },
+ 0, "mtcrf", 0 },
{ X_OPCODE(31,146,0), X_MASK, {O_rS, 0},
- 0, "mtmsr", 0 },
+ 0, "mtmsr", 0 },
{ X_OPCODE(31,150,1), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stwcx.", 0 },
+ 0, "stwcx.", 0 },
{ X_OPCODE(31,151,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stwx", 0 },
+ 0, "stwx", 0 },
{ X_OPCODE(31,183,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stwux", 0 },
+ 0, "stwux", 0 },
{ XO_OPCODE(31,200,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfze", 0 },
+ 0, "subfze", 0 },
{ XO_OPCODE(31,200,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfze.", 0 },
+ 0, "subfze.", 0 },
{ XO_OPCODE(31,202,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addze", 0 },
+ 0, "addze", 0 },
{ XO_OPCODE(31,202,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addze.", 0 },
+ 0, "addze.", 0 },
{ X_OPCODE(31,210,0), X_MASK, {O_SR, O_rS, 0},
- 0, "mtsr", 0 },
+ 0, "mtsr", 0 },
{ X_OPCODE(31,215,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stbx", H_RA0_IS_0 },
+ 0, "stbx", H_RA0_IS_0 },
{ XO_OPCODE(31,232,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfme", 0 },
+ 0, "subfme", 0 },
{ XO_OPCODE(31,232,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfme.", 0 },
+ 0, "subfme.", 0 },
{ XO_OPCODE(31,234,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addme", 0 },
+ 0, "addme", 0 },
{ XO_OPCODE(31,234,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addme.", 0 },
+ 0, "addme.", 0 },
{ XO_OPCODE(31,235,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "mullw", 0 },
+ 0, "mullw", 0 },
{ XO_OPCODE(31,235,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "mullw.", 0 },
+ 0, "mullw.", 0 },
{ X_OPCODE(31,242,0), X_MASK, {O_rS, O_rB, 0},
- 0, "mtsrin", 0 },
+ 0, "mtsrin", 0 },
{ X_OPCODE(31,246,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbtst", H_RA0_IS_0 },
+ 0, "dcbtst", H_RA0_IS_0 },
{ X_OPCODE(31,247,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stbux", 0 },
+ 0, "stbux", 0 },
{ XO_OPCODE(31,266,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "add", 0 },
+ 0, "add", 0 },
{ XO_OPCODE(31,266,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "add.", 0 },
+ 0, "add.", 0 },
{ X_OPCODE(31,278,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbt", H_RA0_IS_0 },
+ 0, "dcbt", H_RA0_IS_0 },
{ X_OPCODE(31,279,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhzx", H_RA0_IS_0 },
+ 0, "lhzx", H_RA0_IS_0 },
{ X_OPCODE(31,284,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "eqv", 0 },
+ 0, "eqv", 0 },
{ X_OPCODE(31,284,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "eqv.", 0 },
+ 0, "eqv.", 0 },
{ X_OPCODE(31,306,0), X_MASK, {O_rB, 0},
- 0, "tlbie", 0 },
+ 0, "tlbie", 0 },
{ X_OPCODE(31,310,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "eciwx", H_RA0_IS_0 },
+ 0, "eciwx", H_RA0_IS_0 },
{ X_OPCODE(31,311,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhzux", 0 },
+ 0, "lhzux", 0 },
{ X_OPCODE(31,316,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "xor", 0 },
+ 0, "xor", 0 },
{ X_OPCODE(31,316,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "xor.", 0 },
+ 0, "xor.", 0 },
{ XFX_OPCODE(31,339,0), XFX_MASK, {O_rD, O_spr, 0},
- 0, "mfspr", 0 },
+ 0, "mfspr", 0 },
{ X_OPCODE(31,343,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhax", H_RA0_IS_0 },
+ 0, "lhax", H_RA0_IS_0 },
{ X_OPCODE(31,370,0), X_MASK, {0},
- 0, "tlbia", 0 },
+ 0, "tlbia", 0 },
{ XFX_OPCODE(31,371,0), XFX_MASK, {O_rD, O_tbr, 0},
- 0, "mftb", 0 },
+ 0, "mftb", 0 },
{ X_OPCODE(31,375,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhaux", 0 },
+ 0, "lhaux", 0 },
{ X_OPCODE(31,407,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "sthx", H_RA0_IS_0 },
+ 0, "sthx", H_RA0_IS_0 },
{ X_OPCODE(31,412,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "orc", 0 },
+ 0, "orc", 0 },
{ X_OPCODE(31,412,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "orc.", 0 },
+ 0, "orc.", 0 },
{ X_OPCODE(31,438,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "ecowx", H_RA0_IS_0 },
+ 0, "ecowx", H_RA0_IS_0 },
{ X_OPCODE(31,439,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "sthux", 0 },
+ 0, "sthux", 0 },
{ X_OPCODE(31,444,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "or", 0 },
+ 0, "or", 0 },
{ X_OPCODE(31,444,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "or.", 0 },
+ 0, "or.", 0 },
{ XO_OPCODE(31,459,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwu", 0 },
+ 0, "divwu", 0 },
{ XO_OPCODE(31,459,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwu.", 0 },
+ 0, "divwu.", 0 },
{ XFX_OPCODE(31,467,0), XFX_MASK, {O_spr, O_rS, 0},
- 0, "mtspr", 0 },
+ 0, "mtspr", 0 },
{ X_OPCODE(31,470,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbi", H_RA0_IS_0 },
+ 0, "dcbi", H_RA0_IS_0 },
{ X_OPCODE(31,476,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "nand", 0 },
+ 0, "nand", 0 },
{ X_OPCODE(31,476,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc,0},
- 0, "nand.", 0 },
+ 0, "nand.", 0 },
{ XO_OPCODE(31,491,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divw", 0 },
+ 0, "divw", 0 },
{ XO_OPCODE(31,491,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divw.", 0 },
+ 0, "divw.", 0 },
{ X_OPCODE(31,512,0), X_MASK, {O_crfD, 0},
- 0, "mcrxr", 0 },
+ 0, "mcrxr", 0 },
{ XO_OPCODE(31,8,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfco", 0 },
+ 0, "subfco", 0 },
{ XO_OPCODE(31,8,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfco.", 0 },
+ 0, "subfco.", 0 },
{ XO_OPCODE(31,10,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addco", 0 },
+ 0, "addco", 0 },
{ XO_OPCODE(31,10,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addco.", 0 },
+ 0, "addco.", 0 },
{ X_OPCODE(31,533,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lswx", H_RA0_IS_0 },
+ 0, "lswx", H_RA0_IS_0 },
{ X_OPCODE(31,534,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lwbrx", H_RA0_IS_0 },
+ 0, "lwbrx", H_RA0_IS_0 },
{ X_OPCODE(31,536,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "srw", 0 },
+ 0, "srw", 0 },
{ X_OPCODE(31,536,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "srw.", 0 },
+ 0, "srw.", 0 },
{ XO_OPCODE(31,40,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfo", 0 },
+ 0, "subfo", 0 },
{ XO_OPCODE(31,40,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfo.", 0 },
+ 0, "subfo.", 0 },
{ X_OPCODE(31,566,0), X_MASK, {0},
- 0, "tlbsync", 0 },
+ 0, "tlbsync", 0 },
{ X_OPCODE(31,595,0), X_MASK, {O_rD, O_SR, 0},
- 0, "mfsr", 0 },
+ 0, "mfsr", 0 },
{ X_OPCODE(31,597,0), X_MASK, {O_rD, O_rA, O_NB, 0},
- 0, "lswi", H_RA0_IS_0 },
+ 0, "lswi", H_RA0_IS_0 },
{ X_OPCODE(31,598,0), X_MASK, {0},
- 0, "sync", 0 },
+ 0, "sync", 0 },
{ XO_OPCODE(31,104,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "nego", 0 },
+ 0, "nego", 0 },
{ XO_OPCODE(31,104,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "nego.", 0 },
+ 0, "nego.", 0 },
{ XO_OPCODE(31,136,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfeo", 0 },
+ 0, "subfeo", 0 },
{ XO_OPCODE(31,136,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfeo.", 0 },
+ 0, "subfeo.", 0 },
{ XO_OPCODE(31,138,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addeo", 0 },
+ 0, "addeo", 0 },
{ XO_OPCODE(31,138,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addeo.", 0 },
+ 0, "addeo.", 0 },
{ X_OPCODE(31,659,0), X_MASK, {O_rD, O_rB, 0},
- 0, "mfsrin", 0 },
+ 0, "mfsrin", 0 },
{ X_OPCODE(31,661,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stswx", H_RA0_IS_0 },
+ 0, "stswx", H_RA0_IS_0 },
{ X_OPCODE(31,662,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stwbrx", H_RA0_IS_0 },
+ 0, "stwbrx", H_RA0_IS_0 },
{ XO_OPCODE(31,200,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfzeo", 0 },
+ 0, "subfzeo", 0 },
{ XO_OPCODE(31,200,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfzeo.", 0 },
+ 0, "subfzeo.", 0 },
{ XO_OPCODE(31,202,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addzeo", 0 },
+ 0, "addzeo", 0 },
{ XO_OPCODE(31,202,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addzeo.", 0 },
+ 0, "addzeo.", 0 },
{ X_OPCODE(31,725,0), X_MASK, {O_rS, O_rA, O_NB, 0},
- 0, "stswi", H_RA0_IS_0 },
+ 0, "stswi", H_RA0_IS_0 },
{ XO_OPCODE(31,232,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfmeo", 0 },
+ 0, "subfmeo", 0 },
{ XO_OPCODE(31,232,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfmeo.", 0 },
+ 0, "subfmeo.", 0 },
{ XO_OPCODE(31,234,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addmeo", 0 },
+ 0, "addmeo", 0 },
{ XO_OPCODE(31,234,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addmeo.", 0 },
+ 0, "addmeo.", 0 },
{ XO_OPCODE(31,235,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "mullwo", 0 },
+ 0, "mullwo", 0 },
{ XO_OPCODE(31,235,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "mullwo.", 0 },
+ 0, "mullwo.", 0 },
{ XO_OPCODE(31,266,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addo", 0 },
+ 0, "addo", 0 },
{ XO_OPCODE(31,266,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addo.", 0 },
+ 0, "addo.", 0 },
{ X_OPCODE(31,790,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhbrx", H_RA0_IS_0 },
+ 0, "lhbrx", H_RA0_IS_0 },
{ X_OPCODE(31,792,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "sraw", 0 },
+ 0, "sraw", 0 },
{ X_OPCODE(31,792,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "sraw.", 0 },
+ 0, "sraw.", 0 },
{ X_OPCODE(31,824,0), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0},
- 0, "srawi", 0 },
+ 0, "srawi", 0 },
{ X_OPCODE(31,824,1), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0},
- 0, "srawi.", 0 },
+ 0, "srawi.", 0 },
{ X_OPCODE(31,854,0), X_MASK, {0},
- 0, "eieio", 0 },
+ 0, "eieio", 0 },
{ X_OPCODE(31,918,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "sthbrx", H_RA0_IS_0 },
+ 0, "sthbrx", H_RA0_IS_0 },
{ X_OPCODE(31,922,0), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "extsh", 0 },
+ 0, "extsh", 0 },
{ X_OPCODE(31,922,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "extsh.", 0 },
+ 0, "extsh.", 0 },
{ X_OPCODE(31,954,0), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "extsb", 0 },
+ 0, "extsb", 0 },
{ X_OPCODE(31,954,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "extsb.", 0 },
+ 0, "extsb.", 0 },
{ XO_OPCODE(31,459,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwuo", 0 },
+ 0, "divwuo", 0 },
{ XO_OPCODE(31,459,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwuo.", 0 },
+ 0, "divwuo.", 0 },
{ X_OPCODE(31,978,0), X_MASK, {O_rB, 0},
- 0, "tlbld", 0 },
+ 0, "tlbld", 0 },
{ X_OPCODE(31,982,0), X_MASK, {O_rA, O_rB, 0},
- 0, "icbi", H_RA0_IS_0 },
+ 0, "icbi", H_RA0_IS_0 },
{ XO_OPCODE(31,491,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwo", 0 },
+ 0, "divwo", 0 },
{ XO_OPCODE(31,491,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwo.", 0 },
+ 0, "divwo.", 0 },
{ X_OPCODE(31,1010,0), X_MASK, {O_rB, 0},
- 0, "tlbli", 0 },
+ 0, "tlbli", 0 },
{ X_OPCODE(31,1014,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbz", H_RA0_IS_0 },
- { D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lwz", H_RA0_IS_0 },
- { D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lwzu", 0 },
- { D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lbz", H_RA0_IS_0 },
- { D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lbzu", 0 },
- { D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stw", H_RA0_IS_0 },
- { D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stwu", 0 },
- { D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stb", H_RA0_IS_0 },
- { D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stbu", 0 },
- { D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lhz", H_RA0_IS_0 },
- { D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lhzu", 0 },
- { D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lha", H_RA0_IS_0 },
- { D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lhau", 0 },
- { D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "sth", H_RA0_IS_0 },
- { D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "sthu", 0 },
- { D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lmw", H_RA0_IS_0 },
- { D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stmw", H_RA0_IS_0 },
+ 0, "dcbz", H_RA0_IS_0 },
+ { D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0},
+ 0, "lwz", H_RA0_IS_0 },
+ { D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0},
+ 0, "lwzu", 0 },
+ { D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0},
+ 0, "lbz", H_RA0_IS_0 },
+ { D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0},
+ 0, "lbzu", 0 },
+ { D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0},
+ 0, "stw", H_RA0_IS_0 },
+ { D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0},
+ 0, "stwu", 0 },
+ { D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0},
+ 0, "stb", H_RA0_IS_0 },
+ { D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0},
+ 0, "stbu", 0 },
+ { D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0},
+ 0, "lhz", H_RA0_IS_0 },
+ { D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0},
+ 0, "lhzu", 0 },
+ { D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0},
+ 0, "lha", H_RA0_IS_0 },
+ { D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0},
+ 0, "lhau", 0 },
+ { D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0},
+ 0, "sth", H_RA0_IS_0 },
+ { D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0},
+ 0, "sthu", 0 },
+ { D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0},
+ 0, "lmw", H_RA0_IS_0 },
+ { D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0},
+ 0, "stmw", H_RA0_IS_0 },
};
const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]);
diff --git a/include/clps7111.h b/include/clps7111.h
index d122d84..baf6007 100644
--- a/include/clps7111.h
+++ b/include/clps7111.h
@@ -231,7 +231,7 @@
#define IO_RTCDR IO_WORD(RTCDR)
#define IO_RTCMR IO_WORD(RTCMR)
#define IO_PMPCON IO_WORD(PMPCON)
-#define IO_CODR IO_BYTE(CODR)
+#define IO_CODR IO_BYTE(CODR)
#define IO_UARTDR IO_WORD(UARTDR)
#define IO_UBRLCR IO_WORD(UBRLCR)
#define IO_SYNCIO IO_WORD(SYNCIO)
diff --git a/include/command.h b/include/command.h
index 0597c10..c3ef51d 100644
--- a/include/command.h
+++ b/include/command.h
@@ -74,7 +74,7 @@ extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *
* void function (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
*/
-typedef void command_t (cmd_tbl_t *, int, int, char *[]);
+typedef void command_t (cmd_tbl_t *, int, int, char *[]);
#endif /* __ASSEMBLY__ */
diff --git a/include/common.h b/include/common.h
index d0f5704..26e1b46 100644
--- a/include/common.h
+++ b/include/common.h
@@ -176,6 +176,17 @@ typedef void (interrupt_handler_t)(void *);
(__x > __y) ? __x : __y; })
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @ptr: the pointer to the member.
+ * @type: the type of the container struct this is embedded in.
+ * @member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({ \
+ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
+ (type *)( (char *)__mptr - offsetof(type,member) );})
+
/*
* Function Prototypes
*/
diff --git a/include/commproc.h b/include/commproc.h
index 32a3e1c..0a4e817 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -786,19 +786,19 @@ typedef struct scc_enet {
#undef SCC_ENET
#define FEC_ENET
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
+#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
+#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
+#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
+#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
+#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
+#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
+#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
+#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
+#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
+#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
+#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
+#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
+#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */
#endif /* CONFIG_GEN860T */
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index d1b5ffb..c2bb094 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -16,13 +16,13 @@
#define CONFIG_CMD_AMBAPP /* AMBA Plug & Play Bus print utility */
#define CONFIG_CMD_ASKENV /* ask for env variable */
#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */
-#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BDI /* bdinfo */
#define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */
#define CONFIG_CMD_BMP /* BMP support */
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE /* icache, dcache */
-#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
+#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
#define CONFIG_CMD_DHCP /* DHCP Support */
@@ -71,7 +71,7 @@
#define CONFIG_CMD_SAVES /* save S record dump */
#define CONFIG_CMD_SCSI /* SCSI Support */
#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
-#define CONFIG_CMD_SETEXPR /* setexpr support */
+#define CONFIG_CMD_SETEXPR /* setexpr support */
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_CMD_SNTP /* SNTP support */
#define CONFIG_CMD_SPI /* SPI utility */
diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h
index f61cfc9..b556706 100644
--- a/include/config_cmd_default.h
+++ b/include/config_cmd_default.h
@@ -17,7 +17,7 @@
*/
#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */
-#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BDI /* bdinfo */
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
diff --git a/include/configs/A3000.h b/include/configs/A3000.h
index 0a9a1ff..dba1bf7 100644
--- a/include/configs/A3000.h
+++ b/include/configs/A3000.h
@@ -87,7 +87,7 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
@@ -95,9 +95,9 @@
* PCI stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CONFIG_NET_MULTI /* Multi ethernet cards support */
@@ -120,11 +120,11 @@
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
-#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM
+#define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */
+#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
+#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM
#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM }
/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
@@ -170,7 +170,7 @@
* Definitions for initial stack pointer and data area
*/
-/* #define CFG_MONITOR_BASE TEXT_BASE */
+/* #define CFG_MONITOR_BASE TEXT_BASE */
/*#define CFG_GBL_DATA_SIZE 256*/
#define CFG_GBL_DATA_SIZE 128
#define CFG_INIT_RAM_ADDR 0x40000000
@@ -192,7 +192,7 @@
*/
#define CFG_ROMNAL 7
#define CFG_ROMFAL 11
-#define CFG_DBUS_SIZE 0x3
+#define CFG_DBUS_SIZE 0x3
/* Bit-field values for MCCR2.
*/
@@ -218,7 +218,7 @@
#define CFG_EXTROM 1
#define CFG_REGDIMM 0
-#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
+#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h
index c45c395..01ee72b 100644
--- a/include/configs/ADNPESC1.h
+++ b/include/configs/ADNPESC1.h
@@ -81,9 +81,9 @@
* appropriately -- this is very important if you plan to move your
* memory to another place as configured at this time !!!).
*
- * -The heap is placed below the monitor.
- * -Global data is placed below the heap.
- * -The stack is placed below global data (&grows down).
+ * -The heap is placed below the monitor.
+ * -Global data is placed below the heap.
+ * -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
diff --git a/include/configs/ADNPESC1_base_32.h b/include/configs/ADNPESC1_base_32.h
index 55210eb..c8428b4 100644
--- a/include/configs/ADNPESC1_base_32.h
+++ b/include/configs/ADNPESC1_base_32.h
@@ -370,10 +370,10 @@
#define CFG_NIOS_CPU_IDE_NUMS 2 /* number of IDE contr. */
#define CFG_NIOS_CPU_IDE0 0x00001000 /* IDE0 addr */
-#define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */
+#define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */
#define CFG_NIOS_CPU_IDE1 0x00001020 /* IDE1 addr */
-#define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */
+#define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */
/* memory accessibility */
#undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */
diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h
index 6f64038..035ebc6 100644
--- a/include/configs/AMX860.h
+++ b/include/configs/AMX860.h
@@ -115,7 +115,7 @@
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
#define CFG_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */
-#define CFG_LOAD_ADDR 0x00100000
+#define CFG_LOAD_ADDR 0x00100000
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index 8ad33f1..02f0c76 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -36,7 +36,7 @@
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_APCG405 1 /* ...on a APC405 board */
+#define CONFIG_APCG405 1 /* ...on a APC405 board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_BOARD_EARLY_INIT_R 1
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index 50f09b0..0602381 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -208,7 +208,7 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR 0xFFFB0000 /* Address of Environment Sector*/
#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-#define CFG_ENV_SIZE 0x04000 /* Size of Environment */
+#define CFG_ENV_SIZE 0x04000 /* Size of Environment */
#define CFG_ENV_ADDR_REDUND 0xFFFA0000
#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index 0d644da..f05c1d5 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -55,7 +55,7 @@
#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/
#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_DDR_ECC /* only for ECC DDR module */
@@ -84,7 +84,7 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
+#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
#define CONFIG_ENABLE_36BIT_PHYS 1
#undef CFG_DRAM_TEST
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
@@ -276,7 +276,7 @@
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#if defined(CONFIG_PCI)
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index 8a76c26..7389c38 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -149,7 +149,7 @@
/* Environment is in flash */
#define CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CONFIG_ENV_OVERWRITE
@@ -191,16 +191,16 @@
#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE)
/* PISCR - Periodic Interrupt Status and Control */
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
/* PLPRCR - PLL, Low-Power, and Reset Control Register */
-/* #define CFG_PLPRCR PLPRCR_TEXPS */
+/* #define CFG_PLPRCR PLPRCR_TEXPS */
/* SCCR - System Clock and reset Control Register */
-#define SCCR_MASK SCCR_EBDF11
+#define SCCR_MASK SCCR_EBDF11
#define CFG_SCCR SCCR_RTSEL
-#define CFG_DER 0
+#define CFG_DER 0
/*-----------------------------------------------------------------------
* Cache Configuration
diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
index 3f2f614..38b962f 100644
--- a/include/configs/Alaska8220.h
+++ b/include/configs/Alaska8220.h
@@ -31,6 +31,8 @@
#define CONFIG_MPC8220 1
#define CONFIG_ALASKA8220 1 /* ... on Alaska board */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
determine the CPU speed. */
#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */
diff --git a/include/configs/B2.h b/include/configs/B2.h
index f1411db..d6ab1ad 100644
--- a/include/configs/B2.h
+++ b/include/configs/B2.h
@@ -37,7 +37,7 @@
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
#define CONFIG_B2 1 /* on an B2 Board */
#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
-#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
+#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index 706c13e..b7574bf 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -61,6 +61,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
diff --git a/include/configs/CCM.h b/include/configs/CCM.h
index 9f06957..6194c5c 100644
--- a/include/configs/CCM.h
+++ b/include/configs/CCM.h
@@ -137,7 +137,7 @@
#define CFG_LOAD_ADDR 0x00100000 /* default load address */
/* Ethernet hardware configuration done using port pins */
-#define CFG_PA_ETH_RESET 0x0200 /* PA 6 */
+#define CFG_PA_ETH_RESET 0x0200 /* PA 6 */
#define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */
#define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
#define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 48e29a2..89edbde 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -61,6 +61,8 @@
#undef CONFIG_ECC /* enable ECC support */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/* which initialization functions to call for this board */
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_PRE_INIT
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index 9763e64..10cebc9 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -115,9 +115,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
/*-----------------------------------------------------------------------
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
index 2356858..604779a 100644
--- a/include/configs/CRAYL1.h
+++ b/include/configs/CRAYL1.h
@@ -130,16 +130,16 @@
/*
* Miscellaneous configurable options
*/
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_LOAD_ADDR 0x100000/* where to load what we get from TFTP */
+#define CFG_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */
#define CFG_TFTP_LOADADDR CFG_LOAD_ADDR
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_DRAM_TEST 1
/*-----------------------------------------------------------------------
@@ -218,7 +218,7 @@
#else
#define CFG_OCM_DATA_ADDR 0xF0000000
#define CFG_OCM_DATA_SIZE 0x1000
-#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
index 8b50087..f36d8da 100644
--- a/include/configs/CU824.h
+++ b/include/configs/CU824.h
@@ -305,7 +305,7 @@
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP
-#define CONFIG_NET_MULTI /* Multi ethernet cards support */
+#define CONFIG_NET_MULTI /* Multi ethernet cards support */
#define CONFIG_TULIP
#define CONFIG_TULIP_USE_IO
diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h
index eb78080..fb06689 100644
--- a/include/configs/DK1C20.h
+++ b/include/configs/DK1C20.h
@@ -76,9 +76,9 @@
* a memory resource (so you must make sure TEXT_BASE is chosen
* appropriately).
*
- * -The heap is placed below the monitor.
- * -Global data is placed below the heap.
- * -The stack is placed below global data (&grows down).
+ * -The heap is placed below the monitor.
+ * -Global data is placed below the heap.
+ * -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h
index bd36071..7a9ef79 100644
--- a/include/configs/DK1S10.h
+++ b/include/configs/DK1S10.h
@@ -84,9 +84,9 @@
* a memory resource (so you must make sure TEXT_BASE is chosen
* appropriately).
*
- * -The heap is placed below the monitor.
- * -Global data is placed below the heap.
- * -The stack is placed below global data (&grows down).
+ * -The heap is placed below the monitor.
+ * -Global data is placed below the heap.
+ * -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h
index 4eb9629..0115699 100644
--- a/include/configs/DK1S10_mtx_ldk_20.h
+++ b/include/configs/DK1S10_mtx_ldk_20.h
@@ -147,7 +147,7 @@
/* IDE i/f */
#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */
#define CFG_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */
-#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */
+#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */
/* memory accessibility */
#undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index d54da97..0f5f85c 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -375,11 +375,11 @@ int du440_phy_addr(int devnum);
#define CFG_FLASH CFG_FLASH_BASE
#define CFG_CPLD_BASE 0xC0000000
-#define CFG_CPLD_RANGE 0x00000010
+#define CFG_CPLD_RANGE 0x00000010
#define CFG_DUMEM_BASE 0xC0100000
-#define CFG_DUMEM_RANGE 0x00100000
+#define CFG_DUMEM_RANGE 0x00100000
#define CFG_DUIO_BASE 0xC0200000
-#define CFG_DUIO_RANGE 0x00010000
+#define CFG_DUIO_RANGE 0x00010000
#define CFG_NAND0_CS 2 /* NAND chip connected to CSx */
#define CFG_NAND1_CS 3 /* NAND chip connected to CSx */
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index 5ba7585..417099e 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -95,7 +95,7 @@
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
@@ -157,7 +157,7 @@
*/
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -219,13 +219,13 @@
#define CFG_CS0_BASE CFG_FLASH_BASE
#define CFG_CS0_SIZE 2*1024*1024
#define CFG_CS0_WIDTH 16
-#define CFG_CS0_RO 0
+#define CFG_CS0_RO 0
#define CFG_CS0_WS 6
#define CFG_CS3_BASE 0xE0000000
#define CFG_CS3_SIZE 1*1024*1024
#define CFG_CS3_WIDTH 16
-#define CFG_CS3_RO 0
+#define CFG_CS3_RO 0
#define CFG_CS3_WS 6
/*-----------------------------------------------------------------------
@@ -250,7 +250,7 @@
#define CFG_PEHLPAR 0xC0
#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
#define CFG_DDRUA 0x05
-#define CFG_PJPAR 0xFF;
+#define CFG_PJPAR 0xFF;
/*-----------------------------------------------------------------------
* CCM configuration
diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h
index c2ab18a..7824b90 100644
--- a/include/configs/EP88x.h
+++ b/include/configs/EP88x.h
@@ -144,7 +144,7 @@
/* Environment is in flash */
#define CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_OR0_PRELIM 0xFC000160
@@ -192,13 +192,13 @@
#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE)
/* PISCR - Periodic Interrupt Status and Control */
-#define CFG_PISCR PISCR_PS
+#define CFG_PISCR PISCR_PS
/* SCCR - System Clock and reset Control Register */
-#define SCCR_MASK SCCR_EBDF11
+#define SCCR_MASK SCCR_EBDF11
#define CFG_SCCR SCCR_RTSEL
-#define CFG_DER 0
+#define CFG_DER 0
/*-----------------------------------------------------------------------
* Cache Configuration
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
index dc15b0c..bfdcf6a 100644
--- a/include/configs/ERIC.h
+++ b/include/configs/ERIC.h
@@ -330,7 +330,7 @@
* BR0/1 and OR0/1 (FLASH)
*/
-#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */
+#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h
index ed439b1..525051f 100644
--- a/include/configs/ETX094.h
+++ b/include/configs/ETX094.h
@@ -51,7 +51,7 @@
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */
-#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */
+#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */
#define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */
#define CONFIG_ETHADDR 08:00:06:00:00:00
diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h
index 1c44a0c..c9d8c27 100644
--- a/include/configs/EVB64260.h
+++ b/include/configs/EVB64260.h
@@ -42,7 +42,7 @@
#define CONFIG_EVB64260 1 /* this is an EVB64260 board */
#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */
-#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
+#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
#undef CONFIG_ECC /* enable ECC support */
/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
@@ -91,7 +91,7 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp && " \
+ "bootp && " \
"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:" \
"$netmask:$hostname:eth0:none; && " \
@@ -412,10 +412,10 @@
#define CFG_L2
#ifdef CONFIG_750CX
-#define L2_INIT 0
+#define L2_INIT 0
#else
-#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
- L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+ L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
#endif
#define L2_ENABLE (L2_INIT | L2CR_L2E)
diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h
index 251227c..99d1cf2 100644
--- a/include/configs/EXBITGEN.h
+++ b/include/configs/EXBITGEN.h
@@ -33,7 +33,7 @@
* (easy to change)
*/
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
+#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */
diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h
index 86cbe58..6f3e6a7 100644
--- a/include/configs/FADS823.h
+++ b/include/configs/FADS823.h
@@ -93,10 +93,10 @@
#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
#define CONFIG_BOOTARGS ""
#define CONFIG_BOOTCOMMAND \
-"bootp ;" \
-"setenv bootargs console=tty0 console=ttyS0 " \
-"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
-"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \
+"bootp ;" \
+"setenv bootargs console=tty0 console=ttyS0 " \
+"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
+"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \
"bootm"
#else
#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index c8b5a6d..037b115 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -39,9 +39,9 @@
* Identify the board
*/
#if !defined(CONFIG_SC)
-#define CONFIG_IDENT_STRING " B2"
+#define CONFIG_IDENT_STRING " B2"
#else
-#define CONFIG_IDENT_STRING " SC"
+#define CONFIG_IDENT_STRING " SC"
#endif
/*
@@ -50,26 +50,26 @@
* generated by the DS1337 - and the DS1337 clock can be turned off.
*/
#if !defined(CONFIG_SC)
-#define CONFIG_8xx_GCLK_FREQ 66600000
+#define CONFIG_8xx_GCLK_FREQ 66600000
#else
-#define CONFIG_8xx_GCLK_FREQ 48000000
+#define CONFIG_8xx_GCLK_FREQ 48000000
#endif
/*
* The RS-232 console port is on SMC1
*/
#define CONFIG_8xx_CONS_SMC1
-#define CONFIG_BAUDRATE 38400
+#define CONFIG_BAUDRATE 38400
/*
* Set allowable console baud rates
*/
-#define CFG_BAUDRATE_TABLE { 9600, \
- 19200, \
- 38400, \
- 57600, \
- 115200, \
- }
+#define CFG_BAUDRATE_TABLE { 9600, \
+ 19200, \
+ 38400, \
+ 57600, \
+ 115200, \
+ }
/*
* Print console information
@@ -148,7 +148,7 @@
#define CFG_DISCOVER_PHY
#define CONFIG_MII
#define CONFIG_MII_INIT 1
-#define CONFIG_PHY_ADDR 0
+#define CONFIG_PHY_ADDR 0
/*
* Set default IP stuff just to get bootstrap entries into the
@@ -172,7 +172,7 @@
* Enable I2C and select the hardware/software driver
*/
#define CONFIG_HARD_I2C 1 /* CPM based I2C */
-#undef CONFIG_SOFT_I2C /* Bit-banged I2C */
+#undef CONFIG_SOFT_I2C /* Bit-banged I2C */
#ifdef CONFIG_HARD_I2C
#define CFG_I2C_SPEED 100000 /* clock speed in Hz */
@@ -181,7 +181,7 @@
#ifdef CONFIG_SOFT_I2C
#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
+#define PB_SDA 0x00000010 /* PB 27 */
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
@@ -388,7 +388,7 @@
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
+#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -480,18 +480,18 @@
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR ( SYPCR_SWTC | \
- SYPCR_BMT | \
- SYPCR_BME | \
- SYPCR_SWF | \
- SYPCR_SWE | \
+ SYPCR_BMT | \
+ SYPCR_BME | \
+ SYPCR_SWF | \
+ SYPCR_SWE | \
SYPCR_SWRI | \
SYPCR_SWP \
)
#else
#define CFG_SYPCR ( SYPCR_SWTC | \
- SYPCR_BMT | \
- SYPCR_BME | \
- SYPCR_SWF | \
+ SYPCR_BMT | \
+ SYPCR_BME | \
+ SYPCR_SWF | \
SYPCR_SWP \
)
#endif
@@ -557,18 +557,18 @@
#define SCCR_MASK SCCR_EBDF11
#if !defined(CONFIG_SC)
-#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
- SCCR_COM00 | /* full strength CLKOUT */ \
- SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
- SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
+#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
+ SCCR_COM00 | /* full strength CLKOUT */ \
+ SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
+ SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
SCCR_DFNL000 | \
SCCR_DFNH000 \
)
#else
-#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
- SCCR_COM00 | /* full strength CLKOUT */ \
- SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
- SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
+#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
+ SCCR_COM00 | /* full strength CLKOUT */ \
+ SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
+ SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
SCCR_DFNL000 | \
SCCR_DFNH000 | \
SCCR_RTDIV | \
@@ -614,7 +614,7 @@
#define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \
BR_MS_GPCM | \
BR_PS_8 | \
- BR_V \
+ BR_V \
)
/*
@@ -626,9 +626,9 @@
)
#define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \
- BR_MS_UPMA | \
- BR_PS_32 | \
- BR_V \
+ BR_MS_UPMA | \
+ BR_PS_32 | \
+ BR_V \
)
/*
@@ -646,9 +646,9 @@
* MAMR settings for SDRAM
*/
#define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
- MAMR_PTAE | \
+ MAMR_PTAE | \
MAMR_AMA_TYPE_1 | \
- MAMR_DSA_1_CYCL | \
+ MAMR_DSA_1_CYCL | \
MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | \
MAMR_WLFA_1X | \
@@ -660,7 +660,7 @@
* 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
* no burst.
*/
-#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
+#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
OR_CSNT_SAM | \
OR_ACS_DIV2 | \
OR_BI | \
@@ -685,20 +685,20 @@
*/
#define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \
OR_SCY_15_CLK | \
- OR_BI \
+ OR_BI \
)
#define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \
BR_PS_32 | \
BR_MS_GPCM | \
- BR_V \
+ BR_V \
)
/*
* CS4* configuration for FPGA SelectMap configuration interface.
* 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
* of GCLK1_50
*/
-#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
+#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
OR_G5LS | \
OR_BI \
)
@@ -706,7 +706,7 @@
#define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \
BR_PS_8 | \
BR_MS_UPMB | \
- BR_V \
+ BR_V \
)
/*
@@ -728,7 +728,7 @@
#define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \
BR_PS_16 | \
BR_MS_GPCM | \
- BR_V \
+ BR_V \
)
/*
@@ -760,5 +760,3 @@
#endif
#endif /* __CONFIG_GEN860T_H */
-
-/* vim: set ts=4 tw=78 ai shiftwidth=4: */
diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h
index 3a660ed..f6d6ae0 100644
--- a/include/configs/GENIETV.h
+++ b/include/configs/GENIETV.h
@@ -80,10 +80,10 @@
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 9600
-#define MPC8XX_FACT 12 /* Multiply by 12 */
-#define MPC8XX_XIN 5000000 /* 4 MHz clock */
+#define MPC8XX_FACT 12 /* Multiply by 12 */
+#define MPC8XX_XIN 5000000 /* 4 MHz clock */
-#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
#define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << 20)
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
@@ -95,9 +95,9 @@
#define CONFIG_BOOTARGS ""
#define CONFIG_BOOTCOMMAND \
"bootp; tftp; " \
-"setenv bootargs console=tty0 console=ttyS0 " \
-"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
-"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \
+"setenv bootargs console=tty0 console=ttyS0 " \
+"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
+"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \
"bootm "
#else
#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
@@ -197,7 +197,7 @@
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
+#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/
/* values according to the manual */
@@ -291,15 +291,15 @@
#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
-#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask (512Kb) */
/* FLASH timing */
-#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
+#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
OR_SCY_15_CLK | OR_TRLX )
/*#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) */
-#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 0xfff80ff4 */
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 0xfff80ff4 */
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) /* 0x02800401 */
/*
diff --git a/include/configs/GTH.h b/include/configs/GTH.h
index 79f5714..00e09f7 100644
--- a/include/configs/GTH.h
+++ b/include/configs/GTH.h
@@ -135,7 +135,7 @@
#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
/* Default location to load data from net */
-#define CFG_LOAD_ADDR 0x100000
+#define CFG_LOAD_ADDR 0x100000
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
@@ -196,7 +196,7 @@
#define CFG_ENV_IS_IN_FLASH 1
#undef CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_OFFSET 0x000E0000
-#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x50000 /* see README - env sector total size */
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 18e5b3c..8ea1ac3 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -41,7 +41,7 @@
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_HH405 1 /* ...on a HH405 board */
+#define CONFIG_HH405 1 /* ...on a HH405 board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h
index 7f3f16d..87827ea 100644
--- a/include/configs/IAD210.h
+++ b/include/configs/IAD210.h
@@ -70,15 +70,15 @@
#undef CONFIG_BOOTARGS
/* #define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
+ "bootp;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+ "bootm"
*/
#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/nfs" \
- "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \
+ "setenv bootargs root=/dev/nfs" \
+ "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -159,7 +159,7 @@
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
-#define CFG_LOAD_ADDR 0x00100000
+#define CFG_LOAD_ADDR 0x00100000
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
index 9c88d7c..f693956 100644
--- a/include/configs/ICU862.h
+++ b/include/configs/ICU862.h
@@ -72,9 +72,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+ "bootp;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -164,7 +164,7 @@
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
-#define CFG_LOAD_ADDR 0x00100000
+#define CFG_LOAD_ADDR 0x00100000
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
index bb2c96a..7d564a0 100644
--- a/include/configs/IPHASE4539.h
+++ b/include/configs/IPHASE4539.h
@@ -274,7 +274,7 @@
* HID1 has only read-only information - nothing to set.
*/
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- HID0_IFEM|HID0_ABE)
+ HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
#define CFG_HID2 0
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
index 965b515..760f7cc 100644
--- a/include/configs/ISPAN.h
+++ b/include/configs/ISPAN.h
@@ -186,7 +186,7 @@
/* Environment is in flash, there is little space left in Serial EEPROM */
#define CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h
index 1142f2a..0ffdfac 100644
--- a/include/configs/IVML24.h
+++ b/include/configs/IVML24.h
@@ -205,7 +205,7 @@
# if defined (CONFIG_IVML24_16M)
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
# elif defined (CONFIG_IVML24_32M)
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWP)
@@ -265,7 +265,7 @@
/* 0x01800014 */
#define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \
SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
+ /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
SCCR_EBDF00 | SCCR_DFSYNC00 | \
SCCR_DFBRG00 | SCCR_DFNL000 | \
SCCR_DFNH000 | SCCR_DFLCD101 | \
@@ -458,8 +458,8 @@
#if defined (CONFIG_IVML24_16M)
/* 8 column SDRAM */
# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
+ MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
+ MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
#elif defined (CONFIG_IVML24_32M)
/* 128 MBit SDRAM */
# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
index bd19dad..ea3ffe0 100644
--- a/include/configs/IVMS8.h
+++ b/include/configs/IVMS8.h
@@ -200,7 +200,7 @@
#if defined(CONFIG_WATCHDOG)
# if defined (CONFIG_IVMS8_16M)
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
# elif defined (CONFIG_IVMS8_32M)
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWP)
@@ -259,7 +259,7 @@
/* 0x01800014 */
#define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \
SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
+ /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
SCCR_EBDF00 | SCCR_DFSYNC00 | \
SCCR_DFBRG00 | SCCR_DFNL000 | \
SCCR_DFNH000 | SCCR_DFLCD101 | \
@@ -440,8 +440,8 @@
#if defined (CONFIG_IVMS8_16M)
/* 8 column SDRAM */
# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
+ MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
+ MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
#elif defined (CONFIG_IVMS8_32M)
/* 128 MBit SDRAM */
#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 38a0226..3a347ea 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -37,6 +37,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
@@ -172,9 +174,9 @@
* IPB Bus clocking configuration.
*/
#if defined(CONFIG_LITE5200B)
-#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#else
-#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
#endif /* CONFIG_MPC5200 */
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 3ee2b39..8af1c52 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -84,7 +84,7 @@
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index e1cc720..a6fac4c 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -95,7 +95,7 @@
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 2b8734b..7edd322 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -97,7 +97,7 @@
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 826778c..df46ee4 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -82,7 +82,7 @@
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
@@ -215,13 +215,13 @@
#define CFG_CS0_BASE CFG_FLASH_BASE
#define CFG_CS0_SIZE 2*1024*1024
#define CFG_CS0_WIDTH 16
-#define CFG_CS0_RO 0
+#define CFG_CS0_RO 0
#define CFG_CS0_WS 6
/*
#define CFG_CS3_BASE 0xE0000000
#define CFG_CS3_SIZE 1*1024*1024
#define CFG_CS3_WIDTH 16
-#define CFG_CS3_RO 0
+#define CFG_CS3_RO 0
#define CFG_CS3_WS 6
*/
/*-----------------------------------------------------------------------
@@ -246,6 +246,6 @@
#define CFG_PEHLPAR 0xC0
#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
#define CFG_DDRUA 0x05
-#define CFG_PJPAR 0xFF;
+#define CFG_PJPAR 0xFF;
#endif /* _CONFIG_M5282EVB_H */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 42692d6..b30d99c 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -77,7 +77,7 @@
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 3b9da17..a710c6d 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -77,7 +77,7 @@
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index fea7551..a19c342 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -83,7 +83,7 @@
# define CFG_FEC1_PINMUX 0
# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 454d0a2..b73e2e0 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -83,7 +83,7 @@
# define CFG_FEC1_PINMUX 0
# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 9ddf82b..d683b87 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -123,7 +123,7 @@
* (to get SDRAM settings)
***************************************************************/
/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
-#define SDRAM_EEPROM_READ_ADDRESS 0xA1
+#define SDRAM_EEPROM_READ_ADDRESS 0xA1
*/
/**************************************************************
* Environment definitions
@@ -132,7 +132,7 @@
#define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
@@ -260,7 +260,7 @@
/*-----------------------------------------------------------------------
* Logbuffer Configuration
*/
-#undef CONFIG_LOGBUFFER /* supported but not enabled */
+#undef CONFIG_LOGBUFFER /* supported but not enabled */
/*-----------------------------------------------------------------------
* Bootcountlimit Configuration
*/
@@ -271,8 +271,8 @@
*/
#if 0 /* enable this if POST is desired (is supported but not enabled) */
#define CONFIG_POST (CFG_POST_MEMORY | \
- CFG_POST_CPU | \
- CFG_POST_RTC | \
+ CFG_POST_CPU | \
+ CFG_POST_RTC | \
CFG_POST_I2C)
#endif
@@ -292,7 +292,7 @@
#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
-#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
+#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
/*-----------------------------------------------------------------------
@@ -301,7 +301,7 @@
#define CFG_TEMP_STACK_OCM 1
#define CFG_OCM_DATA_ADDR 0xF0000000
#define CFG_OCM_DATA_SIZE 0x1000
-#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
@@ -362,7 +362,7 @@
#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
-#define CFG_ATA_REG_OFFSET 0 /* reg offset */
+#define CFG_ATA_REG_OFFSET 0 /* reg offset */
#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h
index 9370c24..021729b 100644
--- a/include/configs/MOUSSE.h
+++ b/include/configs/MOUSSE.h
@@ -265,18 +265,18 @@
#else
#define CFG_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
#endif
-#define CFG_DBAT1U CFG_IBAT1U
-#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT1L CFG_IBAT1L
/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
-#define CFG_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
+#define CFG_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
#define CFG_DBAT2U CFG_IBAT2U
#define CFG_DBAT2L CFG_IBAT2L
/* PCI Memory region 2: PCI Devices in 0xFD space */
-#define CFG_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
#define CFG_DBAT3U CFG_IBAT3U
#define CFG_DBAT3L CFG_IBAT3L
@@ -299,7 +299,7 @@
#if 0
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */
+#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Size of the Environment Sector */
#else
#define CFG_ENV_IS_IN_NVRAM 1
@@ -339,7 +339,7 @@
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP
-#define CONFIG_NET_MULTI /* Multi ethernet cards support */
+#define CONFIG_NET_MULTI /* Multi ethernet cards support */
#define CONFIG_TULIP
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 6eec240..d547681 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -42,9 +42,12 @@
/*
* On-board devices
+ *
+ * TSEC1 is VSC switch
+ * TSEC2 is SoC TSEC
*/
#define CONFIG_VSC7385_ENET
-
+#define CONFIG_TSEC2
#ifdef CFG_66MHZ
#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
@@ -80,7 +83,7 @@
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_TSEC2
+#define CONFIG_TSEC1
/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE 0xFE7FE000
@@ -209,12 +212,12 @@
/*
* Local Bus LCRR and LBCR regs
*/
-#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */
+#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4
#define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \
| (0xFF << LBCR_BMT_SHIFT) \
| 0xF ) /* 0x0004ff0f */
-#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
+#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
/* drivers/mtd/nand/nand.c */
#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */
@@ -466,6 +469,8 @@
#define CFG_HID2 HID2_HBE
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/* DDR @ 0x00000000 */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
@@ -523,13 +528,8 @@
*/
#define CONFIG_ENV_OVERWRITE
-#ifdef CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:95:01
-#endif
-
-#ifdef CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
-#endif
#define CONFIG_IPADDR 10.0.0.2
#define CONFIG_SERVERIP 10.0.0.1
@@ -551,28 +551,28 @@
#define MK_STR(x) XMK_STR(x)
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
"ethprime=TSEC1\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"fdtaddr=400000\0" \
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
"console=ttyS0\0" \
"setbootargs=setenv bootargs " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv rootdev /dev/nfs;" \
- "run setbootargs;" \
- "run setipargs;" \
+ "run setbootargs;" \
+ "run setipargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index e0a887c..7a5d0aa 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -453,6 +453,7 @@
/*
* MMU Setup
*/
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 32f57ac..977c041 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -468,6 +468,7 @@
/*
* MMU Setup
*/
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index ddefa5e..9ca2a2b 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -483,6 +483,8 @@
* MMU Setup
*/
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/* DDR: cache cacheable */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
@@ -574,7 +576,7 @@
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index cf552c2..bd77540 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -39,7 +39,7 @@
#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
#undef CONFIG_PCI
-#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
+#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
#define PCI_66M
#ifdef PCI_66M
@@ -414,7 +414,7 @@
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xFIXME
#define PCI_ENET0_MEMADDR 0xFIXME
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -626,6 +626,7 @@
#define CFG_HID2 HID2_HBE
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index be8850a..38410a1 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -149,8 +149,8 @@
* DDR Setup
*/
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CFG_SDRAM_BASE CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
#define CFG_83XX_DDR_USES_CS0
#define CFG_MEMTEST_START 0x1000 /* memtest region */
#define CFG_MEMTEST_END 0x2000
@@ -187,7 +187,7 @@
boards, we say we have two, but don't display a message if we find only one. */
#define CFG_FLASH_QUIET_TEST
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
-#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
#define CFG_FLASH_SIZE 16 /* FLASH size in MB */
#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
@@ -555,6 +555,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 HID2_HBE
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
@@ -671,21 +672,21 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_BOOTARGS \
"root=/dev/nfs rw" \
" nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
- " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
+ " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
" console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=" MK_STR(CONFIG_CONSOLE) "\0" \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "console=" MK_STR(CONFIG_CONSOLE) "\0" \
+ "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"fdtaddr=400000\0" \
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 983575e..fcfbe6f 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -515,6 +515,8 @@
* MMU Setup
*/
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/* DDR: cache cacheable */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index a4f6af6..adedcb9 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -419,6 +419,8 @@
* MMU Setup
*/
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/* DDR: cache cacheable */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
@@ -535,11 +537,11 @@
"ubootfile=u-boot.bin\0"\
"mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
"setbootargs=setenv bootargs console=$consoledev,$baudrate "\
- "$mtdparts panic=1\0"\
+ "$mtdparts panic=1\0"\
"adddhcpargs=setenv bootargs $bootargs ip=on\0"\
"addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
- "$gatewayip:$netmask:$hostname:$netdev:off "\
- "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
+ "$gatewayip:$netmask:$hostname:$netdev:off "\
+ "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
"addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
"rootfstype=jffs2 rw\0"\
"tftp_get_uboot=tftp 100000 $ubootfile\0"\
@@ -555,7 +557,7 @@
"nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
"nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
"nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
- "cp.b 100000 ff800000 $filesize\0"\
+ "cp.b 100000 ff800000 $filesize\0"\
"nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
"nand_write_kernel\0"\
"nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index e92493a..4e159a0 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -502,6 +502,7 @@
/*
* MMU Setup
*/
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CFG_SDRAM_LOWER CFG_SDRAM_BASE
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index f7e6fd2..29c2490 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -524,6 +524,8 @@
* MMU Setup
*/
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/* DDR: cache cacheable */
#define CFG_SDRAM_LOWER CFG_SDRAM_BASE
#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000)
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 85934d7..5719759 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -46,7 +46,7 @@
#endif
#define CONFIG_PCI
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
@@ -98,7 +98,7 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -147,7 +147,7 @@
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
@@ -268,16 +268,16 @@
#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -337,7 +337,7 @@
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -345,7 +345,7 @@
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -357,7 +357,7 @@
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 77eea73..b13c81c 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -30,14 +30,14 @@
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_MPC8540 1 /* MPC8540 specific */
#define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */
-#undef CONFIG_PCI /* pci ethernet support */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#undef CONFIG_PCI /* pci ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
@@ -63,7 +63,7 @@
#endif
/* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
#undef CONFIG_BTB /* toggle branch predition */
#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
@@ -81,8 +81,8 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
-#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -113,7 +113,7 @@
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
#define CFG_FLASH_CFI 1
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
@@ -150,16 +150,16 @@
#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -168,7 +168,7 @@
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
@@ -203,17 +203,17 @@
#define CONFIG_NET_MULTI
#undef CONFIG_EEPRO100
#define CONFIG_TULIP
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
-#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
+#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
#endif
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#define CFG_PCI_SUBSYS_DEVICEID 0x0008
#elif defined(CONFIG_TSEC_ENET)
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_HAS_ETH0
@@ -262,7 +262,7 @@
#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
-#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
+#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
@@ -318,7 +318,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Internal Definitions
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 3f3f741..5b3ea05 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -38,7 +38,7 @@
#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
#define CONFIG_PCI
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
@@ -69,7 +69,7 @@ extern unsigned long get_clock_freq(void);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
@@ -83,7 +83,7 @@ extern unsigned long get_clock_freq(void);
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -155,7 +155,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
@@ -284,16 +284,16 @@ extern unsigned long get_clock_freq(void);
#define CFG_OR3_PRELIM 0xfff00ff7
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 2
@@ -362,7 +362,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_MPC85XX_PCI2
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -376,7 +376,7 @@ extern unsigned long get_clock_freq(void);
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
@@ -455,7 +455,7 @@ extern unsigned long get_clock_freq(void);
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 500b57c..e838345 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -38,7 +38,7 @@
#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
#define CONFIG_PCI
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
@@ -69,7 +69,7 @@ extern unsigned long get_clock_freq(void);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
@@ -83,7 +83,7 @@ extern unsigned long get_clock_freq(void);
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -155,7 +155,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
@@ -284,16 +284,16 @@ extern unsigned long get_clock_freq(void);
#define CFG_OR3_PRELIM 0xfff00ff7
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 2
@@ -361,7 +361,7 @@ extern unsigned long get_clock_freq(void);
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_MPC85XX_PCI2
#undef CONFIG_EEPRO100
@@ -376,7 +376,7 @@ extern unsigned long get_clock_freq(void);
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
@@ -455,7 +455,7 @@ extern unsigned long get_clock_freq(void);
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index e30302c..9c95cc6 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -42,7 +42,7 @@
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
#define CONFIG_PCI
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
@@ -93,7 +93,7 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -142,7 +142,7 @@
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
@@ -263,23 +263,23 @@
#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
#undef CONFIG_CONS_NONE /* define if console on something else */
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
@@ -325,7 +325,7 @@
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -333,7 +333,7 @@
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -345,7 +345,7 @@
#ifdef CONFIG_TSEC_ENET
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#ifndef CONFIG_MII
@@ -367,9 +367,9 @@
#endif /* CONFIG_TSEC_ENET */
-#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
+#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
+#undef CONFIG_ETHER_NONE /* define if ether on something else */
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
#if (CONFIG_ETHER_INDEX == 2)
@@ -387,7 +387,7 @@
#elif (CONFIG_ETHER_INDEX == 3)
/* need more definitions here for FE3 */
#define FETH3_RST 0x80
-#endif /* CONFIG_ETHER_INDEX */
+#endif /* CONFIG_ETHER_INDEX */
#ifndef CONFIG_MII
#define CONFIG_MII 1 /* MII PHY management */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 7bb20e5..a7c69d2 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -38,7 +38,7 @@
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
@@ -68,7 +68,7 @@ extern unsigned long get_clock_freq(void);
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
@@ -88,7 +88,7 @@ extern unsigned long get_clock_freq(void);
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -166,7 +166,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
@@ -184,10 +184,10 @@ extern unsigned long get_clock_freq(void);
#define CFG_BR2_PRELIM 0xf0001861
#define CFG_OR2_PRELIM 0xfc006901
-#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
-#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
+#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
@@ -267,16 +267,16 @@ extern unsigned long get_clock_freq(void);
#define CFG_OR5_PRELIM 0xffff69f7
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -350,7 +350,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_eTSEC_MDIO_BUS
#ifdef CONFIG_eTSEC_MDIO_BUS
-#define CONFIG_MIIM_ADDRESS 0xE0024520
+#define CONFIG_MIIM_ADDRESS 0xE0024520
#endif
#define CONFIG_UEC_ETH1 /* GETH1 */
@@ -379,7 +379,7 @@ extern unsigned long get_clock_freq(void);
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -395,7 +395,7 @@ extern unsigned long get_clock_freq(void);
#endif /* CONFIG_PCI */
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#if defined(CONFIG_TSEC_ENET)
@@ -480,7 +480,7 @@ extern unsigned long get_clock_freq(void);
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index ed75357..fc16890 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -55,6 +55,7 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
#define CONFIG_ALTIVEC 1
/*
@@ -328,7 +329,7 @@
#define CONFIG_USB_KEYBOARD 1
#define CFG_DEVICE_DEREGISTER
#define CFG_USB_EVENT_POLL 1
-#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
+#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
#define CFG_OHCI_SWAP_REG_ACCESS 1
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index d7a7f90..455e154 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -36,11 +36,11 @@
#define CONFIG_MPC86xx 1 /* MPC86xx */
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
-#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
-#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
+#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#ifdef RUN_DIAG
-#define CFG_DIAG_ADDR 0xff800000
+#define CFG_DIAG_ADDR 0xff800000
#endif
#define CFG_RESET_ADDRESS 0xfff00100
@@ -51,7 +51,7 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
@@ -61,14 +61,15 @@
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_NUM_DDR_CONTROLLERS 2
-/* #define CONFIG_DDR_INTERLEAVE 1 */
+/* #define CONFIG_DDR_INTERLEAVE 1 */
#define CACHE_LINE_INTERLEAVING 0x20000000
#define PAGE_INTERLEAVING 0x21000000
#define BANK_INTERLEAVING 0x22000000
#define SUPER_BANK_INTERLEAVING 0x23000000
+#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
-#define CONFIG_ALTIVEC 1
+#define CONFIG_ALTIVEC 1
/*
* L2CR setup -- make sure this is right for your board!
@@ -81,7 +82,7 @@
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
#endif
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
@@ -93,7 +94,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -126,18 +127,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
#define CFG_DDR_CS0_BNDS 0x0000000F
- #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
+ #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
#define CFG_DDR_EXT_REFRESH 0x00000000
- #define CFG_DDR_TIMING_0 0x00260802
+ #define CFG_DDR_TIMING_0 0x00260802
#define CFG_DDR_TIMING_1 0x39357322
#define CFG_DDR_TIMING_2 0x14904cc8
#define CFG_DDR_MODE_1 0x00480432
#define CFG_DDR_MODE_2 0x00000000
#define CFG_DDR_INTERVAL 0x06090100
- #define CFG_DDR_DATA_INIT 0xdeadbeef
- #define CFG_DDR_CLK_CTRL 0x03800000
- #define CFG_DDR_OCD_CTRL 0x00000000
- #define CFG_DDR_OCD_STATUS 0x00000000
+ #define CFG_DDR_DATA_INIT 0xdeadbeef
+ #define CFG_DDR_CLK_CTRL 0x03800000
+ #define CFG_DDR_OCD_CTRL 0x00000000
+ #define CFG_DDR_OCD_STATUS 0x00000000
#define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
#define CFG_DDR_CONTROL2 0x04400000
@@ -169,7 +170,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
*
* Note that, on switching the boot location, fef00000 becomes fff00000.
*/
-#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */
+#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */
#define CFG_FLASH_BASE2 0xff800000
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
@@ -188,7 +189,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
+#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
@@ -203,7 +204,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
+#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
@@ -211,7 +212,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
@@ -220,7 +221,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
-#undef CFG_RAMBOOT
+#undef CFG_RAMBOOT
#endif
#if defined(CFG_RAMBOOT)
@@ -237,32 +238,32 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#else
#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
#endif
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
@@ -285,7 +286,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3100
/*
@@ -307,13 +308,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
/* PCI view of System Memory */
-#define CFG_PCI_MEMORY_BUS 0x00000000
-#define CFG_PCI_MEMORY_PHYS 0x00000000
-#define CFG_PCI_MEMORY_SIZE 0x80000000
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
/* For RTL8139 */
#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
-#define _IO_BASE 0x00000000
+#define _IO_BASE 0x00000000
#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
@@ -324,12 +325,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#if defined(CONFIG_PCI)
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#undef CFG_SCSI_SCAN_BUS_REVERSE
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_RTL8139
@@ -339,19 +340,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/************************************************************
* USB support
************************************************************/
-#define CONFIG_PCI_OHCI 1
+#define CONFIG_PCI_OHCI 1
#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_USB_KEYBOARD 1
+#define CONFIG_USB_KEYBOARD 1
#define CFG_DEVICE_DEREGISTER
-#define CFG_USB_EVENT_POLL 1
-#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
-#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#define CFG_USB_EVENT_POLL 1
+#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
#define CFG_OHCI_SWAP_REG_ACCESS 1
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
/*PCIE video card used*/
@@ -383,7 +384,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SATA_ULI5288
#define CFG_SCSI_MAX_SCSI_ID 4
#define CFG_SCSI_MAX_LUN 1
-#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
#endif
@@ -394,19 +395,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-#define CONFIG_TSEC4 1
-#define CONFIG_TSEC4_NAME "eTSEC4"
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+#define CONFIG_TSEC4 1
+#define CONFIG_TSEC4_NAME "eTSEC4"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
@@ -426,76 +427,76 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif /* CONFIG_TSEC_ENET */
/*
- * BAT0 2G Cacheable, non-guarded
- * 0x0000_0000 2G DDR
+ * BAT0 2G Cacheable, non-guarded
+ * 0x0000_0000 2G DDR
*/
-#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
-#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CFG_IBAT0U CFG_DBAT0U
+#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CFG_IBAT0U CFG_DBAT0U
/*
- * BAT1 1G Cache-inhibited, guarded
- * 0x8000_0000 512M PCI-Express 1 Memory
- * 0xa000_0000 512M PCI-Express 2 Memory
+ * BAT1 1G Cache-inhibited, guarded
+ * 0x8000_0000 512M PCI-Express 1 Memory
+ * 0xa000_0000 512M PCI-Express 2 Memory
* Changed it for operating from 0xd0000000
*/
-#define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
+#define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
#define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U CFG_DBAT1U
+#define CFG_IBAT1U CFG_DBAT1U
/*
- * BAT2 512M Cache-inhibited, guarded
- * 0xc000_0000 512M RapidIO Memory
+ * BAT2 512M Cache-inhibited, guarded
+ * 0xc000_0000 512M RapidIO Memory
*/
-#define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \
+#define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT2U (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
#define CFG_IBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U CFG_DBAT2U
+#define CFG_IBAT2U CFG_DBAT2U
/*
- * BAT3 4M Cache-inhibited, guarded
- * 0xf800_0000 4M CCSR
+ * BAT3 4M Cache-inhibited, guarded
+ * 0xf800_0000 4M CCSR
*/
-#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \
+#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U CFG_DBAT3U
+#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U CFG_DBAT3U
/*
- * BAT4 32M Cache-inhibited, guarded
- * 0xe200_0000 16M PCI-Express 1 I/O
- * 0xe300_0000 16M PCI-Express 2 I/0
+ * BAT4 32M Cache-inhibited, guarded
+ * 0xe200_0000 16M PCI-Express 1 I/O
+ * 0xe300_0000 16M PCI-Express 2 I/0
* Note that this is at 0xe0000000
*/
-#define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \
+#define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT4U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
#define CFG_IBAT4L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT4U CFG_DBAT4U
+#define CFG_IBAT4U CFG_DBAT4U
/*
- * BAT5 128K Cacheable, non-guarded
- * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
+ * BAT5 128K Cacheable, non-guarded
+ * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
*/
-#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_IBAT5L CFG_DBAT5L
-#define CFG_IBAT5U CFG_DBAT5U
+#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_IBAT5L CFG_DBAT5L
+#define CFG_IBAT5U CFG_DBAT5U
/*
- * BAT6 32M Cache-inhibited, guarded
- * 0xfe00_0000 32M FLASH
+ * BAT6 32M Cache-inhibited, guarded
+ * 0xfe00_0000 32M FLASH
*/
-#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
+#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U CFG_DBAT6U
+#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U CFG_DBAT6U
#define CFG_DBAT7L 0x00000000
#define CFG_DBAT7U 0x00000000
@@ -556,7 +557,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
@@ -597,7 +598,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR 00:E0:0C:00:00:01
+#define CONFIG_ETHADDR 00:E0:0C:00:00:01
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
@@ -623,45 +624,45 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_LOADADDR 1000000
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=mpc8641_hpcn.dtb\0" \
- "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
- "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
- "maxcpus=2"
-
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=mpc8641_hpcn.dtb\0" \
+ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+ "maxcpus=2"
+
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h
index 831cc5e..e0e8554 100644
--- a/include/configs/MPC86xADS.h
+++ b/include/configs/MPC86xADS.h
@@ -22,7 +22,7 @@
#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
/* CPU type - pick one of these */
-#define CONFIG_MPC866T 1
+#define CONFIG_MPC866T 1
#undef CONFIG_MPC866P
#undef CONFIG_MPC859T
#undef CONFIG_MPC859DSL
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
index f8cf01e..4319e6c 100644
--- a/include/configs/MUSENKI.h
+++ b/include/configs/MUSENKI.h
@@ -86,7 +86,7 @@
* PCI stuff
*-----------------------------------------------------------------------
*/
-#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP
#define CONFIG_NET_MULTI /* Multi ethernet cards support */
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
index d799f54..d08d795 100644
--- a/include/configs/MVBLUE.h
+++ b/include/configs/MVBLUE.h
@@ -28,16 +28,16 @@
#define MV_VERSION "v0.2.0"
/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
-#define ERR_NONE 0
-#define ERR_ENV 1
-#define ERR_BOOTM_BADMAGIC 2
-#define ERR_BOOTM_BADCRC 3
-#define ERR_BOOTM_GUNZIP 4
+#define ERR_NONE 0
+#define ERR_ENV 1
+#define ERR_BOOTM_BADMAGIC 2
+#define ERR_BOOTM_BADCRC 3
+#define ERR_BOOTM_GUNZIP 4
#define ERR_BOOTP_TIMEOUT 5
-#define ERR_DHCP 6
-#define ERR_TFTP 7
-#define ERR_NOLAN 8
-#define ERR_LANDRV 9
+#define ERR_DHCP 6
+#define ERR_TFTP 7
+#define ERR_NOLAN 8
+#define ERR_LANDRV 9
#define CONFIG_BOARD_TYPES 1
#define MVBLUE_BOARD_BOX 1
@@ -45,10 +45,10 @@
#if 0
#define ERR_LED(code) do { if (code) \
- *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
- else \
- *(volatile char *)(0xff000003) = ( 1 ); \
- } while(0)
+ *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
+ else \
+ *(volatile char *)(0xff000003) = ( 1 ); \
+} while(0)
#else
#define ERR_LED(code)
#endif
@@ -116,19 +116,19 @@
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS 16 /* Max number of command args */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS 16 /* Max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
-#define CONFIG_BOOTCOMMAND "run nfsboot"
+#define CONFIG_BOOTCOMMAND "run nfsboot"
#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2"
-#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm"
+#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \
@@ -156,11 +156,11 @@
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_NET_MULTI
-#define CONFIG_NET_RETRY_COUNT 5
+#define CONFIG_NET_RETRY_COUNT 5
#define CONFIG_TULIP
#define CONFIG_TULIP_FIX_DAVICOM 1
-#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0
+#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0
#define CONFIG_HW_WATCHDOG
@@ -224,7 +224,7 @@
*/
#define CONFIG_SYS_CLK_FREQ 33000000
-#define CFG_HZ 10000
+#define CFG_HZ 10000
/* Bit-field values for MCCR1. */
#define CFG_ROMNAL 7
diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h
index 75efd1e..87458e3 100644
--- a/include/configs/MVS1.h
+++ b/include/configs/MVS1.h
@@ -43,16 +43,19 @@
#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200 /* console baudrate */
+#define CONFIG_BAUDRATE 115200 /* console baudrate */
#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */
-#define CONFIG_PREBOOT "echo;echo To mount root over NFS use \"run bootnet\";echo To mount root from FLASH use \"run bootflash\";echo"
+#define CONFIG_PREBOOT "echo;" \
+ "echo To mount root over NFS use \"run bootnet\";" \
+ "echo To mount root from FLASH use \"run bootflash\";" \
+ "echo"
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
+#define CONFIG_BOOTCOMMAND \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
@@ -61,7 +64,7 @@
#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
+#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
/*
@@ -100,9 +103,9 @@
#undef CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#undef CFG_HUSH_PARSER /* Hush parse for U-Boot ?? */
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#undef CFG_HUSH_PARSER /* Hush parse for U-Boot ?? */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if defined(CONFIG_CMD_KGDB)
@@ -193,7 +196,7 @@
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
@@ -267,8 +270,8 @@
#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CFG_IDE_MAXBUS 0 /* max. no. of IDE buses */
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 5346545..0b09482 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -76,12 +76,12 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+ "bootp;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
-#define CONFIG_WATCHDOG /* watchdog enabled */
+#define CONFIG_WATCHDOG /* watchdog enabled */
#undef CONFIG_STATUS_LED /* Status LED disabled */
@@ -175,7 +175,7 @@
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
-#define CFG_LOAD_ADDR 0x00100000
+#define CFG_LOAD_ADDR 0x00100000
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index e3c6fd3..27e7ab9 100644
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -66,7 +66,7 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
+ "tftpboot; " \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
@@ -97,7 +97,7 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
+#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
#define FEC_ENET 1 /* eth.c needs it that way... */
#undef CFG_DISCOVER_PHY
#define CONFIG_MII 1
@@ -105,7 +105,7 @@
#define CONFIG_RMII 1 /* use RMII interface */
#define CONFIG_ETHER_ON_FEC1 1
-#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
+#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
#define CONFIG_FEC1_PHY_NORXERR 1
#define CONFIG_ETHER_ON_FEC2 1
@@ -292,27 +292,27 @@
#if MPC8XX_HZ == 120000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 100000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 50000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 25000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 40000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 75000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 10MHz
#endif
@@ -322,15 +322,15 @@
#if MPC8XX_HZ == 120000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 100000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 66666666
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 50MHz
#endif
@@ -514,7 +514,7 @@
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 20404a3..56c76d3 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -64,7 +64,7 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
+ "tftpboot; " \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
@@ -93,7 +93,7 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
+#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
#define FEC_ENET 1 /* eth.c needs it that way... */
#undef CFG_DISCOVER_PHY /* do not discover phys */
#define CONFIG_MII 1
@@ -102,15 +102,15 @@
#if defined(CONFIG_NETTA_ISDN)
#define CONFIG_ETHER_ON_FEC1 1
-#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */
+#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */
#define CONFIG_FEC1_PHY_NORXERR 1
#undef CONFIG_ETHER_ON_FEC2
#else
#define CONFIG_ETHER_ON_FEC1 1
-#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */
+#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */
#define CONFIG_FEC1_PHY_NORXERR 1
#define CONFIG_ETHER_ON_FEC2 1
-#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */
+#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */
#define CONFIG_FEC2_PHY_NORXERR 1
#endif
@@ -296,27 +296,27 @@
#if MPC8XX_HZ == 120000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 100000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 50000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 25000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 40000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 75000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 10MHz
#endif
@@ -326,19 +326,19 @@
#if MPC8XX_HZ == 120000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 100000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 80000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 50000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 50MHz
#endif
@@ -633,7 +633,7 @@
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index cf66e04..b8c4848 100644
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -66,9 +66,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "tftpboot; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_AUTOSCRIPT
@@ -98,7 +98,7 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
+#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
#define FEC_ENET 1 /* eth.c needs it that way... */
#undef CFG_DISCOVER_PHY
#define CONFIG_MII 1
@@ -106,7 +106,7 @@
#define CONFIG_RMII 1 /* use RMII interface */
#define CONFIG_ETHER_ON_FEC1 1
-#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
+#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
#define CONFIG_FEC1_PHY_NORXERR 1
#define CONFIG_ETHER_ON_FEC2 1
@@ -293,27 +293,27 @@
#if MPC8XX_HZ == 120000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 100000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 50000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 25000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 40000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 75000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 10MHz
#endif
@@ -323,15 +323,15 @@
#if MPC8XX_HZ == 120000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 100000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 66666666
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 50MHz
#endif
@@ -515,7 +515,7 @@
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index af5339e..1293fb0 100644
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -63,9 +63,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "tftpboot; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
@@ -411,7 +411,7 @@
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h
index 3929a84..11e5c63 100644
--- a/include/configs/NSCU.h
+++ b/include/configs/NSCU.h
@@ -295,8 +295,8 @@
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
-#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */
-#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */
+#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */
+#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */
#undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */
/*-----------------------------------------------------------------------
diff --git a/include/configs/NX823.h b/include/configs/NX823.h
index da1c173..2a4bd47 100644
--- a/include/configs/NX823.h
+++ b/include/configs/NX823.h
@@ -127,7 +127,7 @@
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x40000000
-#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
+#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
index e85e1b9..5a2d157 100644
--- a/include/configs/P3G4.h
+++ b/include/configs/P3G4.h
@@ -42,7 +42,7 @@
#define CONFIG_P3G4 1 /* this is a P3G4 board */
#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
#undef CONFIG_ECC /* enable ECC support */
/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
@@ -417,8 +417,8 @@
#define CFG_L2
-#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
- L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+ L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
#define L2_ENABLE (L2_INIT | L2CR_L2E)
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index 0de7591..4b37eca 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -32,7 +32,7 @@
*/
#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
-#define CONFIG_PATI 1 /* ...On a PATI board */
+#define CONFIG_PATI 1 /* ...On a PATI board */
/* Serial Console Configuration */
#define CONFIG_5xx_CONS_SCI1
#undef CONFIG_5xx_CONS_SCI2
@@ -74,11 +74,11 @@
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#define CONFIG_BOOTCOMMAND "" /* autoboot command */
+#define CONFIG_BOOTCOMMAND "" /* autoboot command */
#define CONFIG_BOOTARGS "" /* */
-#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
+#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
/*#define CONFIG_STATUS_LED 1 */ /* Enable status led */
@@ -123,30 +123,30 @@
/*
* Internal Memory Mapped (This is not the IMMR content)
*/
-#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */
+#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */
/*
* Definitions for initial stack pointer and data area
*/
-#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
-#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
-#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */
+#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
+#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
+#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
-#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */
+#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */
/*
* Start addresses for the final memory configuration
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
+#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
#define CFG_FLASH_BASE 0xffC00000 /* External flash */
#define PCI_BASE 0x03000000 /* PCI Base (CS2) */
#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */
#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
#define CFG_MONITOR_BASE 0xFFF00000
-/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */
- /* This adress is given to the linker with -Ttext to */
- /* locate the text section at this adress. */
+/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */
+ /* This adress is given to the linker with -Ttext to */
+ /* locate the text section at this adress. */
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
@@ -167,9 +167,9 @@
*/
#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */
-#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
+#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_EEPROM
@@ -180,8 +180,8 @@
#undef CFG_ENV_IS_IN_FLASH
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */
-#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */
+#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */
+#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */
#endif
@@ -233,7 +233,7 @@
*-----------------------------------------------------------------------
* Data show cycle
*/
-#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register
@@ -241,7 +241,7 @@
* Set all bits to 40 Mhz
*
*/
-#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
+#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
@@ -251,12 +251,12 @@
*-----------------------------------------------------------------------
*
*/
-#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
+#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
/*-----------------------------------------------------------------------
* ICTRL - I-Bus Support Control Register
*/
-#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
+#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
/*-----------------------------------------------------------------------
* USIU - Memory Controller Register
diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h
index 24b25d9..abb9bfc 100644
--- a/include/configs/PCI5441.h
+++ b/include/configs/PCI5441.h
@@ -54,10 +54,10 @@
/*------------------------------------------------------------------------
* MEMORY ORGANIZATION
- * -Monitor at top.
- * -The heap is placed below the monitor.
- * -Global data is placed below the heap.
- * -The stack is placed below global data (&grows down).
+ * -Monitor at top.
+ * -The heap is placed below the monitor.
+ * -Global data is placed below the heap.
+ * -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */
#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
@@ -87,7 +87,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
-#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN)
+#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN)
/*------------------------------------------------------------------------
* CONSOLE
@@ -155,8 +155,8 @@
#define CFG_LONGHELP /* Provide extended help*/
#define CFG_PROMPT "==> " /* Command prompt */
#define CFG_CBSIZE 256 /* Console I/O buf size */
-#define CFG_MAXARGS 16 /* Max command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */
+#define CFG_MAXARGS 16 /* Max command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */
#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index b83520d..5890012 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -123,7 +123,7 @@
#define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
@@ -252,7 +252,7 @@
#define CFG_TEMP_STACK_OCM 1
#define CFG_OCM_DATA_ADDR 0xF0000000
#define CFG_OCM_DATA_SIZE 0x1000
-#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index ad480a6..259178f 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -40,6 +40,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
@@ -159,7 +161,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index cf7314d..36e9aa5 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -47,9 +47,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
/* enable I2C and select the hardware/software driver */
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 38a26dc..9355aaf 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -43,7 +43,7 @@
#define CONFIG_PM856 1 /* PM856 board specific */
#define CONFIG_PCI
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_ECC /* only for ECC DDR module */
@@ -92,7 +92,7 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -141,7 +141,7 @@
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
@@ -167,16 +167,16 @@
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
@@ -236,7 +236,7 @@
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -244,7 +244,7 @@
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -256,7 +256,7 @@
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
diff --git a/include/configs/PN62.h b/include/configs/PN62.h
index 72acf5a..da7d8b8 100644
--- a/include/configs/PN62.h
+++ b/include/configs/PN62.h
@@ -73,7 +73,7 @@
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_SERVERIP 10.0.0.201
-#define CONFIG_IPADDR 10.0.0.200
+#define CONFIG_IPADDR 10.0.0.200
#define CONFIG_ROOTPATH /opt/eldk/ppc_82xx
#define CONFIG_NETMASK 255.255.255.0
#undef CONFIG_BOOTARGS
@@ -81,7 +81,7 @@
/* Boot Linux with NFS root filesystem */
#define CONFIG_BOOTCOMMAND \
"setenv verify y;" \
- "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
+ "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
"loadp 100000; bootm"
@@ -90,7 +90,7 @@
/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
#define CONFIG_BOOTCOMMAND \
"setenv verify n;" \
- "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
+ "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
"root=/dev/ram rw " \
"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
"loadp 200000; bootm"
@@ -128,7 +128,7 @@
/*
* Networking stuff
*/
-#define CONFIG_NET_MULTI /* Multi ethernet cards support */
+#define CONFIG_NET_MULTI /* Multi ethernet cards support */
#define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */
#define CONFIG_PCNET_79C973
@@ -153,9 +153,9 @@
/*#define CFG_GBL_DATA_SIZE 256*/
#define CFG_GBL_DATA_SIZE 128
-#define CFG_INIT_RAM_ADDR 0x40000000
-#define CFG_INIT_RAM_END 0x1000
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_END 0x1000
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_NO_FLASH 1 /* There is no FLASH memory */
diff --git a/include/configs/QS823.h b/include/configs/QS823.h
index 3dd84e8..cef9f42 100644
--- a/include/configs/QS823.h
+++ b/include/configs/QS823.h
@@ -492,12 +492,12 @@
/* For boards with 16M of SDRAM */
#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
-#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
+#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* For boards with 32M of SDRAM */
#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */
-#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
+#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
diff --git a/include/configs/QS850.h b/include/configs/QS850.h
index 7dd6eca..ba5827a 100644
--- a/include/configs/QS850.h
+++ b/include/configs/QS850.h
@@ -492,12 +492,12 @@
/* For boards with 16M of SDRAM */
#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
-#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
+#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* For boards with 32M of SDRAM */
#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */
-#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
+#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h
index f4aecfc..a653cca 100644
--- a/include/configs/R360MPI.h
+++ b/include/configs/R360MPI.h
@@ -62,9 +62,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#undef CONFIG_SCC1_ENET
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index e3c7561..9222d21 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -65,9 +65,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h
index 793b1db..706e2aa 100644
--- a/include/configs/RPXClassic.h
+++ b/include/configs/RPXClassic.h
@@ -78,9 +78,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "tftpboot; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@@ -467,7 +467,7 @@
#define BCSR3 0xFA400003
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
-#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
+#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h
index 3c5e6b8..671094b 100644
--- a/include/configs/RPXlite.h
+++ b/include/configs/RPXlite.h
@@ -51,9 +51,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@@ -156,7 +156,7 @@
#define CFG_DIRECT_FLASH_TFTP
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
+#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CONFIG_ENV_OVERWRITE
@@ -361,7 +361,7 @@
#define BCSR3 0xFA400003
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
-#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
+#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
index 32e2285..6a71801 100644
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -119,7 +119,7 @@
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_SOFT_I2C /* I2C bit-banged */
# define CFG_I2C_SPEED 50000 /* 50 kHz is supposed to work */
# define CFG_I2C_SLAVE 0xFE
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index 428c0c2..01ebc8f 100644
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -250,13 +250,13 @@
/* Hard reset configuration word */
#define CFG_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */
/* No slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 946b3c2..ff64378 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -48,7 +48,7 @@
#define CONFIG_CPM2 1 /* has CPM2 */
-#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
+#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
diff --git a/include/configs/SCM.h b/include/configs/SCM.h
index bc5389f..febfc39 100644
--- a/include/configs/SCM.h
+++ b/include/configs/SCM.h
@@ -67,9 +67,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
/* enable I2C and select the hardware/software driver */
@@ -165,7 +165,7 @@
* - Enable Full Duplex in FSMR
*/
# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
# define CFG_CPMFCR_RAMTYPE 0
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h
index 4d9d41b..31853c8 100644
--- a/include/configs/SL8245.h
+++ b/include/configs/SL8245.h
@@ -90,10 +90,10 @@
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */
-#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM
+#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM
#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM }
#define CFG_RESET_ADDRESS 0xFFF00100
diff --git a/include/configs/SM850.h b/include/configs/SM850.h
index 41a54f0..465db47 100644
--- a/include/configs/SM850.h
+++ b/include/configs/SM850.h
@@ -54,9 +54,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index 8f2a5ec..3aee45c 100644
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -204,7 +204,7 @@
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
@@ -250,7 +250,7 @@
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
-#define CFG_LOAD_ADDR 0x00100000
+#define CFG_LOAD_ADDR 0x00100000
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index 6cb3022..d21783b 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -42,6 +42,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index 1affcfd..4c44735 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -50,6 +50,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
@@ -176,7 +178,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h
index 8237ba1..151c407 100644
--- a/include/configs/TOP860.h
+++ b/include/configs/TOP860.h
@@ -201,10 +201,10 @@
* defines we need to get FEC running
*/
#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
-#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */
-#define FEC_ENET 1 /* eth.c needs it that way... */
+#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */
+#define FEC_ENET 1 /* eth.c needs it that way... */
#define CFG_DISCOVER_PHY 1
-#define CONFIG_MII 1
+#define CONFIG_MII 1
#define CONFIG_MII_INIT 1
#define CONFIG_PHY_ADDR 31
@@ -287,7 +287,7 @@
*-----------------------------------------------------------------------
* set up SYPCR:
* 16 SWTC 0xffff Software watchdog timer count
- * 8 BMT 0xff Bus monitor timing
+ * 8 BMT 0xff Bus monitor timing
* 1 BME 1 Bus monitor enable
* 3 0 000
* 1 SWF 1 Software watchdog freeze
@@ -297,7 +297,7 @@
*/
#if defined (CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
#endif
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index bff2edf..bfb478a 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -47,6 +47,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 02a16ac..89fc465 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -176,7 +176,7 @@ extern int tqm834x_num_flash_banks;
#define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
-#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -231,7 +231,7 @@ extern int tqm834x_num_flash_banks;
/*
* TSEC
*/
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_MII
#define CFG_TSEC1_OFFSET 0x24000
@@ -423,6 +423,8 @@ extern int tqm834x_num_flash_banks;
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 HID2_HBE
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/* DDR 0 - 512M */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index 2507d77..598fe7b 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -48,6 +48,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
@@ -178,7 +180,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index df6894f..ad8db61 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -44,7 +44,7 @@
#define USE_920T_MMU 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
@@ -84,8 +84,8 @@
* address 0x50 with 16bit addressing
***********************************************************/
#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CFG_I2C_SPEED 100000 /* I2C speed */
-#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */
+#define CFG_I2C_SPEED 100000 /* I2C speed */
+#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */
#define CFG_I2C_EEPROM_ADDR 0x50
#define CFG_I2C_EEPROM_ADDR_LEN 2
@@ -111,7 +111,7 @@
*/
#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
#define CS8900_BASE 0x20000300
-#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */
@@ -145,7 +145,7 @@
#define CONFIG_BOOTDELAY 5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.0.0.110
@@ -262,7 +262,7 @@
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h
index 1405784..db05d82 100644
--- a/include/configs/VoVPN-GW.h
+++ b/include/configs/VoVPN-GW.h
@@ -369,7 +369,7 @@
/*
* MEMORY MAP
* ----------
- * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored)
+ * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored)
* CS1 - SDRAM 32MB/64Bit base=0x00000000
* CS2 - DSP/SL1 1MB/16Bit base=0xf0100000
* CS3 - DSP/SL2 1MB/16Bit base=0xf0200000
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index 7017fff..bb6b6b9 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -154,10 +154,10 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
-#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
-#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* Set up values for external bus controller
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index bfb3156..3050caf 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -161,10 +161,10 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
-#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
-#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* Set up values for external bus controller
diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h
index 00c4ff0..1b4195a 100644
--- a/include/configs/Yukon8220.h
+++ b/include/configs/Yukon8220.h
@@ -31,6 +31,8 @@
#define CONFIG_MPC8220 1
#define CONFIG_YUKON8220 1 /* ... on Yukon board */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
determine the CPU speed. */
#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index 7c1a5b9..b04be76 100644
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -200,13 +200,13 @@
HRCW_MODCK_H0111 \
) /* 0x16848207 */
/* No slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 81e7c1e..4226529 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -45,14 +45,25 @@
*/
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC512X 1 /* MPC512X family */
+#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
+
+/* video */
+#undef CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
/* CONFIG_PCI is defined at config time */
#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
#define CFG_IMMR 0x80000000
+#define CFG_DIU_ADDR (CFG_IMMR+0x2100)
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
@@ -127,28 +138,28 @@
#define CFG_MICRON_OCD_DEFAULT 0x01010780
/* DDR Priority Manager Configuration */
-#define CFG_MDDRCGRP_PM_CFG1 0x000777AA
-#define CFG_MDDRCGRP_PM_CFG2 0x00000055
-#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000
-#define CFG_MDDRCGRP_LUT0_MU 0x11111117
-#define CFG_MDDRCGRP_LUT0_ML 0x7777777A
-#define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE
-#define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE
-#define CFG_MDDRCGRP_LUT2_MU 0x44444444
+#define CFG_MDDRCGRP_PM_CFG1 0x00077777
+#define CFG_MDDRCGRP_PM_CFG2 0x00000000
+#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000001
+#define CFG_MDDRCGRP_LUT0_MU 0xFFEEDDCC
+#define CFG_MDDRCGRP_LUT0_ML 0xBBAAAAAA
+#define CFG_MDDRCGRP_LUT1_MU 0x66666666
+#define CFG_MDDRCGRP_LUT1_ML 0x55555555
+#define CFG_MDDRCGRP_LUT2_MU 0x44444444
#define CFG_MDDRCGRP_LUT2_ML 0x44444444
-#define CFG_MDDRCGRP_LUT3_MU 0x55555555
+#define CFG_MDDRCGRP_LUT3_MU 0x55555555
#define CFG_MDDRCGRP_LUT3_ML 0x55555558
-#define CFG_MDDRCGRP_LUT4_MU 0x11111111
-#define CFG_MDDRCGRP_LUT4_ML 0x1111117C
-#define CFG_MDDRCGRP_LUT0_AU 0x33333377
-#define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE
-#define CFG_MDDRCGRP_LUT1_AU 0x11111111
-#define CFG_MDDRCGRP_LUT1_AL 0x11111111
-#define CFG_MDDRCGRP_LUT2_AU 0x11111111
+#define CFG_MDDRCGRP_LUT4_MU 0x11111111
+#define CFG_MDDRCGRP_LUT4_ML 0x11111122
+#define CFG_MDDRCGRP_LUT0_AU 0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT0_AL 0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT1_AU 0x66666666
+#define CFG_MDDRCGRP_LUT1_AL 0x66666666
+#define CFG_MDDRCGRP_LUT2_AU 0x11111111
#define CFG_MDDRCGRP_LUT2_AL 0x11111111
-#define CFG_MDDRCGRP_LUT3_AU 0x11111111
+#define CFG_MDDRCGRP_LUT3_AU 0x11111111
#define CFG_MDDRCGRP_LUT3_AL 0x11111111
-#define CFG_MDDRCGRP_LUT4_AU 0x11111111
+#define CFG_MDDRCGRP_LUT4_AU 0x11111111
#define CFG_MDDRCGRP_LUT4_AL 0x11111111
/*
@@ -161,7 +172,7 @@
#define CFG_FLASH_USE_BUFFER_WRITE
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
-#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
#undef CFG_FLASH_CHECKSUM
@@ -189,7 +200,11 @@
#define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+#ifdef CONFIG_FSL_DIU_FB
+#define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
+#else
+#define CFG_MALLOC_LEN (512 * 1024)
+#endif
/*
* Serial Port
@@ -357,6 +372,8 @@
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
#define CFG_HID2 HID2_HBE
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Internal Definitions
*
diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h
index 703d312..427b548 100644
--- a/include/configs/adsvix.h
+++ b/include/configs/adsvix.h
@@ -359,7 +359,7 @@
/* Flash environment locations */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */
-#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */
+#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
#endif /* __CONFIG_H */
diff --git a/include/configs/aev.h b/include/configs/aev.h
index e3f810c..c5e4759 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -41,6 +41,8 @@
#define CONFIG_AEVFIFO 1
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
index 294cd26..8973296 100755..100644
--- a/include/configs/apollon.h
+++ b/include/configs/apollon.h
@@ -174,7 +174,7 @@
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
+#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h
index 73a8885..98a83db 100644
--- a/include/configs/armadillo.h
+++ b/include/configs/armadillo.h
@@ -41,9 +41,9 @@
* (easy to change)
*/
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
-#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */
+#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */
#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
-#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
+#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
#undef CONFIG_USE_IRQ /* don't need them anymore */
@@ -88,7 +88,7 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200"
+#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200"
#define CONFIG_BOOTCOMMAND "bootm 40000 180000"
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index c891fa8..342ce2a 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -28,6 +28,7 @@
#define __CONFIG_H
/* ARM asynchronous clock */
+#define AT91_CPU_NAME "AT91CAP9"
#define AT91_MAIN_CLOCK 200000000 /* from 12 MHz crystal */
#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */
#define CFG_HZ 1000000 /* 1us resolution */
@@ -55,11 +56,19 @@
#undef CONFIG_USART2
#define CONFIG_USART3 1 /* USART 3 is DBGU */
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
- "root=/dev/mtdblock1 rw rootfstype=jffs2"
+/* LCD */
+#define CONFIG_LCD 1
+#define LCD_BPP LCD_COLOR8
+#define CONFIG_LCD_LOGO 1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO 1
+#define CONFIG_LCD_INFO_BELOW_LOGO 1
+#define CFG_WHITE_ON_BLACK 1
+#define CONFIG_ATMEL_LCD 1
+#define CONFIG_ATMEL_LCD_BGR555 1
+#define CFG_CONSOLE_IS_IN_ENV 1
-/* #define CONFIG_ENV_OVERWRITE 1 */
+#define CONFIG_BOOTDELAY 3
/*
* BOOTP options
@@ -94,9 +103,9 @@
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 1
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
-#define AT91_SPI_CLK 20000000
-#define DATAFLASH_TCSS (0xFA << 16)
-#define DATAFLASH_TCHS (0x8 << 24)
+#define AT91_SPI_CLK 15000000
+#define DATAFLASH_TCSS (0x1a << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
/* NOR flash */
#define CFG_FLASH_CFI 1
@@ -110,6 +119,7 @@
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
#define CFG_NAND_BASE 0x40000000
+#define CFG_NAND_DBW_8 1
/* Ethernet */
#define CONFIG_MACB 1
@@ -143,7 +153,12 @@
#define CFG_ENV_OFFSET 0x4200
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4200
-#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x72000000 0x200040; bootm"
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock1 " \
+ "mtdparts=physmap-flash.0:-(nor);" \
+ "at91_nand:-(root) " \
+ "rw rootfstype=jffs2"
#else
@@ -154,6 +169,12 @@
#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4000
#define CONFIG_BOOTCOMMAND "cp.b 0x10040000 0x72000000 0x200000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock4 " \
+ "mtdparts=physmap-flash.0:16k(bootstrap)ro,"\
+ "16k(env),224k(uboot)ro,-(linux);" \
+ "at91_nand:-(root) " \
+ "rw rootfstype=jffs2"
#endif
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 41c418f..675224e 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -56,10 +56,6 @@
#define CONFIG_USART3 1 /* USART 3 is DBGU */
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
- "root=/dev/mtdblock0 rw rootfstype=jffs2"
-
-/* #define CONFIG_ENV_OVERWRITE 1 */
/*
* BOOTP options
@@ -96,7 +92,7 @@
#define CFG_MAX_DATAFLASH_BANKS 2
#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
#define CFG_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */
-#define AT91_SPI_CLK 33000000
+#define AT91_SPI_CLK 15000000
#define DATAFLASH_TCSS (0x1a << 16)
#define DATAFLASH_TCHS (0x1 << 24)
@@ -104,6 +100,7 @@
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1
#define CFG_NAND_BASE 0x40000000
+#define CFG_NAND_DBW_8 1
/* NOR flash - no real flash on this board */
#define CFG_NO_FLASH 1
@@ -142,7 +139,11 @@
#define CFG_ENV_OFFSET 0x4200
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4200
-#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x22000000 0x200040; bootm"
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock0 " \
+ "mtdparts=at91_nand:-(root) " \
+ "rw rootfstype=jffs2"
#elif CFG_USE_DATAFLASH_CS1
@@ -152,7 +153,11 @@
#define CFG_ENV_OFFSET 0x4200
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE 0x4200
-#define CONFIG_BOOTCOMMAND "cp.b 0xD003DE00 0x22000000 0x200040; bootm"
+#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock0 " \
+ "mtdparts=at91_nand:-(root) " \
+ "rw rootfstype=jffs2"
#else /* CFG_USE_NANDFLASH */
@@ -162,6 +167,12 @@
#define CFG_ENV_OFFSET_REDUND 0x80000
#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock5 " \
+ "mtdparts=at91_nand:128k(bootstrap)ro," \
+ "256k(uboot)ro,128k(env1)ro," \
+ "128k(env2)ro,2M(linux),-(root) " \
+ "rw rootfstype=jffs2"
#endif
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
new file mode 100644
index 0000000..e53a23f
--- /dev/null
+++ b/include/configs/at91sam9261ek.h
@@ -0,0 +1,202 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9261EK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_CPU_NAME "AT91SAM9261"
+#define AT91_MAIN_CLOCK 198656000 /* from 18.432 MHz crystal */
+#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */
+#define CFG_HZ 1000000 /* 1us resolution */
+
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/
+#define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+/* LCD */
+#define CONFIG_LCD 1
+#define LCD_BPP LCD_COLOR8
+#define CONFIG_LCD_LOGO 1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO 1
+#define CONFIG_LCD_INFO_BELOW_LOGO 1
+#define CFG_WHITE_ON_BLACK 1
+#define CONFIG_ATMEL_LCD 1
+#define CONFIG_ATMEL_LCD_BGR555 1
+#define CFG_CONSOLE_IS_IN_ENV 1
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_USB 1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+/* DataFlash */
+#define CONFIG_HAS_DATAFLASH 1
+#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS 2
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
+#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
+#define AT91_SPI_CLK 15000000
+#define DATAFLASH_TCSS (0x1a << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
+/* NAND flash */
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1
+#define CFG_NAND_BASE 0x40000000
+#define CFG_NAND_DBW_8 1
+
+/* NOR flash - no real flash on this board */
+#define CFG_NO_FLASH 1
+
+/* Ethernet */
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x30000000
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R 1
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW 1
+#define LITTLEENDIAN 1
+#define CONFIG_DOS_PARTITION 1
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
+#define CFG_USB_OHCI_SLOT_NAME "at91sam9261"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE 1
+
+#define CFG_LOAD_ADDR 0x22000000 /* load address */
+
+#define CFG_MEMTEST_START PHYS_SDRAM
+#define CFG_MEMTEST_END 0x23e00000
+
+#define CFG_USE_DATAFLASH_CS0 1
+#undef CFG_USE_NANDFLASH
+
+#ifdef CFG_USE_DATAFLASH_CS0
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CFG_ENV_IS_IN_DATAFLASH 1
+#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CFG_ENV_OFFSET 0x4200
+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x4200
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock0 " \
+ "mtdparts=at91_nand:-(root) " \
+ "rw rootfstype=jffs2"
+
+#else /* CFG_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CFG_ENV_IS_IN_NAND 1
+#define CFG_ENV_OFFSET 0x60000
+#define CFG_ENV_OFFSET_REDUND 0x80000
+#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock5 " \
+ "mtdparts=at91_nand:128k(bootstrap)ro," \
+ "256k(uboot)ro,128k(env1)ro," \
+ "128k(env2)ro,2M(linux),-(root) " \
+ "rw rootfstype=jffs2"
+
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT "U-Boot> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+
+#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
+#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
new file mode 100644
index 0000000..a8194b5
--- /dev/null
+++ b/include/configs/at91sam9263ek.h
@@ -0,0 +1,206 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9263EK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_CPU_NAME "AT91SAM9263"
+#define AT91_MAIN_CLOCK 199919000 /* from 16.367 MHz crystal */
+#define AT91_MASTER_CLOCK 99959500 /* peripheral = main / 2 */
+#define CFG_HZ 1000000 /* 1us resolution */
+
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
+#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+/* LCD */
+#define CONFIG_LCD 1
+#define LCD_BPP LCD_COLOR8
+#define CONFIG_LCD_LOGO 1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO 1
+#define CONFIG_LCD_INFO_BELOW_LOGO 1
+#define CFG_WHITE_ON_BLACK 1
+#define CONFIG_ATMEL_LCD 1
+#define CONFIG_ATMEL_LCD_BGR555 1
+#define CFG_CONSOLE_IS_IN_ENV 1
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_USB 1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+/* DataFlash */
+#define CONFIG_HAS_DATAFLASH 1
+#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS 1
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
+#define AT91_SPI_CLK 15000000
+#define DATAFLASH_TCSS (0x1a << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
+/* NOR flash, if populated */
+#if 1
+#define CFG_NO_FLASH 1
+#else
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#define PHYS_FLASH_1 0x10000000
+#define CFG_FLASH_BASE PHYS_FLASH_1
+#define CFG_MAX_FLASH_SECT 256
+#define CFG_MAX_FLASH_BANKS 1
+#endif
+
+/* NAND flash */
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1
+#define CFG_NAND_BASE 0x40000000
+#define CFG_NAND_DBW_8 1
+
+/* Ethernet */
+#define CONFIG_MACB 1
+#define CONFIG_RMII 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R 1
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW 1
+#define LITTLEENDIAN 1
+#define CONFIG_DOS_PARTITION 1
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
+#define CFG_USB_OHCI_SLOT_NAME "at91sam9263"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE 1
+
+#define CFG_LOAD_ADDR 0x22000000 /* load address */
+
+#define CFG_MEMTEST_START PHYS_SDRAM
+#define CFG_MEMTEST_END 0x23e00000
+
+#define CFG_USE_DATAFLASH 1
+#undef CFG_USE_NANDFLASH
+
+#ifdef CFG_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CFG_ENV_IS_IN_DATAFLASH 1
+#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CFG_ENV_OFFSET 0x4200
+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x4200
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock0 " \
+ "mtdparts=at91_nand:-(root) "\
+ "rw rootfstype=jffs2"
+
+#else /* CFG_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CFG_ENV_IS_IN_NAND 1
+#define CFG_ENV_OFFSET 0x60000
+#define CFG_ENV_OFFSET_REDUND 0x80000
+#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock5 " \
+ "mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
+ "rw rootfstype=jffs2"
+
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT "U-Boot> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+
+#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
+#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
new file mode 100644
index 0000000..2ad8d05
--- /dev/null
+++ b/include/configs/at91sam9rlek.h
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9RLEK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_CPU_NAME "AT91SAM9RL"
+#define AT91_MAIN_CLOCK 200000000 /* from 12.000 MHz crystal */
+#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */
+#define CFG_HZ 1000000 /* 1us resolution */
+
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/
+#define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+/* LCD */
+#define CONFIG_LCD 1
+#define LCD_BPP LCD_COLOR8
+#define CONFIG_LCD_LOGO 1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO 1
+#define CONFIG_LCD_INFO_BELOW_LOGO 1
+#define CFG_WHITE_ON_BLACK 1
+#define CONFIG_ATMEL_LCD 1
+#define CONFIG_ATMEL_LCD_RGB565 1
+#define CFG_CONSOLE_IS_IN_ENV 1
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_USB
+
+#define CONFIG_CMD_NAND 1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+/* DataFlash */
+#define CONFIG_HAS_DATAFLASH 1
+#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS 1
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
+#define AT91_SPI_CLK 15000000
+#define DATAFLASH_TCSS (0x1a << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
+/* NOR flash - not present */
+#define CFG_NO_FLASH 1
+
+/* NAND flash */
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1
+#define CFG_NAND_BASE 0x40000000
+#define CFG_NAND_DBW_8 1
+
+/* Ethernet - not present */
+
+/* USB - not supported */
+
+#define CFG_LOAD_ADDR 0x22000000 /* load address */
+
+#define CFG_MEMTEST_START PHYS_SDRAM
+#define CFG_MEMTEST_END 0x23e00000
+
+#define CFG_USE_DATAFLASH 1
+#undef CFG_USE_NANDFLASH
+
+#ifdef CFG_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CFG_ENV_IS_IN_DATAFLASH 1
+#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CFG_ENV_OFFSET 0x4200
+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x4200
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock0 " \
+ "mtdparts=at91_nand:-(root) "\
+ "rw rootfstype=jffs2"
+
+#else /* CFG_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CFG_ENV_IS_IN_NAND 1
+#define CFG_ENV_OFFSET 0x60000
+#define CFG_ENV_OFFSET_REDUND 0x80000
+#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock5 " \
+ "mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
+ "rw rootfstype=jffs2"
+
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT "U-Boot> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+
+#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
+#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/atc.h b/include/configs/atc.h
index 4ef50c2..285b4e4 100644
--- a/include/configs/atc.h
+++ b/include/configs/atc.h
@@ -111,7 +111,7 @@
#define CONFIG_BOOTCOMMAND \
"bootp;" \
"setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath} " \
+ "nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
"bootm"
@@ -182,9 +182,9 @@
#define CONFIG_RTC_DS12887
-#define RTC_BASE_ADDR 0xF5000000
-#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
-#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
+#define RTC_BASE_ADDR 0xF5000000
+#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
+#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 5aad043..3fc9975 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -24,6 +24,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <asm/arch/memory-map.h>
+
#define CONFIG_AVR32 1
#define CONFIG_AT32AP 1
#define CONFIG_AT32AP7000 1
@@ -112,8 +114,11 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
#define CONFIG_ATMEL_USART 1
#define CONFIG_MACB 1
@@ -137,11 +142,9 @@
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_INTRAM_BASE 0x24000000
-#define CFG_INTRAM_SIZE 0x8000
-
-#define CFG_SDRAM_BASE 0x10000000
-#define CFG_SDRAM_16BIT 1
+#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE EBI_SDRAM_BASE
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 65536
@@ -150,27 +153,20 @@
#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
#define CFG_MALLOC_LEN (256*1024)
-#define CFG_MALLOC_END \
- ({ \
- DECLARE_GLOBAL_DATA_PTR; \
- CFG_SDRAM_BASE + gd->sdram_size; \
- })
-#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN)
-
#define CFG_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT "Uboot> "
+#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
-#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_START EBI_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 95aeab6..ba18eb6 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -24,6 +24,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <asm/arch/memory-map.h>
+
#define CONFIG_AVR32 1
#define CONFIG_AT32AP 1
#define CONFIG_AT32AP7000 1
@@ -139,9 +141,9 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
-#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
@@ -170,10 +172,9 @@
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_INTRAM_BASE 0x24000000
-#define CFG_INTRAM_SIZE 0x8000
-
-#define CFG_SDRAM_BASE 0x10000000
+#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE EBI_SDRAM_BASE
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 65536
@@ -185,17 +186,17 @@
#define CFG_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT "Uboot> "
+#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
-#define CFG_MAXARGS 8
+#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
-#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_START EBI_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
index 194788b..a528ddf 100644
--- a/include/configs/atstk1003.h
+++ b/include/configs/atstk1003.h
@@ -24,6 +24,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <asm/arch/memory-map.h>
+
#define CONFIG_AVR32 1
#define CONFIG_AT32AP 1
#define CONFIG_AT32AP7001 1
@@ -153,10 +155,9 @@
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_INTRAM_BASE 0x24000000
-#define CFG_INTRAM_SIZE 0x8000
-
-#define CFG_SDRAM_BASE 0x10000000
+#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE EBI_SDRAM_BASE
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 65536
@@ -167,17 +168,17 @@
#define CFG_MALLOC_LEN (256*1024)
/* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT "Uboot> "
+#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
-#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_START EBI_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index b81fc21..fc9585e 100644
--- a/include/configs/atstk1004.h
+++ b/include/configs/atstk1004.h
@@ -24,6 +24,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <asm/arch/memory-map.h>
+
#define CONFIG_AVR32 1
#define CONFIG_AT32AP 1
#define CONFIG_AT32AP7002 1
@@ -153,11 +155,9 @@
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_INTRAM_BASE 0x24000000
-#define CFG_INTRAM_SIZE 0x8000
-
-#define CFG_SDRAM_BASE 0x10000000
-#define CFG_SDRAM_16BIT 1
+#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE EBI_SDRAM_BASE
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 65536
@@ -168,17 +168,17 @@
#define CFG_MALLOC_LEN (256*1024)
/* Allow 2MB for the kernel run-time image */
-#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
+#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT "Uboot> "
+#define CFG_PROMPT "U-Boot> "
#define CFG_CBSIZE 256
#define CFG_MAXARGS 16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
-#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_START EBI_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
new file mode 100644
index 0000000..9fd49a5
--- /dev/null
+++ b/include/configs/atstk1006.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1002 CPU daughterboard
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/memory-map.h>
+
+#define CONFIG_AVR32 1
+#define CONFIG_AT32AP 1
+#define CONFIG_AT32AP7000 1
+#define CONFIG_ATSTK1006 1
+#define CONFIG_ATSTK1000 1
+
+#define CONFIG_ATSTK1000_EXT_FLASH 1
+
+/*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+ */
+#define CFG_HZ 1000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
+ */
+#define CONFIG_PLL 1
+#define CFG_POWER_MANAGER 1
+#define CFG_OSC0_HZ 20000000
+#define CFG_PLL0_DIV 1
+#define CFG_PLL0_MUL 7
+#define CFG_PLL0_SUPPRESS_CYCLES 16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ */
+#define CFG_CLKDIV_CPU 0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ */
+#define CFG_CLKDIV_HSB 1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ */
+#define CFG_CLKDIV_PBA 2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ */
+#define CFG_CLKDIV_PBB 1
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ * icp = PLLOPT<2>
+ * ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CFG_PLL0_OPT 0x04
+
+#undef CONFIG_USART0
+#define CONFIG_USART1 1
+#undef CONFIG_USART2
+#undef CONFIG_USART3
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION 1
+
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_STACKSIZE (2048)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS \
+ "console=ttyS0 root=mtd3 fbmem=2400k"
+
+#define CONFIG_BOOTCOMMAND \
+ "fsload; bootm $(fileaddr)"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_AUTOBOOT 1
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+#define CONFIG_NET_MULTI 1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART 1
+#define CONFIG_MACB 1
+#define CONFIG_PIO2 1
+#define CFG_NR_PIOS 5
+#define CFG_HSDRAMC 1
+#define CONFIG_MMC 1
+
+#define CFG_DCACHE_LINESZ 32
+#define CFG_ICACHE_LINESZ 32
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+/* External flash on STK1000 */
+#if 0
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#endif
+
+#define CFG_FLASH_BASE 0x00000000
+#define CFG_FLASH_SIZE 0x800000
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 135
+
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+
+#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE EBI_SDRAM_BASE
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 65536
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
+
+#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+
+#define CFG_MALLOC_LEN (256*1024)
+#define CFG_DMA_ALLOC_LEN (16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
+#define CFG_BOOTPARAMS_LEN (16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CFG_PROMPT "U-Boot> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+
+#define CFG_MEMTEST_START EBI_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x3f00000)
+#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/barco.h b/include/configs/barco.h
index 0bb446f..4f57067 100644
--- a/include/configs/barco.h
+++ b/include/configs/barco.h
@@ -96,8 +96,8 @@
#define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_BOOTCOMMAND "boot_default"
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_BOOTCOMMAND "boot_default"
/*
* Miscellaneous configurable options
@@ -135,9 +135,9 @@
#define CONFIG_LOGBUFFER
#ifdef CONFIG_LOGBUFFER
-#define CFG_STDOUT_ADDR 0x1FFC000
+#define CFG_STDOUT_ADDR 0x1FFC000
#else
-#define CFG_STDOUT_ADDR 0x2B9000
+#define CFG_STDOUT_ADDR 0x2B9000
#endif
#define CFG_RESET_ADDRESS 0xFFF00100
@@ -158,9 +158,9 @@
#define CFG_GBL_DATA_SIZE 128
-#define CFG_INIT_RAM_ADDR 0x40000000
-#define CFG_INIT_RAM_END 0x1000
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_END 0x1000
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#endif
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 66a0af6..d70aa10 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -25,7 +25,7 @@
#define CONFIG_SMC91111_BASE 0x20300300
/* FLASH/ETHERNET uses the same address range */
-#define SHARED_RESOURCES 1
+#define SHARED_RESOURCES 1
/* Is I2C bit-banged? */
#define CONFIG_SOFT_I2C 1
@@ -112,7 +112,7 @@
#endif
#define CFG_ENV_SIZE 0x2000
-#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
#define ENV_IS_EMBEDDED
#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
@@ -123,7 +123,7 @@
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS 1
/* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR 11
+#define CFG_JFFS2_FIRST_SECTOR 11
/*
* following timeouts shall be used once the
@@ -148,7 +148,7 @@
#define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1)
#define CONFIG_LOADADDR 0x01000000
-#define CFG_LOAD_ADDR CONFIG_LOADADDR
+#define CFG_LOAD_ADDR CONFIG_LOADADDR
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 39c7359..a881d53 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -103,11 +103,11 @@
#define CFG_LONGHELP 1
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-#define CONFIG_BOOTCOMMAND "run ramboot"
+#define CONFIG_BOOTCOMMAND "run ramboot"
#if defined(CONFIG_POST_TEST)
/* POST support */
-#define CONFIG_POST ( CFG_POST_MEMORY | \
+#define CONFIG_POST ( CFG_POST_MEMORY | \
CFG_POST_UART | \
CFG_POST_FLASH | \
CFG_POST_ETHER | \
@@ -208,7 +208,7 @@
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024)
+#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024)
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@@ -281,10 +281,10 @@
#define NAND_MAX_CHIPS 1
#define BFIN_NAND_READY PF3
-#define NAND_WAIT_READY(nand) \
- do { \
- int timeout = 0; \
- while(!(*pPORTFIO & PF3)) \
+#define NAND_WAIT_READY(nand) \
+ do { \
+ int timeout = 0; \
+ while(!(*pPORTFIO & PF3)) \
if (timeout++ > 100000) \
break; \
} while (0)
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 641548d..e99e979 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -148,28 +148,27 @@
#if (CONFIG_DRIVER_SMC91111)
#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
- "$(rootpath) console=ttyBF0,57600\0" \
+ "$(rootpath) console=ttyBF0,57600\0" \
"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux; " \
+ "ramboot=tftpboot $(loadaddr) linux; " \
"run ramargs; run addip; bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux; " \
+ "nfsboot=tftpboot $(loadaddr) linux; " \
"run nfsargs; run addip; bootelf\0" \
- "update=tftpboot $(loadaddr) u-boot.bin; " \
+ "update=tftpboot $(loadaddr) u-boot.bin; " \
"protect off 0x20000000 0x2003FFFF; " \
"erase 0x20000000 0x2003FFFF; " \
- "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
+ "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
""
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"flashboot=bootm 0x20100000\0" \
""
#endif
-
/*
* BOOTP options
*/
@@ -178,7 +177,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
@@ -193,7 +191,6 @@
#define CONFIG_CMD_DHCP
#endif
-
/*
* Console settings
*/
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index cbd74a0..75dd4e7 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -302,7 +302,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h
index a5621b8..6f0d4b0 100644
--- a/include/configs/c2mon.h
+++ b/include/configs/c2mon.h
@@ -54,9 +54,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 440972c..f097e2c 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -31,7 +31,7 @@
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
-#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
+#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
@@ -40,6 +40,8 @@
#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
@@ -115,7 +117,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* Flash configuration, expect one 16 Megabyte Bank at most
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index e06735d..c801f03 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -39,7 +39,7 @@
#define BOARD_LATE_INIT 1
#define CONFIG_BAUDRATE 38400
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/*
* Size of malloc() pool
@@ -104,7 +104,7 @@
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#endif
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
/* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@@ -137,21 +137,21 @@
/*
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
-#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
+#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
#define CFG_DRAM_BASE 0xa0000000
#define CFG_DRAM_SIZE 0x04000000
@@ -210,7 +210,7 @@
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index d554348..ef50c7c 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -31,6 +31,8 @@
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_CM5200 1 /* ... on CM5200 platform */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Supported commands
*/
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
index a869364..ac2b7a1 100644
--- a/include/configs/cmi_mpc5xx.h
+++ b/include/configs/cmi_mpc5xx.h
@@ -24,7 +24,7 @@
* File: cmi_mpc5xx.h
*
* Discription: Config header file for cmi
- * board using an MPC5xx CPU
+ * board using an MPC5xx CPU
*
*/
@@ -36,7 +36,7 @@
*/
#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
-#define CONFIG_CMI 1 /* Using the customized cmi board */
+#define CONFIG_CMI 1 /* Using the customized cmi board */
/* Serial Console Configuration */
#define CONFIG_5xx_CONS_SCI1
@@ -79,11 +79,11 @@
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */
+#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */
#define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */
-#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
+#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
#define CONFIG_STATUS_LED 1 /* Enable status led */
@@ -121,30 +121,30 @@
/*
* Internal Memory Mapped (This is not the IMMR content)
*/
-#define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */
+#define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */
/*
* Definitions for initial stack pointer and data area
*/
-#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
-#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
-#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */
+#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
+#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
+#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
-#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */
+#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */
/*
* Start addresses for the final memory configuration
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
+#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
#define CFG_FLASH_BASE 0x02000000 /* External flash */
#define PLD_BASE 0x03000000 /* PLD */
#define ANYBUS_BASE 0x03010000 /* Anybus Module */
#define CFG_RESET_ADRESS 0x01000000 /* Adress which causes reset */
-#define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */
- /* This adress is given to the linker with -Ttext to */
- /* locate the text section at this adress. */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */
+ /* This adress is given to the linker with -Ttext to */
+ /* locate the text section at this adress. */
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CFG_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */
@@ -163,16 +163,16 @@
*/
#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */
-#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
+#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_PROTECTION 1 /* Physically section protection on */
#define CFG_ENV_IS_IN_FLASH 1
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
-#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
+#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
+#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#endif
@@ -219,7 +219,7 @@
*-----------------------------------------------------------------------
* Data show cycle
*/
-#define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */
+#define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register
@@ -227,7 +227,7 @@
* Set all bits to 40 Mhz
*
*/
-#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
+#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
@@ -236,12 +236,12 @@
*-----------------------------------------------------------------------
*
*/
-#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
+#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
/*-----------------------------------------------------------------------
* ICTRL - I-Bus Support Control Register
*/
-#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
+#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
/*-----------------------------------------------------------------------
* USIU - Memory Controller Register
@@ -256,7 +256,7 @@
#define CFG_OR2_PRELIM (OR_ADDR_MK_FF)
#define CFG_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
#define CFG_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
- OR_ACS_10 | OR_ETHR | OR_CSNT)
+ OR_ACS_10 | OR_ETHR | OR_CSNT)
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index c7e3899..649b053 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -101,7 +101,7 @@
* bootloader residing in flash ('chainloading'); if you want to use
* chainloading or want to compile a u-boot binary that can be loaded into
* RAM via BDM set
- * "#if 0" to "#if 1"
+ * "#if 0" to "#if 1"
* You will need a first stage bootloader then, e. g. colilo or a working BDM
* cable (Background Debug Mode)
*
@@ -165,7 +165,7 @@
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
index 1b30e51..fffd1fe 100644
--- a/include/configs/cpci5200.h
+++ b/include/configs/cpci5200.h
@@ -50,6 +50,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index 0be0f21..a807d00 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -37,7 +37,7 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
+#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
#define CONFIG_CSB226 1 /* on a CSB226 board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
index a24478d..15bf177 100644
--- a/include/configs/csb272.h
+++ b/include/configs/csb272.h
@@ -33,7 +33,7 @@
* (easy to change)
*/
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
+#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
@@ -182,7 +182,7 @@
*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
+#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
/* 32usec min. for LXT971A */
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
index 064650c..b06c0a2 100644
--- a/include/configs/csb472.h
+++ b/include/configs/csb472.h
@@ -33,7 +33,7 @@
* (easy to change)
*/
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
+#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
@@ -181,7 +181,7 @@
*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
+#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
/* 32usec min. for LXT971A */
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 8ecd059..632c4c2 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -145,16 +145,16 @@
#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3)
-#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 96c9a30..10166a1 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -102,7 +102,7 @@
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index de8c4fa..ba68605 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -140,16 +140,16 @@
#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */
#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*2)
-#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h
index d32e046..e7873e9 100644
--- a/include/configs/dnp1110.h
+++ b/include/configs/dnp1110.h
@@ -83,7 +83,7 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200"
+#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200"
#define CONFIG_ETHADDR 02:80:ad:20:31:b8
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_IPADDR 172.22.2.23
diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h
index f5cf477..5433082 100644
--- a/include/configs/ep7312.h
+++ b/include/configs/ep7312.h
@@ -34,7 +34,7 @@
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
#define CONFIG_EP7312 1 /* on an EP7312 Board */
#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
-#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
+#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
#undef CONFIG_USE_IRQ /* don't need them anymore */
@@ -81,8 +81,8 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600"
-#define CONFIG_ETHADDR 08:00:3e:21:c7:f7
+#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600"
+#define CONFIG_ETHADDR 08:00:3e:21:c7:f7
/*#define CONFIG_NETMASK 255.255.0.0 */
/*#define CONFIG_IPADDR 172.22.2.128 */
/*#define CONFIG_SERVERIP 172.22.2.126 */
diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h
index cebe849..8a220b6 100644
--- a/include/configs/ep8248.h
+++ b/include/configs/ep8248.h
@@ -234,13 +234,13 @@
/* Hard reset configuration word */
#define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
/* No slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index 490db5f..0ce6b80 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -28,17 +28,17 @@
* board/config.h - configuration options, board specific
*
* "EP8260 H, V.1.1"
- * - 64M 60x Bus SDRAM
- * - 32M Local Bus SDRAM
- * - 16M Flash (4 x AM29DL323DB90WDI)
- * - 128k NVRAM with RTC
+ * - 64M 60x Bus SDRAM
+ * - 32M Local Bus SDRAM
+ * - 16M Flash (4 x AM29DL323DB90WDI)
+ * - 128k NVRAM with RTC
*
* "EP8260 H2, V.1.3" (CFG_EP8260_H2)
- * - 300MHz/133MHz/66MHz
- * - 64M 60x Bus SDRAM
- * - 32M Local Bus SDRAM
- * - 32M Flash
- * - 128k NVRAM with RTC
+ * - 300MHz/133MHz/66MHz
+ * - 64M 60x Bus SDRAM
+ * - 32M Local Bus SDRAM
+ * - 32M Flash
+ * - 128k NVRAM with RTC
*/
#ifndef __CONFIG_H
@@ -408,7 +408,7 @@
CFG_SBC_HRCW_IMMR |\
HRCW_APPC10 |\
HRCW_CS10PC01 |\
- CFG_SBC_MODCK_H |\
+ CFG_SBC_MODCK_H |\
CFG_SBC_HRCW_BOOT_FLAGS)
#else
#define CFG_HRCW_MASTER 0x10400245
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index 8e5d6e5..ac5847c 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -229,7 +229,7 @@
#endif /* CFG_ENV_IS_IN_EEPROM */
/* RTC Configuration */
-#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */
+#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */
#define CFG_I2C_RTC_ADDR 0x68
#define CONFIG_M41T11_BASE_YEAR 1900
@@ -353,13 +353,13 @@
/* Hard reset configuration word */
#define CFG_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */
/* No slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h
index 66500c2..1571477 100644
--- a/include/configs/evb4510.h
+++ b/include/configs/evb4510.h
@@ -98,7 +98,7 @@
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTCOMMAND "tftp 100000 uImage"
-/* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */
+/* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index 1276f4d..ffe7671 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -58,7 +58,7 @@
#define CONFIG_LEON_RAM_SELECT CONFIG_LEON_RAM_SRAM
/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 20000000 /* 20MHz */
+#define CONFIG_SYS_CLK_FREQ 20000000 /* 20MHz */
/* Number of SPARC register windows */
#define CFG_SPARC_NWINDOWS 8
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 710a082..7b1d582 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -39,10 +39,10 @@
#define CONFIG_LEON3 /* This is an LEON3 CPU */
#define CONFIG_LEON 1 /* This is an LEON CPU */
/* Altera NIOS Development board, Stratix II board */
-#define CONFIG_GR_EP2S60 1
+#define CONFIG_GR_EP2S60 1
/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */
+#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */
/* Number of SPARC register windows */
#define CFG_SPARC_NWINDOWS 8
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index 1fdef3d..6fe2b7c 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -39,7 +39,7 @@
#define CONFIG_GRXC3S1500 1 /* ... on GR-XC3S-1500 board */
/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
+#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
/* Number of SPARC register windows */
#define CFG_SPARC_NWINDOWS 8
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index 60ad396..3fb8eb3 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -46,7 +46,7 @@
#define CONFIG_TSIM 1 /* ... running on TSIM */
/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
+#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
/* Number of SPARC register windows */
#define CFG_SPARC_NWINDOWS 8
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index 2ad5b95..406ce3d 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -45,7 +45,7 @@
#define CONFIG_TSIM 1 /* ... running on TSIM */
/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
+#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
/* Number of SPARC register windows */
#define CFG_SPARC_NWINDOWS 8
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h
index 4ecaf90..13b0358 100644
--- a/include/configs/hcu4.h
+++ b/include/configs/hcu4.h
@@ -127,14 +127,14 @@
#ifdef CFG_ENV_IS_IN_EEPROM
/* Put the environment after the SDRAM configuration */
-#define PROM_SIZE 2048
+#define PROM_SIZE 2048
#define CFG_ENV_OFFSET 512
#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* Put the environment in Flash */
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
index f5f1197..2080868 100644
--- a/include/configs/hcu5.h
+++ b/include/configs/hcu5.h
@@ -113,7 +113,7 @@
#ifdef CFG_ENV_IS_IN_EEPROM
/* Put the environment after the SDRAM and bootstrap configuration */
-#define PROM_SIZE 2048
+#define PROM_SIZE 2048
#define CFG_BOOSTRAP_OPTION_OFFSET 512
#define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10)
#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
@@ -134,7 +134,7 @@
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
+#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
#define CFG_DDR_CACHED_ADDR 0x50000000 /* setup 2nd TLB cached here */
#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
#define CONFIG_DDR_ECC 1 /* enable ECC */
@@ -176,13 +176,13 @@
/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAME hcu5
#define CONFIG_IPADDR 172.25.1.99
-#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
+#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SERVERIP 172.25.1.3
#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=0x01000000\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@@ -192,11 +192,11 @@
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
- "bootfile=hcu5/uImage\0" \
- "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
- "load=tftp 100000 hcu5/u-boot.bin\0" \
+ "bootfile=hcu5/uImage\0" \
+ "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
+ "load=tftp 100000 hcu5/u-boot.bin\0" \
"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \
"cp.b 100000 FFFB0000 50000\0" \
"upd=run load update\0" \
@@ -204,9 +204,9 @@
"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \
"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
- "usbargs=setenv bootargs root=/dev/sda1 ro\0" \
+ "usbargs=setenv bootargs root=/dev/sda1 ro\0" \
"linux=usb start; ext2load usb 0 ${loadaddr} /boot/uImage;" \
- "run usbargs addip addtty; bootm\0" \
+ "run usbargs addip addtty; bootm\0" \
"net_nfs_fdt=tftp 200000 ${bootfile};" \
"tftp ${fdt_addr} ${fdt_file};" \
"run nfsargs addip addtty;" \
diff --git a/include/configs/hermes.h b/include/configs/hermes.h
index e3a2ed2..48b23bd 100644
--- a/include/configs/hermes.h
+++ b/include/configs/hermes.h
@@ -54,9 +54,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@@ -105,7 +105,7 @@
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CFG_ALLOC_DPRAM 1 /* use allocation routines */
+#define CFG_ALLOC_DPRAM 1 /* use allocation routines */
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
@@ -227,7 +227,7 @@
/* +0x0282 => 0x03800000 */
#define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \
SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
+ /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
SCCR_EBDF00 | SCCR_DFSYNC00 | \
SCCR_DFBRG00 | SCCR_DFNL000 | \
SCCR_DFNH000)
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index e5a8897..ad7cf76 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -40,6 +40,8 @@
#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
index 2ed51f7..7c3ebad 100644
--- a/include/configs/idmr.h
+++ b/include/configs/idmr.h
@@ -164,7 +164,7 @@
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
diff --git a/include/configs/impa7.h b/include/configs/impa7.h
index 0e52ffe..e9704fc 100644
--- a/include/configs/impa7.h
+++ b/include/configs/impa7.h
@@ -34,7 +34,7 @@
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
#define CONFIG_IMPA7 1 /* on an impA7 Board */
#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
-#define CONFIG_ARM7_REVD 1 /* enable ARM720 REV.D Workarounds */
+#define CONFIG_ARM7_REVD 1 /* enable ARM720 REV.D Workarounds */
#undef CONFIG_USE_IRQ /* don't need them anymore */
@@ -80,7 +80,7 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600"
+#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600"
/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5a */
/*#define CONFIG_NETMASK 255.255.0.0 */
/*#define CONFIG_IPADDR 172.22.2.128 */
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 4281d73..ec4ed1e 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -65,7 +65,8 @@
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
-#define CONFIG_MXC_SPI_IFACE 1
+#define CONFIG_DEFAULT_SPI_BUS 1
+#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index c89f041..6ec92c3 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -40,6 +40,8 @@
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index 5310e0d..2b65052 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -34,7 +34,7 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
+#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
@@ -136,11 +136,11 @@
/*
* I2C bus
*/
-#define CONFIG_HARD_I2C 1
-#define CFG_I2C_SPEED 50000
-#define CFG_I2C_SLAVE 0xfe
+#define CONFIG_HARD_I2C 1
+#define CFG_I2C_SPEED 50000
+#define CFG_I2C_SLAVE 0xfe
-#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_IS_IN_EEPROM 1
#define CFG_ENV_OFFSET 0x00 /* environment starts here */
#define CFG_ENV_SIZE 1024 /* 1 KiB */
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index e1d1483..347fa02 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -140,7 +140,7 @@ SIB at Block62 End Block62 address 0x24f80000
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
/*-----------------------------------------------------------------------
* FLASH and environment organization
@@ -156,9 +156,9 @@ SIB at Block62 End Block62 address 0x24f80000
*/
#define CFG_FLASH_BASE 0x24000000
-#define CFG_MAX_FLASH_SECT 64
+#define CFG_MAX_FLASH_SECT 64
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
+#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h
index bc5f9e1..b7c43fe 100644
--- a/include/configs/ixdp425.h
+++ b/include/configs/ixdp425.h
@@ -165,7 +165,7 @@
*/
#define CFG_SDR_CONFIG 0xd
#define CFG_SDR_MODE_CONFIG 0x1
-#define CFG_SDRAM_REFRESH_CNT 0x81a
+#define CFG_SDRAM_REFRESH_CNT 0x81a
/*
* GPIO settings
@@ -178,7 +178,7 @@
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
@@ -193,7 +193,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h
index a3be0b5..05dc841 100644
--- a/include/configs/ixdpg425.h
+++ b/include/configs/ixdpg425.h
@@ -201,13 +201,13 @@
*/
#define CFG_SDR_CONFIG 0x18
#define CFG_SDR_MODE_CONFIG 0x1
-#define CFG_SDRAM_REFRESH_CNT 0x81a
+#define CFG_SDRAM_REFRESH_CNT 0x81a
/*
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
@@ -225,7 +225,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 0ac3e7e..c985927 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -41,6 +41,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
@@ -142,7 +144,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#if 0
/* pass open firmware flat tree */
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index c7c42a4..a596768 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -108,7 +108,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
diff --git a/include/configs/korat.h b/include/configs/korat.h
index 48d73ac..7655666 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -225,7 +225,7 @@
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
/* buffers & descriptors */
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
@@ -308,7 +308,7 @@
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
- /* Print Buffer Size */
+ /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@@ -339,7 +339,7 @@
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
/* CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT
diff --git a/include/configs/lart.h b/include/configs/lart.h
index 8f18c9f..4570398 100644
--- a/include/configs/lart.h
+++ b/include/configs/lart.h
@@ -76,7 +76,7 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600"
+#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600"
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_IPADDR 172.22.2.131
diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h
index 518186b..d3908b9 100644
--- a/include/configs/linkstation.h
+++ b/include/configs/linkstation.h
@@ -114,9 +114,9 @@
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00800000 /* Default load address: 8 MB */
-#define CONFIG_BOOTCOMMAND "run bootcmd1"
+#define CONFIG_BOOTCOMMAND "run bootcmd1"
#define CONFIG_BOOTARGS "root=/dev/sda1 console=ttyS1,57600 netconsole=@192.168.1.7/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug"
-#define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm"
+#define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm"
#define CFG_CONSOLE_IS_IN_ENV
@@ -214,28 +214,28 @@
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFFC00000
+#define CFG_FLASH_BASE 0xFFC00000
#define CFG_FLASH_SIZE 0x00400000
-#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_RESET_ADDRESS 0xFFF00100
-#define CFG_EUMB_ADDR 0x80000000
+#define CFG_RESET_ADDRESS 0xFFF00100
+#define CFG_EUMB_ADDR 0x80000000
#define CFG_PCI_MEM_ADDR 0xB0000000
#define CFG_MISC_REGION_ADDR 0xFE000000
-#define CFG_MONITOR_LEN 0x00040000 /* 256 kB */
-#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
+#define CFG_MONITOR_LEN 0x00040000 /* 256 kB */
+#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
-#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
-#define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
/* Maximum amount of RAM */
#if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
-#define CFG_MAX_RAM_SIZE 0x04000000 /* 64MB of SDRAM */
+#define CFG_MAX_RAM_SIZE 0x04000000 /* 64MB of SDRAM */
#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
-#define CFG_MAX_RAM_SIZE 0x08000000 /* 128MB of SDRAM */
+#define CFG_MAX_RAM_SIZE 0x08000000 /* 128MB of SDRAM */
#else
#error Unknown LinkStation type
#endif
diff --git a/include/configs/logodl.h b/include/configs/logodl.h
index 2b2d377..047b4a4 100644
--- a/include/configs/logodl.h
+++ b/include/configs/logodl.h
@@ -34,7 +34,7 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
+#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
#define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 1f669aa..cf406c8 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -88,15 +88,20 @@
/* unused GPT0 COMP reg */
#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */
+#define CFG_OCM_SIZE (16 << 10)
/* Additional registers for watchdog timer post test */
#define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK2)
#define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK1)
#define CFG_DSPIC_TEST_ADDR CFG_WATCHDOG_FLAGS_ADDR
+#define CFG_OCM_STATUS_ADDR CFG_WATCHDOG_FLAGS_ADDR
#define CFG_WATCHDOG_MAGIC 0x12480000
#define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000
#define CFG_DSPIC_TEST_MASK 0x00000001
+#define CFG_OCM_STATUS_OK 0x00009A00
+#define CFG_OCM_STATUS_FAIL 0x0000A300
+#define CFG_OCM_STATUS_MASK 0x0000FF00
/*-----------------------------------------------------------------------
* Serial Port
@@ -162,6 +167,7 @@
CFG_POST_FPU | \
CFG_POST_I2C | \
CFG_POST_MEMORY | \
+ CFG_POST_OCM | \
CFG_POST_RTC | \
CFG_POST_SPR | \
CFG_POST_UART | \
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index 67243d4..af066f3 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -101,7 +101,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index a9c86f9..e4c3f72 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -40,6 +40,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*
diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h
index c5b6e8f..4e9645e 100644
--- a/include/configs/mcu25.h
+++ b/include/configs/mcu25.h
@@ -45,7 +45,7 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
+#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
@@ -54,13 +54,13 @@
#define CFG_MONITOR_BASE TEXT_BASE
/* ... with on-chip memory here (4KBytes) */
-#define CFG_OCM_DATA_ADDR 0xF4000000
-#define CFG_OCM_DATA_SIZE 0x00001000
+#define CFG_OCM_DATA_ADDR 0xF4000000
+#define CFG_OCM_DATA_SIZE 0x00001000
/* Do not set up locked dcache as init ram. */
#undef CFG_INIT_DCACHE_CS
/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
-#define CFG_TEMP_STACK_OCM 1
+#define CFG_TEMP_STACK_OCM 1
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
@@ -127,7 +127,7 @@
#ifdef CFG_ENV_IS_IN_EEPROM
/* Put the environment after the SDRAM configuration */
-#define PROM_SIZE 2048
+#define PROM_SIZE 2048
#define CFG_ENV_OFFSET 512
#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
#endif
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index 49919fb..8dfb9aa 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -50,6 +50,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
@@ -154,7 +156,7 @@
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#endif
/*
* I2C configuration
diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h
index 2924acc..59ff96b 100644
--- a/include/configs/mgcoge.h
+++ b/include/configs/mgcoge.h
@@ -188,13 +188,13 @@
#define CFG_HRCW_MASTER 0x0604b211
/* No slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h
index 4461bdf..5159897 100644
--- a/include/configs/modnet50.h
+++ b/include/configs/modnet50.h
@@ -90,7 +90,8 @@
/*#define CONFIG_BOOTDELAY 10*/
/* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */
#define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000"
-#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd"
+#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K " \
+ "root=/dev/ram keepinitrd"
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 1503598..b6843af 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -35,6 +35,7 @@
#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
#define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* BOOTP options
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
index f614e67..a218f75 100644
--- a/include/configs/mpc7448hpc2.h
+++ b/include/configs/mpc7448hpc2.h
@@ -39,7 +39,7 @@
#define CONFIG_MPC7448HPC2
#define CONFIG_74xx
-#define CONFIG_750FX /* this option to enable init of extended BATs */
+#define CONFIG_HIGH_BATS /* High BATs supported */
#define CONFIG_ALTIVEC /* undef to disable */
#define CFG_BOARD_NAME "MPC7448 HPC II"
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
index 9c94c4e..5e79a27 100644
--- a/include/configs/ms7720se.h
+++ b/include/configs/ms7720se.h
@@ -96,7 +96,7 @@
#define CFG_ENV_SECT_SIZE (64 * 1024)
#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_ERASE_TOUT 120000
#define CFG_FLASH_WRITE_TOUT 500
/* Board Clock */
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 8538037..8d92a13 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -39,7 +39,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
+#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.0.22
#define CONFIG_SERVERIP 192.168.0.1
@@ -86,7 +86,7 @@
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */
#define CFG_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image
- in Flash (NOT run time address in SDRAM) ?!? */
+ in Flash (NOT run time address in SDRAM) ?!? */
#define CFG_MONITOR_LEN (128 * 1024) /* */
#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */
@@ -101,7 +101,7 @@
#define CFG_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */
#define CFG_MAX_FLASH_SECT 150 /* Max number of sectors on each
- Flash chip */
+ Flash chip */
/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
#define CFG_MAX_FLASH_BANKS 2
@@ -123,7 +123,7 @@
#define CFG_ENV_SECT_SIZE (8 * 1024)
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + (1 * CFG_ENV_SECT_SIZE))
-#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) /* Offset of env Flash sector relative to CFG_FLASH_BASE */
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) /* Offset of env Flash sector relative to CFG_FLASH_BASE */
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE))
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index a25364d..3000c77 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -48,7 +48,7 @@
#define BOARD_LATE_INIT 1
#define CONFIG_BOOTDELAY -1
-#define CONFIG_BOOTARGS "console=ttySC0,38400"
+#define CONFIG_BOOTARGS "console=ttySC0,38400"
#define CONFIG_ENV_OVERWRITE 1
/* SDRAM */
@@ -71,8 +71,8 @@
/* #define CFG_FLASH_BASE (0xA1000000)*/
#define CFG_FLASH_BASE (0xA0000000)
#define CFG_MAX_FLASH_BANKS (1) /* Max number of
- * Flash memory banks
- */
+ * Flash memory banks
+ */
#define CFG_MAX_FLASH_SECT 142
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
@@ -96,7 +96,7 @@
#define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_ERASE_TOUT 120000
#define CFG_FLASH_WRITE_TOUT 500
/* Board Clock */
diff --git a/include/configs/munices.h b/include/configs/munices.h
index 38b27bb..e0046ec 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -35,6 +35,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Command line configuration.
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 2ea48a6..37ba872 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -62,7 +62,8 @@
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
-#define CONFIG_MXC_SPI_IFACE 1 /* Default SPI interface number */
+#define CONFIG_DEFAULT_SPI_BUS 1
+#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index a48893d..d4deda4 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -180,16 +180,16 @@
"if test -n $swapos; then " \
"setenv swapos; saveenv; " \
"else " \
- "if test $ospart -eq 0; then setenv ospart 1;" \
- "else setenv ospart 0; fi; " \
+ "if test $ospart -eq 0; then setenv ospart 1;" \
+ "else setenv ospart 0; fi; " \
"fi\0" \
"nfsargs=setenv bootargs $bootargs " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
"nfsroot=$rootpath root=/dev/nfs\0" \
"flashargs=run setpart;setenv bootargs $bootargs " \
"root=mtd:rootfs$ospart ro " \
"rootfstype=jffs2\0" \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
"fboot=run flashargs;nboot kernel$ospart\0" \
"nboot=bootp;run nfsargs;tftp\0"
diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h
index 1d691f9..f30cb46 100644
--- a/include/configs/ns9750dev.h
+++ b/include/configs/ns9750dev.h
@@ -62,7 +62,7 @@
/*
* select serial console configuration
*/
-#define CONFIG_CONS_INDEX 1 /* Port B */
+#define CONFIG_CONS_INDEX 1 /* Port B */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@@ -93,7 +93,7 @@
#define CONFIG_BOOTDELAY 3
-/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
+/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
#define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */
#define CONFIG_NETMASK 255.255.255.0
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 8dde1ef..88bdb03 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -37,6 +37,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
index 45dc343..0913b14 100644
--- a/include/configs/p3mx.h
+++ b/include/configs/p3mx.h
@@ -42,6 +42,7 @@
#if defined (CONFIG_P3M750)
#define CONFIG_750FX /* 750GL/GX/FX */
+#define CONFIG_HIGH_BATS /* High BATs supported */
#define CFG_BOARD_NAME "P3M750"
#define CFG_BUS_HZ 100000000
#define CFG_BUS_CLK CFG_BUS_HZ
@@ -138,9 +139,9 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#if defined (CONFIG_P3M750)
-#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (1 device)*/
+#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */
#elif defined (CONFIG_P3M7448)
-#define CFG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */
+#define CFG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */
#endif
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h
index e3c8843..7e393f7 100644
--- a/include/configs/pcu_e.h
+++ b/include/configs/pcu_e.h
@@ -228,7 +228,7 @@
#if 0
/* Start port with environment in flash; switch to SPI EEPROM later */
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
#define CFG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */
#define CFG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */
@@ -313,7 +313,7 @@
/* 0x01800000 */
#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
+ /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
SCCR_EBDF00 | SCCR_DFSYNC00 | \
SCCR_DFBRG00 | SCCR_DFNL000 | \
SCCR_DFNH000 | SCCR_DFLCD100 | \
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index ac72f98..aca70dc 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -211,7 +211,7 @@
*/
#define CFG_SDR_CONFIG 0x18
#define CFG_SDR_MODE_CONFIG 0x1
-#define CFG_SDRAM_REFRESH_CNT 0x81a
+#define CFG_SDRAM_REFRESH_CNT 0x81a
/*
* FLASH and environment organization
@@ -251,7 +251,7 @@
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#else
-#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
index 2ce39c9..c065d33 100644
--- a/include/configs/pf5200.h
+++ b/include/configs/pf5200.h
@@ -49,6 +49,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
index fb5ae99..56b4d92 100644
--- a/include/configs/ppmc8260.h
+++ b/include/configs/ppmc8260.h
@@ -237,7 +237,7 @@
/* Define a command string that is automatically executed when no character
* is read on the console interface withing "Boot Delay" after reset.
*/
-#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
+#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
#ifdef CONFIG_BOOT_ROOT_INITRD
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
new file mode 100644
index 0000000..622a5d4
--- /dev/null
+++ b/include/configs/quad100hd.h
@@ -0,0 +1,298 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * quad100hd.h - configuration for Quad100hd board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405EP 1 /* Specifc 405EP support*/
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+
+#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */
+#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */
+
+/* the environment is in the EEPROM by default */
+#define CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_IN_FLASH
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0x01 /* PHY address */
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_PHY_RESET 1
+#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_LOG
+#undef CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#undef CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*-----------------------------------------------------------------------
+ * SDRAM
+ *----------------------------------------------------------------------*/
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1
+#define CFG_SDRAM_SIZE 0x02000000 /* 32 MB */
+
+/* FIX! SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL 3 /* CAS latency */
+#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
+#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*
+ * JFFS2
+ */
+#define CFG_JFFS2_FIRST_BANK 0
+#ifdef CFG_KERNEL_IN_JFFS2
+#define CFG_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */
+#else /* kernel not in JFFS */
+#define CFG_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */
+#endif
+#define CFG_JFFS2_NUM_BANKS 1
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CFG_BASE_BAUD 691200
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */
+
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CFG_EEPROM_SIZE 0x2000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFFC00000
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (TEXT_BASE)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+/* the environment is located before u-boot */
+#define CFG_ENV_ADDR (TEXT_BASE - CFG_ENV_SECT_SIZE)
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
+#endif
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE 0x400 /* Size of Environment vars */
+#define CFG_ENV_OFFSET 0x00000000
+#define CFG_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */
+#endif
+
+/* partly from PPCBoot */
+/* NAND */
+#define CONFIG_NAND
+#ifdef CONFIG_NAND
+#define CFG_NAND_BASE 0x60000000
+#define CFG_NAND_CS 10 /* our CS is GPIO10 */
+#define CFG_NAND_RDY 23 /* our RDY is GPIO23 */
+#define CFG_NAND_CE 24 /* our CE is GPIO24 */
+#define CFG_NAND_CLE 31 /* our CLE is GPIO31 */
+#define CFG_NAND_ALE 30 /* our ALE is GPIO30 */
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+/* see ./cpu/ppc4xx/start.S */
+#define CFG_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ * Taken from PPCBoot board/icecube/icecube.h
+ */
+
+/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
+#define CFG_EBC_PB0AP 0x04002480
+/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
+#define CFG_EBC_PB0CR 0xFFC5A000
+#define CFG_EBC_PB1AP 0x04005480
+#define CFG_EBC_PB1CR 0x60018000
+#define CFG_EBC_PB2AP 0x00000000
+#define CFG_EBC_PB2CR 0x00000000
+#define CFG_EBC_PB3AP 0x00000000
+#define CFG_EBC_PB3CR 0x00000000
+#define CFG_EBC_PB4AP 0x00000000
+#define CFG_EBC_PB4CR 0x00000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * Taken in part from PPCBoot board/icecube/icecube.h
+ */
+/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
+#define CFG_GPIO0_OSRH 0x55555550
+#define CFG_GPIO0_OSRL 0x00000110
+#define CFG_GPIO0_ISR1H 0x00000000
+#define CFG_GPIO0_ISR1L 0x15555445
+#define CFG_GPIO0_TSRH 0x00000000
+#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TCR 0xFFFF8097
+#define CFG_GPIO0_ODR 0x00000000
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/* ENVIRONMENT VARS */
+
+#define CONFIG_IPADDR 192.168.1.67
+#define CONFIG_SERVERIP 192.168.1.50
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_LOADADDR 300000
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index 42787f4..4e89580 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -113,7 +113,7 @@
#define CFG_ENV_SECT_SIZE (16 * 1024)
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_ERASE_TOUT 120000
#define CFG_FLASH_WRITE_TOUT 500
/* Board Clock */
diff --git a/include/configs/rmu.h b/include/configs/rmu.h
index 2ca60b7..28fb7c3 100644
--- a/include/configs/rmu.h
+++ b/include/configs/rmu.h
@@ -51,9 +51,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@@ -399,7 +399,7 @@
#define BCSR3 (CFG_BCSR_BASE + 3)
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
-#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
+#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
index 40a05fa..6251383 100644
--- a/include/configs/rsdproto.h
+++ b/include/configs/rsdproto.h
@@ -53,7 +53,7 @@
*/
#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on neither */
+#undef CONFIG_CONS_NONE /* define if console on neither */
#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
/*
@@ -91,7 +91,7 @@
#define CONFIG_ENV_OVERWRITE
/* enable I2C */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x30
@@ -128,7 +128,7 @@
#define CFG_RSD_BOOT_LOW 1
#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTARGS "devfs=mount root=ramfs"
+#define CONFIG_BOOTARGS "devfs=mount root=ramfs"
#define CONFIG_ETHADDR 08:00:3e:26:0a:5a
#define CONFIG_NETMASK 255.255.0.0
@@ -176,14 +176,14 @@
#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */
#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */
-#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */
-#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
+#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */
+#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */
/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */
-#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */
-#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
+#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */
+#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */
/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index ec7d34a..4974fb4 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -441,7 +441,7 @@
/* Define a command string that is automatically executed when no character
* is read on the console interface withing "Boot Delay" after reset.
*/
-#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
+#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
#ifdef CONFIG_BOOT_ROOT_INITRD
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index 9b05bd6..08cadf6 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -106,7 +106,9 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
+#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs " \
+ "nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \
+ "ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.0.69
@@ -205,7 +207,7 @@
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
index 6063398..7993137 100644
--- a/include/configs/sbc8260.h
+++ b/include/configs/sbc8260.h
@@ -387,7 +387,7 @@
/* Define a command string that is automatically executed when no character
* is read on the console interface withing "Boot Delay" after reset.
*/
-#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
+#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
#ifdef CONFIG_BOOT_ROOT_INITRD
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 0ebc674..7481556 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -570,6 +570,8 @@
#define CFG_HID2 HID2_HBE
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/* DDR @ 0x00000000 */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index c84b70a..358fc02 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -176,7 +176,7 @@
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 20da73e..3cd9ff8 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -55,13 +55,13 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_NUM_DDR_CONTROLLERS 2
@@ -94,7 +94,7 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -219,7 +219,7 @@
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
@@ -236,14 +236,14 @@
#else
#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
#endif
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -323,7 +323,7 @@
#undef CFG_SCSI_SCAN_BUS_REVERSE
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -331,7 +331,7 @@
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@@ -343,7 +343,7 @@
#define CONFIG_SATA_ULI5288
#define CFG_SCSI_MAX_SCSI_ID 4
#define CFG_SCSI_MAX_LUN 1
-#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
#endif
@@ -352,7 +352,7 @@
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
/* #define CONFIG_MII 1 */ /* MII PHY management */
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index 4df461d..0e830b8 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -87,7 +87,7 @@
#define CONFIG_CMD_EEPROM
#define CONFIG_BOOTDELAY 15
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
#if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
index c6f7f15..051b2e0 100644
--- a/include/configs/sc520_spunk.h
+++ b/include/configs/sc520_spunk.h
@@ -88,8 +88,12 @@
#define CONFIG_BOOTDELAY 15
-#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) "
-#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 " \
+ "mtdparts=phys:7936k(root),256k(uboot) "
+#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf " \
+ "console=ttyS0,9600 " \
+ "mtdparts=phys:7808k(root),128k(env),256k(uboot);" \
+ "bootp;bootm"
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 555316f..48251f3 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -318,7 +318,7 @@
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
/* buffers & descriptors */
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
@@ -417,7 +417,7 @@
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
- /* Print Buffer Size */
+ /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@@ -443,7 +443,7 @@
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
/* CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT
diff --git a/include/configs/shannon.h b/include/configs/shannon.h
index c1fa53f..8bbc730 100644
--- a/include/configs/shannon.h
+++ b/include/configs/shannon.h
@@ -83,7 +83,7 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200"
+#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200"
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_BOOTCOMMAND "help"
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
index 05f6053..ac1642e 100644
--- a/include/configs/smdk2400.h
+++ b/include/configs/smdk2400.h
@@ -114,17 +114,9 @@
#define CONFIG_BOOTDELAY 3
-#if 0
-#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600"
-#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
-#endif
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 134.98.93.36
#define CONFIG_SERVERIP 134.98.93.22
-#if 0
-#define CONFIG_BOOTFILE "elinos-lart"
-#define CONFIG_BOOTCOMMAND "tftp; bootm"
-#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index 18a036c..efe4693 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -93,7 +93,7 @@
#define CONFIG_BOOTDELAY 3
-/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
+/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.0.0.110
diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
index 4578cae..3e47eb8 100644
--- a/include/configs/smmaco4.h
+++ b/include/configs/smmaco4.h
@@ -42,6 +42,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
new file mode 100644
index 0000000..6dc9eff
--- /dev/null
+++ b/include/configs/socrates.h
@@ -0,0 +1,423 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Wolfgang Denk <wd@denx.de>
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Socrates
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
+#define CONFIG_MPC8544 1
+#define CONFIG_SOCRATES 1
+
+#define CONFIG_PCI
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ * 33000000
+ * 66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz. In any event, this value
+ * must match the settings of some switches. Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ 66666666
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00000000
+#define CFG_MEMTEST_END 0x10000000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+
+#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
+
+/* Hardcoded values, to use instead of SPD */
+#define CFG_DDR_CS0_BNDS 0x0000000f
+#define CFG_DDR_CS0_CONFIG 0x80010102
+#define CFG_DDR_TIMING_0 0x00260802
+#define CFG_DDR_TIMING_1 0x3935D322
+#define CFG_DDR_TIMING_2 0x14904CC8
+#define CFG_DDR_MODE 0x00480432
+#define CFG_DDR_INTERVAL 0x030C0100
+#define CFG_DDR_CONFIG_2 0x04400000
+#define CFG_DDR_CONFIG 0xC3008000
+#define CFG_DDR_CLK_CONTROL 0x03800000
+#define CFG_SDRAM_SIZE 256 /* in Megs */
+
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/
+#define SPD_EEPROM_ADDRESS 0x50 /* DDR DIMM */
+#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
+
+/*
+ * Flash on the Local Bus
+ */
+/*
+ * Flash on the LocalBus
+ */
+#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
+
+#define CFG_FLASH0 0xFE000000
+#define CFG_FLASH1 0xFC000000
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
+
+#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
+#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
+
+#define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */
+#define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */
+#define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */
+#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */
+
+#define CFG_FLASH_CFI /* flash is CFI compat. */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
+
+#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
+#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+
+/* I2C RTC */
+#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
+#define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */
+
+/* I2C temp sensor */
+/* Socrates uses Maxim's DS75, which is compatible with LM75 */
+#define CONFIG_DTT_LM75 1
+#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP 125
+#define CFG_DTT_LOW_TEMP -55
+#define CFG_DTT_HYSTERESIS 3
+#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+
+/* RapidIO MMU */
+#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1.
+ */
+#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
+
+/* PCI is clocked by the external source at 33 MHz */
+#define CONFIG_PCI_CLK_FREQ 33000000
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0xE2000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#define CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "TSEC1"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC3_PHY_ADDR 1
+
+#define TSEC1_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC3_FLAGS TSEC_GIGABIT
+
+/* Options are: TSEC[0,1] */
+#define CONFIG_ETHPRIME "TSEC0"
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_TIMESTAMP /* Print image info with ts */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+
+#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
+
+#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootfile=$hostname/uImage\0" \
+ "netdev=eth0\0" \
+ "consdev=ttyS0\0" \
+ "hostname=socrates\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $bootargs " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
+ ":$hostname:$netdev:off panic=1\0" \
+ "addcons=setenv bootargs $bootargs " \
+ "console=$consdev,$baudrate\0" \
+ "flash_self=run ramargs addip addcons;" \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+ "flash_nfs=run nfsargs addip addcons;" \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "tftp ${fdt_addr_r} ${fdt_file}; " \
+ "run nfsargs addip addcons;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "fdt_file=$hostname/socrates.dtb\0" \
+ "fdt_addr_r=B00000\0" \
+ "fdt_addr=FC1E0000\0" \
+ "rootpath=/opt/eldk/ppc_85xx\0" \
+ "kernel_addr=FC000000\0" \
+ "kernel_addr_r=200000\0" \
+ "ramdisk_addr=FC200000\0" \
+ "ramdisk_addr_r=400000\0" \
+ "load=tftp 100000 $hostname/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* USB support */
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_PCI_OHCI 1
+#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
+#define CFG_OHCI_SWAP_REG_ACCESS 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_USB_STORAGE 1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
index b622a30..18f5533 100644
--- a/include/configs/sorcery.h
+++ b/include/configs/sorcery.h
@@ -31,6 +31,8 @@
#define CONFIG_MPC8220 1
#define CONFIG_SORCERY 1 /* Sorcery board */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
determine the CPU speed. */
#define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */
@@ -189,7 +191,7 @@
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
CFG_FLASH_BASE+0x04000000 } /* two banks */
/*
@@ -243,12 +245,12 @@
/* SDRAM configuration (for SPD) */
#define CFG_SDRAM_TOTAL_BANKS 1
-#define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
+#define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
#define CFG_SDRAM_SPD_SIZE 0x100
-#define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
+#define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
/* SDRAM drive strength register (for SSTL_2 class II)*/
-#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
+#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
(DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
(DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
(DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
@@ -285,7 +287,7 @@
#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
#if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index 49213dc..69d2d67 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -44,6 +44,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index fc5d0cc..ec04a30 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -42,8 +42,8 @@
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
-#undef CONFIG_PCI /* pci ethernet support */
-#define CONFIG_TSEC_ENET /* tsec ethernet support*/
+#undef CONFIG_PCI /* pci ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support*/
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
@@ -100,7 +100,7 @@
#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
#define CFG_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
@@ -109,9 +109,9 @@
#endif
#ifdef CFG_RAMBOOT
-#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
+#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
#else
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#endif
#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
@@ -129,14 +129,14 @@
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
+#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
#undef CONFIG_CLOCKS_IN_MHZ
/* local bus definitions */
#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
#define CFG_OR2_PRELIM 0xfc006901
-#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
+#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
#define CFG_LBC_LBCR 0x00000000
#define CFG_LBC_LSRT 0x20000000
#define CFG_LBC_MRTPR 0x20000000
@@ -147,23 +147,23 @@
#define CFG_LBC_LSDMR_5 0x4061b723
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
+#define CONFIG_CONS_ON_SCC /* define if console on SCC */
+#undef CONFIG_CONS_NONE /* define if console on something else */
+#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
-#define CONFIG_BAUDRATE 38400
+#define CONFIG_BAUDRATE 38400
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
@@ -205,18 +205,18 @@
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x01000000 /* 16 M */
-#if defined(CONFIG_PCI) /* PCI Ethernet card */
+#if defined(CONFIG_PCI) /* PCI Ethernet card */
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#undef CONFIG_PCI_SCAN_SHOW
@@ -227,7 +227,7 @@
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
@@ -270,7 +270,7 @@
#elif (CONFIG_ETHER_INDEX == 3)
/* need more definitions here for FE3 */
#define FETH3_RST 0x80
-#endif /* CONFIG_ETHER_INDEX */
+#endif /* CONFIG_ETHER_INDEX */
/* MDIO is done through the TSEC0 control.
*/
@@ -375,20 +375,20 @@
/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
+#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
+#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
+#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
#endif
-#define CONFIG_SERVERIP 192.168.85.1
-#define CONFIG_IPADDR 192.168.85.60
+#define CONFIG_SERVERIP 192.168.85.1
+#define CONFIG_IPADDR 192.168.85.60
#define CONFIG_GATEWAYIP 192.168.85.1
#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_HOSTNAME STX_GP3
-#define CONFIG_ROOTPATH /gppproot
-#define CONFIG_BOOTFILE uImage
+#define CONFIG_HOSTNAME STX_GP3
+#define CONFIG_ROOTPATH /gppproot
+#define CONFIG_BOOTFILE uImage
#define CONFIG_LOADADDR 0x1000000
#endif /* __CONFIG_H */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 15f690a..d033c86 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -69,10 +69,10 @@
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#undef CFG_DRAM_TEST /* memory test, takes time */
-#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
@@ -232,7 +232,7 @@
#define CFG_PCI2_IO_PHYS 0xe3000000
#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
-#if defined(CONFIG_PCI) /* PCI Ethernet card */
+#if defined(CONFIG_PCI) /* PCI Ethernet card */
#define CONFIG_MPC85XX_PCI2 1
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
@@ -428,13 +428,13 @@
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
-#define CONFIG_SERVERIP 192.168.85.1
+#define CONFIG_SERVERIP 192.168.85.1
#define CONFIG_IPADDR 192.168.85.60
#define CONFIG_GATEWAYIP 192.168.85.1
#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_HOSTNAME STX_SSA
-#define CONFIG_ROOTPATH /gppproot
-#define CONFIG_BOOTFILE uImage
+#define CONFIG_HOSTNAME STX_SSA
+#define CONFIG_ROOTPATH /gppproot
+#define CONFIG_BOOTFILE uImage
#define CONFIG_LOADADDR 0x1000000
#else /* ENV IS IN FLASH -- use a full-blown envionment */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index a3ab798..97a1032 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -63,9 +63,9 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "tftpboot; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_AUTOSCRIPT
@@ -93,7 +93,7 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
+#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
#define FEC_ENET 1 /* eth.c needs it that way... */
#undef CFG_DISCOVER_PHY
#define CONFIG_MII 1
@@ -101,7 +101,7 @@
#undef CONFIG_RMII
#define CONFIG_ETHER_ON_FEC1 1
-#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
+#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
#undef CONFIG_FEC1_PHY_NORXERR
#define CONFIG_ETHER_ON_FEC2 1
@@ -214,7 +214,7 @@
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
-#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
+#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
@@ -283,11 +283,11 @@
#if MPC8XX_HZ == 50000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 66666666
#define CFG_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 10MHz
#endif
@@ -462,7 +462,7 @@
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
index 3b90f3c..70336b5 100644
--- a/include/configs/svm_sc8xx.h
+++ b/include/configs/svm_sc8xx.h
@@ -68,7 +68,7 @@
#undef CONFIG_WATCHDOG /* watchdog */
-#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */
+#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */
#ifdef CONFIG_LCD /* with LCD controller ? */
/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
@@ -109,8 +109,8 @@
"ramdisk_addr=48100000\0" \
""
#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@@ -363,14 +363,14 @@
*-----------------------------------------------------------------------
*/
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#define CFG_ATA_BASE_ADDR 0xFE100010
#define CFG_ATA_IDE0_OFFSET 0x0000
diff --git a/include/configs/taihu.h b/include/configs/taihu.h
index 8a1ff1a..c060b1e 100644
--- a/include/configs/taihu.h
+++ b/include/configs/taihu.h
@@ -363,7 +363,7 @@ unsigned char spi_read(void);
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
-{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
diff --git a/include/configs/trab.h b/include/configs/trab.h
index b9088a8..de36fca 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -69,8 +69,8 @@
* address 0x54 with 8bit addressing
***********************************************************/
#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CFG_I2C_SPEED 100000 /* I2C speed */
-#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */
+#define CFG_I2C_SPEED 100000 /* I2C speed */
+#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */
#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM address */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* 1 address byte */
@@ -237,7 +237,7 @@
"mdm_init2=ATS0=1\0" \
"mdm_flow_control=rts/cts\0"
#endif /* CFG_HUSH_PARSER */
-#else /* CONFIG_FLASH_8MB => 8 MB flash */
+#else /* CONFIG_FLASH_8MB => 8 MB flash */
#ifdef CFG_HUSH_PARSER
#define CONFIG_EXTRA_ENV_SETTINGS \
"nfs_args=setenv bootargs root=/dev/nfs rw " \
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 7a15d97..25155ad 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -303,7 +303,7 @@
#define CFG_MONITOR_LEN 0x40000
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
@@ -314,8 +314,8 @@
/* Flash environment locations */
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */
-#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */
+#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */
#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
diff --git a/include/configs/uc100.h b/include/configs/uc100.h
index 3c2de40..e74b1bb 100644
--- a/include/configs/uc100.h
+++ b/include/configs/uc100.h
@@ -243,7 +243,7 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN)
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
diff --git a/include/configs/uc101.h b/include/configs/uc101.h
index dc1d7e1..042750e 100644
--- a/include/configs/uc101.h
+++ b/include/configs/uc101.h
@@ -40,6 +40,8 @@
#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
index cd00c49..287a618 100644
--- a/include/configs/utx8245.h
+++ b/include/configs/utx8245.h
@@ -58,7 +58,7 @@
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_BOOTDELAY 2
-#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */
@@ -255,7 +255,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
mem_freq = 100MHz */
#define CFG_BANK7_ROW 0 /* SDRAM bank 7-0 row address */
-#define CFG_BANK6_ROW 0 /* bit count */
+#define CFG_BANK6_ROW 0 /* bit count */
#define CFG_BANK5_ROW 0
#define CFG_BANK4_ROW 0
#define CFG_BANK3_ROW 0
@@ -278,7 +278,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
#define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */
#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */
-#define CFG_ACTORW 2 /* trcd min */
+#define CFG_ACTORW 2 /* trcd min */
#define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
#define CFG_REGISTERD_TYPE_BUFFER 1
#define CFG_EXTROM 0 /* we don't need extended ROM space */
diff --git a/include/configs/v37.h b/include/configs/v37.h
index 47851c2..751d702 100644
--- a/include/configs/v37.h
+++ b/include/configs/v37.h
@@ -34,7 +34,7 @@
*/
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
-#define CONFIG_V37 1 /* ...on a Marel V37 board */
+#define CONFIG_V37 1 /* ...on a Marel V37 board */
#define CONFIG_LCD
#define CONFIG_SHARP_LQ084V1DG21
@@ -63,10 +63,10 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
+ "tftpboot; " \
"setenv bootargs console=tty0 " \
- "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@@ -333,7 +333,7 @@
#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
-#define CFG_OR_TIMING_FLASH 0xF56
+#define CFG_OR_TIMING_FLASH 0xF56
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index e24d6f7..c203522 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -46,6 +46,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
/*
* Serial console configuration
*/
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
index d250150..a88d356 100644
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -80,7 +80,7 @@
#define CONFIG_DRIVER_SMC91111
#define CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC91111_BASE 0x10010000
+#define CONFIG_SMC91111_BASE 0x10010000
#undef CONFIG_SMC91111_EXT_PHY
/*
diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h
index c67b301..f2efe9f 100644
--- a/include/configs/wepep250.h
+++ b/include/configs/wepep250.h
@@ -132,9 +132,9 @@
/*
* Configuration for FLASH memory
*/
-#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
-#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
-#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */
+#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
+#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
+#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */
#define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */
#define WEP_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank*/
#define WEP_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 7418986..dc0ee0b2 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -97,7 +97,7 @@
#define CONFIG_BOOTCOMMAND "bootm 0x00100000"
#define CONFIG_BOOTARGS "console=ttyS1,115200"
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h
index c738567..570d6a8 100644
--- a/include/configs/xupv2p.h
+++ b/include/configs/xupv2p.h
@@ -124,7 +124,7 @@
* 0x3FFB_F000 CFG_MONITOR_BASE
* MONITOR_CODE 256kB Env
* 0x3FFF_F000 CFG_GBL_DATA_OFFSET
- * GLOBAL_DATA 4kB bd, gd
+ * GLOBAL_DATA 4kB bd, gd
* 0x4000_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
*/
@@ -194,13 +194,13 @@
#define CFG_LONGHELP
#define CFG_LOAD_ADDR 0x12000000 /* default load address */
-#define CONFIG_BOOTDELAY 30
+#define CONFIG_BOOTDELAY 30
#define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_HOSTNAME "xupv2p"
-#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
+#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
#define CONFIG_IPADDR 192.168.0.3
-#define CONFIG_SERVERIP 192.168.0.5
-#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.5
+#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
/* architecture dependent code */
diff --git a/include/div64.h b/include/div64.h
index 2e0ba83..c495aef 100644
--- a/include/div64.h
+++ b/include/div64.h
@@ -8,9 +8,9 @@
*
* uint32_t do_div(uint64_t *n, uint32_t base)
* {
- * uint32_t remainder = *n % base;
- * *n = *n / base;
- * return remainder;
+ * uint32_t remainder = *n % base;
+ * *n = *n / base;
+ * return remainder;
* }
*
* NOTE: macro parameter n is evaluated multiple times,
@@ -31,7 +31,7 @@ extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
if (((n) >> 32) == 0) { \
__rem = (uint32_t)(n) % __base; \
(n) = (uint32_t)(n) / __base; \
- } else \
+ } else \
__rem = __div64_32(&(n), __base); \
__rem; \
})
diff --git a/include/dm9161.h b/include/dm9161.h
index d5d0e8d..218f15c 100644
--- a/include/dm9161.h
+++ b/include/dm9161.h
@@ -15,7 +15,7 @@
/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */
-#define DM9161_BMCR 0 /* Basic Mode Control Register */
+#define DM9161_BMCR 0 /* Basic Mode Control Register */
#define DM9161_BMSR 1 /* Basic Mode Status Register */
#define DM9161_PHYID1 2 /* PHY Idendifier Register 1 */
#define DM9161_PHYID2 3 /* PHY Idendifier Register 2 */
@@ -32,7 +32,7 @@
/* --Bit definitions: DM9161_BMCR */
-#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
+#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
#define DM9161_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */
#define DM9161_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */
#define DM9161_AUTONEG (1 << 12)
diff --git a/include/elf.h b/include/elf.h
index d0febc5..a9839df 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -43,9 +43,9 @@
#include <stdint.h>
#elif defined(__WIN32__)
#include <unistd.h>
-typedef unsigned char uint8_t;
-typedef unsigned short uint16_t;
-typedef unsigned int uint32_t;
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int uint32_t;
#endif
/*
@@ -415,7 +415,7 @@ typedef struct
/* Extract relocation info - r_info */
#define ELF32_R_SYM(i) ((i) >> 8)
#define ELF32_R_TYPE(i) ((unsigned char) (i))
-#define ELF32_R_INFO(s,t) (((s) << 8) + (unsigned char)(t))
+#define ELF32_R_INFO(s,t) (((s) << 8) + (unsigned char)(t))
/* Program Header */
typedef struct {
diff --git a/include/fat.h b/include/fat.h
index f993cca..59de3fb 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -101,7 +101,7 @@
#else
#define FAT2CPU16(x) ((((x) & 0x00ff) << 8) | (((x) & 0xff00) >> 8))
#define FAT2CPU32(x) ((((x) & 0x000000ff) << 24) | \
- (((x) & 0x0000ff00) << 8) | \
+ (((x) & 0x0000ff00) << 8) | \
(((x) & 0x00ff0000) >> 8) | \
(((x) & 0xff000000) >> 24))
#endif
diff --git a/include/flash.h b/include/flash.h
index 2ed1e20..af8a7c0 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -51,10 +51,10 @@ typedef struct {
ushort device_id2; /* extended device id */
ushort ext_addr; /* extended query table address */
ushort cfi_version; /* cfi version */
- ushort cfi_offset; /* offset for cfi query */
+ ushort cfi_offset; /* offset for cfi query */
ulong addr_unlock1; /* unlock address 1 for AMD flash roms */
ulong addr_unlock2; /* unlock address 2 for AMD flash roms */
- const char *name; /* human-readable name */
+ const char *name; /* human-readable name */
#endif
} flash_info_t;
diff --git a/include/fpga.h b/include/fpga.h
index a038aa1..52d93b1 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -22,7 +22,7 @@
*
*/
-#include <linux/types.h> /* for ulong typedef */
+#include <linux/types.h> /* for ulong typedef */
#ifndef _FPGA_H_
#define _FPGA_H_
@@ -33,41 +33,41 @@
/* these probably belong somewhere else */
#ifndef FALSE
-#define FALSE (0)
+#define FALSE (0)
#endif
#ifndef TRUE
-#define TRUE (!FALSE)
+#define TRUE (!FALSE)
#endif
/* CONFIG_FPGA bit assignments */
-#define CFG_FPGA_MAN(x) (x)
-#define CFG_FPGA_DEV(x) ((x) << 8 )
-#define CFG_FPGA_IF(x) ((x) << 16 )
+#define CFG_FPGA_MAN(x) (x)
+#define CFG_FPGA_DEV(x) ((x) << 8 )
+#define CFG_FPGA_IF(x) ((x) << 16 )
/* FPGA Manufacturer bits in CONFIG_FPGA */
-#define CFG_FPGA_XILINX CFG_FPGA_MAN( 0x1 )
-#define CFG_FPGA_ALTERA CFG_FPGA_MAN( 0x2 )
+#define CFG_FPGA_XILINX CFG_FPGA_MAN( 0x1 )
+#define CFG_FPGA_ALTERA CFG_FPGA_MAN( 0x2 )
/* fpga_xxxx function return value definitions */
-#define FPGA_SUCCESS 0
-#define FPGA_FAIL -1
+#define FPGA_SUCCESS 0
+#define FPGA_FAIL -1
/* device numbers must be non-negative */
-#define FPGA_INVALID_DEVICE -1
+#define FPGA_INVALID_DEVICE -1
/* root data type defintions */
-typedef enum { /* typedef fpga_type */
- fpga_min_type, /* range check value */
- fpga_xilinx, /* Xilinx Family) */
- fpga_altera, /* unimplemented */
- fpga_undefined /* invalid range check value */
-} fpga_type; /* end, typedef fpga_type */
+typedef enum { /* typedef fpga_type */
+ fpga_min_type, /* range check value */
+ fpga_xilinx, /* Xilinx Family) */
+ fpga_altera, /* unimplemented */
+ fpga_undefined /* invalid range check value */
+} fpga_type; /* end, typedef fpga_type */
-typedef struct { /* typedef fpga_desc */
- fpga_type devtype; /* switch value to select sub-functions */
- void * devdesc; /* real device descriptor */
-} fpga_desc; /* end, typedef fpga_desc */
+typedef struct { /* typedef fpga_desc */
+ fpga_type devtype; /* switch value to select sub-functions */
+ void *devdesc; /* real device descriptor */
+} fpga_desc; /* end, typedef fpga_desc */
/* root function definitions */
diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h
index ebf087a..c2cfb06 100644
--- a/include/galileo/gt64260R.h
+++ b/include/galileo/gt64260R.h
@@ -14,154 +14,154 @@
#define CPU_MASTER_CONTROL 0x160
/****************************************/
-/* Processor Address Space */
+/* Processor Address Space */
/****************************************/
/* Sdram's BAR'S */
-#define SCS_0_LOW_DECODE_ADDRESS 0x008
-#define SCS_0_HIGH_DECODE_ADDRESS 0x010
-#define SCS_1_LOW_DECODE_ADDRESS 0x208
-#define SCS_1_HIGH_DECODE_ADDRESS 0x210
-#define SCS_2_LOW_DECODE_ADDRESS 0x018
-#define SCS_2_HIGH_DECODE_ADDRESS 0x020
-#define SCS_3_LOW_DECODE_ADDRESS 0x218
-#define SCS_3_HIGH_DECODE_ADDRESS 0x220
+#define SCS_0_LOW_DECODE_ADDRESS 0x008
+#define SCS_0_HIGH_DECODE_ADDRESS 0x010
+#define SCS_1_LOW_DECODE_ADDRESS 0x208
+#define SCS_1_HIGH_DECODE_ADDRESS 0x210
+#define SCS_2_LOW_DECODE_ADDRESS 0x018
+#define SCS_2_HIGH_DECODE_ADDRESS 0x020
+#define SCS_3_LOW_DECODE_ADDRESS 0x218
+#define SCS_3_HIGH_DECODE_ADDRESS 0x220
/* Devices BAR'S */
-#define CS_0_LOW_DECODE_ADDRESS 0x028
-#define CS_0_HIGH_DECODE_ADDRESS 0x030
-#define CS_1_LOW_DECODE_ADDRESS 0x228
-#define CS_1_HIGH_DECODE_ADDRESS 0x230
-#define CS_2_LOW_DECODE_ADDRESS 0x248
-#define CS_2_HIGH_DECODE_ADDRESS 0x250
-#define CS_3_LOW_DECODE_ADDRESS 0x038
-#define CS_3_HIGH_DECODE_ADDRESS 0x040
-#define BOOTCS_LOW_DECODE_ADDRESS 0x238
-#define BOOTCS_HIGH_DECODE_ADDRESS 0x240
-
-#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
-#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
-#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
-#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
-#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
-#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
-#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
-#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
-#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
-#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
-
-#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
-#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
-#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
-#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
-#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
-#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
-#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
-#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
-#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
-#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
+#define CS_0_LOW_DECODE_ADDRESS 0x028
+#define CS_0_HIGH_DECODE_ADDRESS 0x030
+#define CS_1_LOW_DECODE_ADDRESS 0x228
+#define CS_1_HIGH_DECODE_ADDRESS 0x230
+#define CS_2_LOW_DECODE_ADDRESS 0x248
+#define CS_2_HIGH_DECODE_ADDRESS 0x250
+#define CS_3_LOW_DECODE_ADDRESS 0x038
+#define CS_3_HIGH_DECODE_ADDRESS 0x040
+#define BOOTCS_LOW_DECODE_ADDRESS 0x238
+#define BOOTCS_HIGH_DECODE_ADDRESS 0x240
+
+#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
+#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
+#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
+#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
+#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
+#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
+#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
+#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
+#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
+#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
+
+#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
+#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
+#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
+#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
+#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
+#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
+#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
+#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
+#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
+#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
-#define INTERNAL_SPACE_DECODE 0x068
+#define INTERNAL_SPACE_DECODE 0x068
-#define CPU_0_LOW_DECODE_ADDRESS 0x290
-#define CPU_0_HIGH_DECODE_ADDRESS 0x298
-#define CPU_1_LOW_DECODE_ADDRESS 0x2c0
-#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
+#define CPU_0_LOW_DECODE_ADDRESS 0x290
+#define CPU_0_HIGH_DECODE_ADDRESS 0x298
+#define CPU_1_LOW_DECODE_ADDRESS 0x2c0
+#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
-#define PCI_0I_O_ADDRESS_REMAP 0x0f0
-#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
-#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
-#define PCI_0MEMORY1_ADDRESS_REMAP 0x100
-#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
-#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
-#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
-#define PCI_0MEMORY3_ADDRESS_REMAP 0x300
-#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
+#define PCI_0I_O_ADDRESS_REMAP 0x0f0
+#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
+#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
+#define PCI_0MEMORY1_ADDRESS_REMAP 0x100
+#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
+#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
+#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
+#define PCI_0MEMORY3_ADDRESS_REMAP 0x300
+#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
-#define PCI_1I_O_ADDRESS_REMAP 0x108
-#define PCI_1MEMORY0_ADDRESS_REMAP 0x110
-#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
-#define PCI_1MEMORY1_ADDRESS_REMAP 0x118
-#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
-#define PCI_1MEMORY2_ADDRESS_REMAP 0x310
-#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
-#define PCI_1MEMORY3_ADDRESS_REMAP 0x318
-#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
+#define PCI_1I_O_ADDRESS_REMAP 0x108
+#define PCI_1MEMORY0_ADDRESS_REMAP 0x110
+#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
+#define PCI_1MEMORY1_ADDRESS_REMAP 0x118
+#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
+#define PCI_1MEMORY2_ADDRESS_REMAP 0x310
+#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
+#define PCI_1MEMORY3_ADDRESS_REMAP 0x318
+#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
/****************************************/
-/* CPU Sync Barrier */
+/* CPU Sync Barrier */
/****************************************/
-#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0
-#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8
+#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0
+#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8
/****************************************/
-/* CPU Access Protect */
+/* CPU Access Protect */
/****************************************/
-#define CPU_LOW_PROTECT_ADDRESS_0 0x180
-#define CPU_HIGH_PROTECT_ADDRESS_0 0x188
-#define CPU_LOW_PROTECT_ADDRESS_1 0x190
-#define CPU_HIGH_PROTECT_ADDRESS_1 0x198
-#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0
-#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8
-#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0
-#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8
-#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0
-#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8
-#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0
-#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8
-#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0
-#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8
-#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0
-#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8
+#define CPU_LOW_PROTECT_ADDRESS_0 0x180
+#define CPU_HIGH_PROTECT_ADDRESS_0 0x188
+#define CPU_LOW_PROTECT_ADDRESS_1 0x190
+#define CPU_HIGH_PROTECT_ADDRESS_1 0x198
+#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0
+#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8
+#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0
+#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8
+#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0
+#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8
+#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0
+#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8
+#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0
+#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8
+#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0
+#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8
/****************************************/
-/* Snoop Control */
+/* Snoop Control */
/****************************************/
-#define SNOOP_BASE_ADDRESS_0 0x380
-#define SNOOP_TOP_ADDRESS_0 0x388
-#define SNOOP_BASE_ADDRESS_1 0x390
-#define SNOOP_TOP_ADDRESS_1 0x398
-#define SNOOP_BASE_ADDRESS_2 0x3a0
-#define SNOOP_TOP_ADDRESS_2 0x3a8
-#define SNOOP_BASE_ADDRESS_3 0x3b0
-#define SNOOP_TOP_ADDRESS_3 0x3b8
+#define SNOOP_BASE_ADDRESS_0 0x380
+#define SNOOP_TOP_ADDRESS_0 0x388
+#define SNOOP_BASE_ADDRESS_1 0x390
+#define SNOOP_TOP_ADDRESS_1 0x398
+#define SNOOP_BASE_ADDRESS_2 0x3a0
+#define SNOOP_TOP_ADDRESS_2 0x3a8
+#define SNOOP_BASE_ADDRESS_3 0x3b0
+#define SNOOP_TOP_ADDRESS_3 0x3b8
/****************************************/
-/* CPU Error Report */
+/* CPU Error Report */
/****************************************/
-#define CPU_ERROR_ADDRESS_LOW 0x070
-#define CPU_ERROR_ADDRESS_HIGH 0x078
-#define CPU_ERROR_DATA_LOW 0x128
-#define CPU_ERROR_DATA_HIGH 0x130
-#define CPU_ERROR_PARITY 0x138
-#define CPU_ERROR_CAUSE 0x140
-#define CPU_ERROR_MASK 0x148
+#define CPU_ERROR_ADDRESS_LOW 0x070
+#define CPU_ERROR_ADDRESS_HIGH 0x078
+#define CPU_ERROR_DATA_LOW 0x128
+#define CPU_ERROR_DATA_HIGH 0x130
+#define CPU_ERROR_PARITY 0x138
+#define CPU_ERROR_CAUSE 0x140
+#define CPU_ERROR_MASK 0x148
/****************************************/
-/* Pslave Debug */
+/* Pslave Debug */
/****************************************/
-#define X_0_ADDRESS 0x360
-#define X_0_COMMAND_ID 0x368
-#define X_1_ADDRESS 0x370
-#define X_1_COMMAND_ID 0x378
-#define WRITE_DATA_LOW 0x3c0
-#define WRITE_DATA_HIGH 0x3c8
-#define WRITE_BYTE_ENABLE 0x3e0
-#define READ_DATA_LOW 0x3d0
-#define READ_DATA_HIGH 0x3d8
-#define READ_ID 0x3e8
+#define X_0_ADDRESS 0x360
+#define X_0_COMMAND_ID 0x368
+#define X_1_ADDRESS 0x370
+#define X_1_COMMAND_ID 0x378
+#define WRITE_DATA_LOW 0x3c0
+#define WRITE_DATA_HIGH 0x3c8
+#define WRITE_BYTE_ENABLE 0x3e0
+#define READ_DATA_LOW 0x3d0
+#define READ_DATA_HIGH 0x3d8
+#define READ_ID 0x3e8
/****************************************/
-/* SDRAM and Device Address Space */
+/* SDRAM and Device Address Space */
/****************************************/
@@ -191,1004 +191,1004 @@
/****************************************/
-/* SDRAM Error Report */
+/* SDRAM Error Report */
/****************************************/
-#define SDRAM_ERROR_DATA_LOW 0x484
-#define SDRAM_ERROR_DATA_HIGH 0x480
-#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490
-#define SDRAM_RECEIVED_ECC 0x488
-#define SDRAM_CALCULATED_ECC 0x48c
-#define SDRAM_ECC_CONTROL 0x494
-#define SDRAM_ECC_ERROR_COUNTER 0x498
+#define SDRAM_ERROR_DATA_LOW 0x484
+#define SDRAM_ERROR_DATA_HIGH 0x480
+#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490
+#define SDRAM_RECEIVED_ECC 0x488
+#define SDRAM_CALCULATED_ECC 0x48c
+#define SDRAM_ECC_CONTROL 0x494
+#define SDRAM_ECC_ERROR_COUNTER 0x498
/****************************************/
/* SDunit Debug (for internal use) */
/****************************************/
-#define X0_ADDRESS 0x500
-#define X0_COMMAND_AND_ID 0x504
-#define X0_WRITE_DATA_LOW 0x508
-#define X0_WRITE_DATA_HIGH 0x50c
-#define X0_WRITE_BYTE_ENABLE 0x518
-#define X0_READ_DATA_LOW 0x510
-#define X0_READ_DATA_HIGH 0x514
-#define X0_READ_ID 0x51c
-#define X1_ADDRESS 0x520
-#define X1_COMMAND_AND_ID 0x524
-#define X1_WRITE_DATA_LOW 0x528
-#define X1_WRITE_DATA_HIGH 0x52c
-#define X1_WRITE_BYTE_ENABLE 0x538
-#define X1_READ_DATA_LOW 0x530
-#define X1_READ_DATA_HIGH 0x534
-#define X1_READ_ID 0x53c
-#define X0_SNOOP_ADDRESS 0x540
-#define X0_SNOOP_COMMAND 0x544
-#define X1_SNOOP_ADDRESS 0x548
-#define X1_SNOOP_COMMAND 0x54c
-
-
-/****************************************/
-/* Device Parameters */
-/****************************************/
-
-#define DEVICE_BANK0PARAMETERS 0x45c
-#define DEVICE_BANK1PARAMETERS 0x460
-#define DEVICE_BANK2PARAMETERS 0x464
-#define DEVICE_BANK3PARAMETERS 0x468
-#define DEVICE_BOOT_BANK_PARAMETERS 0x46c
-#define DEVICE_CONTROL 0x4c0
-#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
-#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
-#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
-
-
-/****************************************/
-/* Device Interrupt */
-/****************************************/
-
-#define DEVICE_INTERRUPT_CAUSE 0x4d0
-#define DEVICE_INTERRUPT_MASK 0x4d4
-#define DEVICE_ERROR_ADDRESS 0x4d8
-
-/****************************************/
-/* DMA Record */
-/****************************************/
-
-#define CHANNEL0_DMA_BYTE_COUNT 0x800
-#define CHANNEL1_DMA_BYTE_COUNT 0x804
-#define CHANNEL2_DMA_BYTE_COUNT 0x808
-#define CHANNEL3_DMA_BYTE_COUNT 0x80C
-#define CHANNEL4_DMA_BYTE_COUNT 0x900
-#define CHANNEL5_DMA_BYTE_COUNT 0x904
-#define CHANNEL6_DMA_BYTE_COUNT 0x908
-#define CHANNEL7_DMA_BYTE_COUNT 0x90C
-#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
-#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
-#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
-#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
-#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910
-#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914
-#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918
-#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C
-#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
-#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
-#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
-#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
-#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920
-#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924
-#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928
-#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C
-#define CHANNEL0NEXT_RECORD_POINTER 0x830
-#define CHANNEL1NEXT_RECORD_POINTER 0x834
-#define CHANNEL2NEXT_RECORD_POINTER 0x838
-#define CHANNEL3NEXT_RECORD_POINTER 0x83C
-#define CHANNEL4NEXT_RECORD_POINTER 0x930
-#define CHANNEL5NEXT_RECORD_POINTER 0x934
-#define CHANNEL6NEXT_RECORD_POINTER 0x938
-#define CHANNEL7NEXT_RECORD_POINTER 0x93C
-#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
-#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
-#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
-#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
-#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970
-#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974
-#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978
-#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C
-#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890
-#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894
-#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898
-#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c
-#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990
-#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994
-#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998
-#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c
-#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0
-#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4
-#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8
-#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac
-#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0
-#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4
-#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8
-#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac
-#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0
-#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4
-#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8
-#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc
-#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0
-#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4
-#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8
-#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc
-
-/****************************************/
-/* DMA Channel Control */
-/****************************************/
-
-#define CHANNEL0CONTROL 0x840
-#define CHANNEL0CONTROL_HIGH 0x880
-#define CHANNEL1CONTROL 0x844
-#define CHANNEL1CONTROL_HIGH 0x884
-#define CHANNEL2CONTROL 0x848
-#define CHANNEL2CONTROL_HIGH 0x888
-#define CHANNEL3CONTROL 0x84C
-#define CHANNEL3CONTROL_HIGH 0x88C
-
-#define CHANNEL4CONTROL 0x940
-#define CHANNEL4CONTROL_HIGH 0x980
-#define CHANNEL5CONTROL 0x944
-#define CHANNEL5CONTROL_HIGH 0x984
-#define CHANNEL6CONTROL 0x948
-#define CHANNEL6CONTROL_HIGH 0x988
-#define CHANNEL7CONTROL 0x94C
-#define CHANNEL7CONTROL_HIGH 0x98C
-
-
-/****************************************/
-/* DMA Arbiter */
-/****************************************/
-
-#define ARBITER_CONTROL_0_3 0x860
-#define ARBITER_CONTROL_4_7 0x960
-
-
-/****************************************/
-/* DMA Interrupt */
-/****************************************/
-
-#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
-#define CHANELS0_3_INTERRUPT_MASK 0x8c4
-#define CHANELS0_3_ERROR_ADDRESS 0x8c8
-#define CHANELS0_3_ERROR_SELECT 0x8cc
-#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0
-#define CHANELS4_7_INTERRUPT_MASK 0x9c4
-#define CHANELS4_7_ERROR_ADDRESS 0x9c8
-#define CHANELS4_7_ERROR_SELECT 0x9cc
-
-
-/****************************************/
-/* DMA Debug (for internal use) */
-/****************************************/
-
-#define DMA_X0_ADDRESS 0x8e0
-#define DMA_X0_COMMAND_AND_ID 0x8e4
-#define DMA_X0_WRITE_DATA_LOW 0x8e8
-#define DMA_X0_WRITE_DATA_HIGH 0x8ec
-#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8
-#define DMA_X0_READ_DATA_LOW 0x8f0
-#define DMA_X0_READ_DATA_HIGH 0x8f4
-#define DMA_X0_READ_ID 0x8fc
-#define DMA_X1_ADDRESS 0x9e0
-#define DMA_X1_COMMAND_AND_ID 0x9e4
-#define DMA_X1_WRITE_DATA_LOW 0x9e8
-#define DMA_X1_WRITE_DATA_HIGH 0x9ec
-#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8
-#define DMA_X1_READ_DATA_LOW 0x9f0
-#define DMA_X1_READ_DATA_HIGH 0x9f4
-#define DMA_X1_READ_ID 0x9fc
-
-/****************************************/
-/* Timer_Counter */
-/****************************************/
-
-#define TIMER_COUNTER0 0x850
-#define TIMER_COUNTER1 0x854
-#define TIMER_COUNTER2 0x858
-#define TIMER_COUNTER3 0x85C
-#define TIMER_COUNTER_0_3_CONTROL 0x864
-#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
-#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
-#define TIMER_COUNTER4 0x950
-#define TIMER_COUNTER5 0x954
-#define TIMER_COUNTER6 0x958
-#define TIMER_COUNTER7 0x95C
-#define TIMER_COUNTER_4_7_CONTROL 0x964
-#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968
-#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c
-
-/****************************************/
-/* PCI Slave Address Decoding */
-/****************************************/
-
-#define PCI_0SCS_0_BANK_SIZE 0xc08
-#define PCI_1SCS_0_BANK_SIZE 0xc88
-#define PCI_0SCS_1_BANK_SIZE 0xd08
-#define PCI_1SCS_1_BANK_SIZE 0xd88
-#define PCI_0SCS_2_BANK_SIZE 0xc0c
-#define PCI_1SCS_2_BANK_SIZE 0xc8c
-#define PCI_0SCS_3_BANK_SIZE 0xd0c
-#define PCI_1SCS_3_BANK_SIZE 0xd8c
-#define PCI_0CS_0_BANK_SIZE 0xc10
-#define PCI_1CS_0_BANK_SIZE 0xc90
-#define PCI_0CS_1_BANK_SIZE 0xd10
-#define PCI_1CS_1_BANK_SIZE 0xd90
-#define PCI_0CS_2_BANK_SIZE 0xd18
-#define PCI_1CS_2_BANK_SIZE 0xd98
-#define PCI_0CS_3_BANK_SIZE 0xc14
-#define PCI_1CS_3_BANK_SIZE 0xc94
-#define PCI_0CS_BOOT_BANK_SIZE 0xd14
-#define PCI_1CS_BOOT_BANK_SIZE 0xd94
-#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
-#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
-#define PCI_0P2P_MEM1_BAR_SIZE 0xd20
-#define PCI_1P2P_MEM1_BAR_SIZE 0xda0
-#define PCI_0P2P_I_O_BAR_SIZE 0xd24
-#define PCI_1P2P_I_O_BAR_SIZE 0xda4
-#define PCI_0CPU_BAR_SIZE 0xd28
-#define PCI_1CPU_BAR_SIZE 0xda8
-#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
-#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
-#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
-#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
-#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
-#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
-#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
-#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
-#define PCI_0DAC_CS_0_BANK_SIZE 0xe10
-#define PCI_1DAC_CS_0_BANK_SIZE 0xe90
-#define PCI_0DAC_CS_1_BANK_SIZE 0xe14
-#define PCI_1DAC_CS_1_BANK_SIZE 0xe94
-#define PCI_0DAC_CS_2_BANK_SIZE 0xe18
-#define PCI_1DAC_CS_2_BANK_SIZE 0xe98
-#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
-#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
-#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
-#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
-#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
-#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
-#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
-#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
-#define PCI_0DAC_CPU_BAR_SIZE 0xe2c
-#define PCI_1DAC_CPU_BAR_SIZE 0xeac
-#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
-#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
-#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
-#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
-#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
-#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
-#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
-#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
-#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
-#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
-#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
-#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
-#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
-#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
-#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
-#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
-#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
-#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
-#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
-#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
-#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
-#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
-#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
-#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
-#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
-#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
-#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
-#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
-#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
-#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
-#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
-#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
-#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
-#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
-#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
-#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
-#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
-#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
-#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
-#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
-#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
-#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
-#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
-#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
-#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
-#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
-#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
-#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
-#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
-#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
-
-/****************************************/
-/* PCI Control */
-/****************************************/
-
-#define PCI_0COMMAND 0xc00
-#define PCI_1COMMAND 0xc80
-#define PCI_0MODE 0xd00
-#define PCI_1MODE 0xd80
-#define PCI_0TIMEOUT_RETRY 0xc04
-#define PCI_1TIMEOUT_RETRY 0xc84
-#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
-#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
-#define MSI_0TRIGGER_TIMER 0xc38
-#define MSI_1TRIGGER_TIMER 0xcb8
-#define PCI_0ARBITER_CONTROL 0x1d00
-#define PCI_1ARBITER_CONTROL 0x1d80
+#define X0_ADDRESS 0x500
+#define X0_COMMAND_AND_ID 0x504
+#define X0_WRITE_DATA_LOW 0x508
+#define X0_WRITE_DATA_HIGH 0x50c
+#define X0_WRITE_BYTE_ENABLE 0x518
+#define X0_READ_DATA_LOW 0x510
+#define X0_READ_DATA_HIGH 0x514
+#define X0_READ_ID 0x51c
+#define X1_ADDRESS 0x520
+#define X1_COMMAND_AND_ID 0x524
+#define X1_WRITE_DATA_LOW 0x528
+#define X1_WRITE_DATA_HIGH 0x52c
+#define X1_WRITE_BYTE_ENABLE 0x538
+#define X1_READ_DATA_LOW 0x530
+#define X1_READ_DATA_HIGH 0x534
+#define X1_READ_ID 0x53c
+#define X0_SNOOP_ADDRESS 0x540
+#define X0_SNOOP_COMMAND 0x544
+#define X1_SNOOP_ADDRESS 0x548
+#define X1_SNOOP_COMMAND 0x54c
+
+
+/****************************************/
+/* Device Parameters */
+/****************************************/
+
+#define DEVICE_BANK0PARAMETERS 0x45c
+#define DEVICE_BANK1PARAMETERS 0x460
+#define DEVICE_BANK2PARAMETERS 0x464
+#define DEVICE_BANK3PARAMETERS 0x468
+#define DEVICE_BOOT_BANK_PARAMETERS 0x46c
+#define DEVICE_CONTROL 0x4c0
+#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
+#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
+#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
+
+
+/****************************************/
+/* Device Interrupt */
+/****************************************/
+
+#define DEVICE_INTERRUPT_CAUSE 0x4d0
+#define DEVICE_INTERRUPT_MASK 0x4d4
+#define DEVICE_ERROR_ADDRESS 0x4d8
+
+/****************************************/
+/* DMA Record */
+/****************************************/
+
+#define CHANNEL0_DMA_BYTE_COUNT 0x800
+#define CHANNEL1_DMA_BYTE_COUNT 0x804
+#define CHANNEL2_DMA_BYTE_COUNT 0x808
+#define CHANNEL3_DMA_BYTE_COUNT 0x80C
+#define CHANNEL4_DMA_BYTE_COUNT 0x900
+#define CHANNEL5_DMA_BYTE_COUNT 0x904
+#define CHANNEL6_DMA_BYTE_COUNT 0x908
+#define CHANNEL7_DMA_BYTE_COUNT 0x90C
+#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
+#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
+#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
+#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
+#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910
+#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914
+#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918
+#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C
+#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
+#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
+#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
+#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
+#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920
+#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924
+#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928
+#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C
+#define CHANNEL0NEXT_RECORD_POINTER 0x830
+#define CHANNEL1NEXT_RECORD_POINTER 0x834
+#define CHANNEL2NEXT_RECORD_POINTER 0x838
+#define CHANNEL3NEXT_RECORD_POINTER 0x83C
+#define CHANNEL4NEXT_RECORD_POINTER 0x930
+#define CHANNEL5NEXT_RECORD_POINTER 0x934
+#define CHANNEL6NEXT_RECORD_POINTER 0x938
+#define CHANNEL7NEXT_RECORD_POINTER 0x93C
+#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
+#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
+#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
+#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
+#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970
+#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974
+#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978
+#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C
+#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890
+#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894
+#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898
+#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c
+#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990
+#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994
+#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998
+#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c
+#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0
+#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4
+#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8
+#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac
+#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0
+#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4
+#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8
+#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac
+#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0
+#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4
+#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8
+#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc
+#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0
+#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4
+#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8
+#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc
+
+/****************************************/
+/* DMA Channel Control */
+/****************************************/
+
+#define CHANNEL0CONTROL 0x840
+#define CHANNEL0CONTROL_HIGH 0x880
+#define CHANNEL1CONTROL 0x844
+#define CHANNEL1CONTROL_HIGH 0x884
+#define CHANNEL2CONTROL 0x848
+#define CHANNEL2CONTROL_HIGH 0x888
+#define CHANNEL3CONTROL 0x84C
+#define CHANNEL3CONTROL_HIGH 0x88C
+
+#define CHANNEL4CONTROL 0x940
+#define CHANNEL4CONTROL_HIGH 0x980
+#define CHANNEL5CONTROL 0x944
+#define CHANNEL5CONTROL_HIGH 0x984
+#define CHANNEL6CONTROL 0x948
+#define CHANNEL6CONTROL_HIGH 0x988
+#define CHANNEL7CONTROL 0x94C
+#define CHANNEL7CONTROL_HIGH 0x98C
+
+
+/****************************************/
+/* DMA Arbiter */
+/****************************************/
+
+#define ARBITER_CONTROL_0_3 0x860
+#define ARBITER_CONTROL_4_7 0x960
+
+
+/****************************************/
+/* DMA Interrupt */
+/****************************************/
+
+#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
+#define CHANELS0_3_INTERRUPT_MASK 0x8c4
+#define CHANELS0_3_ERROR_ADDRESS 0x8c8
+#define CHANELS0_3_ERROR_SELECT 0x8cc
+#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0
+#define CHANELS4_7_INTERRUPT_MASK 0x9c4
+#define CHANELS4_7_ERROR_ADDRESS 0x9c8
+#define CHANELS4_7_ERROR_SELECT 0x9cc
+
+
+/****************************************/
+/* DMA Debug (for internal use) */
+/****************************************/
+
+#define DMA_X0_ADDRESS 0x8e0
+#define DMA_X0_COMMAND_AND_ID 0x8e4
+#define DMA_X0_WRITE_DATA_LOW 0x8e8
+#define DMA_X0_WRITE_DATA_HIGH 0x8ec
+#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8
+#define DMA_X0_READ_DATA_LOW 0x8f0
+#define DMA_X0_READ_DATA_HIGH 0x8f4
+#define DMA_X0_READ_ID 0x8fc
+#define DMA_X1_ADDRESS 0x9e0
+#define DMA_X1_COMMAND_AND_ID 0x9e4
+#define DMA_X1_WRITE_DATA_LOW 0x9e8
+#define DMA_X1_WRITE_DATA_HIGH 0x9ec
+#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8
+#define DMA_X1_READ_DATA_LOW 0x9f0
+#define DMA_X1_READ_DATA_HIGH 0x9f4
+#define DMA_X1_READ_ID 0x9fc
+
+/****************************************/
+/* Timer_Counter */
+/****************************************/
+
+#define TIMER_COUNTER0 0x850
+#define TIMER_COUNTER1 0x854
+#define TIMER_COUNTER2 0x858
+#define TIMER_COUNTER3 0x85C
+#define TIMER_COUNTER_0_3_CONTROL 0x864
+#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
+#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
+#define TIMER_COUNTER4 0x950
+#define TIMER_COUNTER5 0x954
+#define TIMER_COUNTER6 0x958
+#define TIMER_COUNTER7 0x95C
+#define TIMER_COUNTER_4_7_CONTROL 0x964
+#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968
+#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c
+
+/****************************************/
+/* PCI Slave Address Decoding */
+/****************************************/
+
+#define PCI_0SCS_0_BANK_SIZE 0xc08
+#define PCI_1SCS_0_BANK_SIZE 0xc88
+#define PCI_0SCS_1_BANK_SIZE 0xd08
+#define PCI_1SCS_1_BANK_SIZE 0xd88
+#define PCI_0SCS_2_BANK_SIZE 0xc0c
+#define PCI_1SCS_2_BANK_SIZE 0xc8c
+#define PCI_0SCS_3_BANK_SIZE 0xd0c
+#define PCI_1SCS_3_BANK_SIZE 0xd8c
+#define PCI_0CS_0_BANK_SIZE 0xc10
+#define PCI_1CS_0_BANK_SIZE 0xc90
+#define PCI_0CS_1_BANK_SIZE 0xd10
+#define PCI_1CS_1_BANK_SIZE 0xd90
+#define PCI_0CS_2_BANK_SIZE 0xd18
+#define PCI_1CS_2_BANK_SIZE 0xd98
+#define PCI_0CS_3_BANK_SIZE 0xc14
+#define PCI_1CS_3_BANK_SIZE 0xc94
+#define PCI_0CS_BOOT_BANK_SIZE 0xd14
+#define PCI_1CS_BOOT_BANK_SIZE 0xd94
+#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
+#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
+#define PCI_0P2P_MEM1_BAR_SIZE 0xd20
+#define PCI_1P2P_MEM1_BAR_SIZE 0xda0
+#define PCI_0P2P_I_O_BAR_SIZE 0xd24
+#define PCI_1P2P_I_O_BAR_SIZE 0xda4
+#define PCI_0CPU_BAR_SIZE 0xd28
+#define PCI_1CPU_BAR_SIZE 0xda8
+#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
+#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
+#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
+#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
+#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
+#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
+#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
+#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
+#define PCI_0DAC_CS_0_BANK_SIZE 0xe10
+#define PCI_1DAC_CS_0_BANK_SIZE 0xe90
+#define PCI_0DAC_CS_1_BANK_SIZE 0xe14
+#define PCI_1DAC_CS_1_BANK_SIZE 0xe94
+#define PCI_0DAC_CS_2_BANK_SIZE 0xe18
+#define PCI_1DAC_CS_2_BANK_SIZE 0xe98
+#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
+#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
+#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
+#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
+#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
+#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
+#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
+#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
+#define PCI_0DAC_CPU_BAR_SIZE 0xe2c
+#define PCI_1DAC_CPU_BAR_SIZE 0xeac
+#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
+#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
+#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
+#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
+#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
+#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
+#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
+#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
+#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
+#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
+#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
+#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
+#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
+#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
+#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
+#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
+#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
+#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
+#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
+#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
+#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
+#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
+#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
+#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
+#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
+#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
+#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
+#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
+#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
+#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
+#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
+#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
+#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
+#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
+#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
+#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
+#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
+#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
+#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
+#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
+#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
+#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
+#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
+#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
+#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
+#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
+#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
+#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
+#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
+#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
+
+/****************************************/
+/* PCI Control */
+/****************************************/
+
+#define PCI_0COMMAND 0xc00
+#define PCI_1COMMAND 0xc80
+#define PCI_0MODE 0xd00
+#define PCI_1MODE 0xd80
+#define PCI_0TIMEOUT_RETRY 0xc04
+#define PCI_1TIMEOUT_RETRY 0xc84
+#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
+#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
+#define MSI_0TRIGGER_TIMER 0xc38
+#define MSI_1TRIGGER_TIMER 0xcb8
+#define PCI_0ARBITER_CONTROL 0x1d00
+#define PCI_1ARBITER_CONTROL 0x1d80
/* changing untill here */
-#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
-#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
-#define PCI_0CROSS_BAR_TIMEOUT 0x1d04
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
-#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
-#define PCI_0P2P_CONFIGURATION 0x1d14
-#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
-#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
-#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
-#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10
-#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
-#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
-#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20
-#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
-#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
-#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30
-#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
-#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
-#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40
-#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
-#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
-#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50
-#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
-#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
-#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60
-#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
-#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
-#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70
-#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
-#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
-#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
-#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
-#define PCI_1CROSS_BAR_TIMEOUT 0x1d84
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
-#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
-#define PCI_1P2P_CONFIGURATION 0x1d94
-#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
-#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
-#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
-#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90
-#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
-#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
-#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0
-#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
-#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
-#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0
-#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
-#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
-#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0
-#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
-#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
-#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0
-#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
-#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
-#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0
-#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
-#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
-#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0
-#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
-#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
-
-/****************************************/
-/* PCI Snoop Control */
-/****************************************/
-
-#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
-#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
-#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
-#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
-#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
-#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
-#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
-#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
-#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
-#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
-#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
-#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
-#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
-#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
-#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
-#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
-#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
-#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
-#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
-#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
-#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
-#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
-#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
-#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
-
-/****************************************/
-/* PCI Configuration Address */
-/****************************************/
-
-#define PCI_0CONFIGURATION_ADDRESS 0xcf8
-#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
-#define PCI_1CONFIGURATION_ADDRESS 0xc78
-#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
-#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
-#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
-
-/****************************************/
-/* PCI Error Report */
+#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
+#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
+#define PCI_0CROSS_BAR_TIMEOUT 0x1d04
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
+#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
+#define PCI_0P2P_CONFIGURATION 0x1d14
+#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
+#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
+#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
+#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10
+#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
+#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
+#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20
+#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
+#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
+#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30
+#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
+#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
+#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40
+#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
+#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
+#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50
+#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
+#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
+#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60
+#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
+#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
+#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70
+#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
+#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
+#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
+#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
+#define PCI_1CROSS_BAR_TIMEOUT 0x1d84
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
+#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
+#define PCI_1P2P_CONFIGURATION 0x1d94
+#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
+#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
+#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
+#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90
+#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
+#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
+#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0
+#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
+#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
+#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0
+#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
+#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
+#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0
+#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
+#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
+#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0
+#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
+#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
+#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0
+#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
+#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
+#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0
+#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
+#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
+
+/****************************************/
+/* PCI Snoop Control */
+/****************************************/
+
+#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
+#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
+#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
+#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
+#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
+#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
+#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
+#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
+#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
+#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
+#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
+#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
+#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
+#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
+#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
+#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
+#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
+#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
+#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
+#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
+#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
+#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
+#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
+#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
+
+/****************************************/
+/* PCI Configuration Address */
+/****************************************/
+
+#define PCI_0CONFIGURATION_ADDRESS 0xcf8
+#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
+#define PCI_1CONFIGURATION_ADDRESS 0xc78
+#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
+#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
+#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
+
+/****************************************/
+/* PCI Error Report */
/****************************************/
#define PCI_0SERR_MASK 0xc28
-#define PCI_0ERROR_ADDRESS_LOW 0x1d40
-#define PCI_0ERROR_ADDRESS_HIGH 0x1d44
-#define PCI_0ERROR_DATA_LOW 0x1d48
-#define PCI_0ERROR_DATA_HIGH 0x1d4c
-#define PCI_0ERROR_COMMAND 0x1d50
-#define PCI_0ERROR_CAUSE 0x1d58
-#define PCI_0ERROR_MASK 0x1d5c
+#define PCI_0ERROR_ADDRESS_LOW 0x1d40
+#define PCI_0ERROR_ADDRESS_HIGH 0x1d44
+#define PCI_0ERROR_DATA_LOW 0x1d48
+#define PCI_0ERROR_DATA_HIGH 0x1d4c
+#define PCI_0ERROR_COMMAND 0x1d50
+#define PCI_0ERROR_CAUSE 0x1d58
+#define PCI_0ERROR_MASK 0x1d5c
#define PCI_1SERR_MASK 0xca8
-#define PCI_1ERROR_ADDRESS_LOW 0x1dc0
-#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
-#define PCI_1ERROR_DATA_LOW 0x1dc8
-#define PCI_1ERROR_DATA_HIGH 0x1dcc
-#define PCI_1ERROR_COMMAND 0x1dd0
-#define PCI_1ERROR_CAUSE 0x1dd8
-#define PCI_1ERROR_MASK 0x1ddc
+#define PCI_1ERROR_ADDRESS_LOW 0x1dc0
+#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
+#define PCI_1ERROR_DATA_LOW 0x1dc8
+#define PCI_1ERROR_DATA_HIGH 0x1dcc
+#define PCI_1ERROR_COMMAND 0x1dd0
+#define PCI_1ERROR_CAUSE 0x1dd8
+#define PCI_1ERROR_MASK 0x1ddc
/****************************************/
-/* Lslave Debug (for internal use) */
+/* Lslave Debug (for internal use) */
/****************************************/
-#define L_SLAVE_X0_ADDRESS 0x1d20
-#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
-#define L_SLAVE_X1_ADDRESS 0x1d28
-#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
-#define L_SLAVE_WRITE_DATA_LOW 0x1d30
-#define L_SLAVE_WRITE_DATA_HIGH 0x1d34
-#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
-#define L_SLAVE_READ_DATA_LOW 0x1d38
-#define L_SLAVE_READ_DATA_HIGH 0x1d3c
-#define L_SLAVE_READ_ID 0x1d64
+#define L_SLAVE_X0_ADDRESS 0x1d20
+#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
+#define L_SLAVE_X1_ADDRESS 0x1d28
+#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
+#define L_SLAVE_WRITE_DATA_LOW 0x1d30
+#define L_SLAVE_WRITE_DATA_HIGH 0x1d34
+#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
+#define L_SLAVE_READ_DATA_LOW 0x1d38
+#define L_SLAVE_READ_DATA_HIGH 0x1d3c
+#define L_SLAVE_READ_ID 0x1d64
/****************************************/
-/* PCI Configuration Function 0 */
+/* PCI Configuration Function 0 */
/****************************************/
-#define PCI_DEVICE_AND_VENDOR_ID 0x000
-#define PCI_STATUS_AND_COMMAND 0x004
-#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
-#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
-#define PCI_SCS_0_BASE_ADDRESS 0x010
-#define PCI_SCS_1_BASE_ADDRESS 0x014
-#define PCI_SCS_2_BASE_ADDRESS 0x018
-#define PCI_SCS_3_BASE_ADDRESS 0x01C
-#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
-#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
-#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
-#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
-#define PCI_CAPABILTY_LIST_POINTER 0x034
-#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
-#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
-#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
-#define PCI_VPD_ADDRESS 0x048
-#define PCI_VPD_DATA 0x04c
-#define PCI_MSI_MESSAGE_CONTROL 0x050
-#define PCI_MSI_MESSAGE_ADDRESS 0x054
-#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
-#define PCI_MSI_MESSAGE_DATA 0x05c
-#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
+#define PCI_DEVICE_AND_VENDOR_ID 0x000
+#define PCI_STATUS_AND_COMMAND 0x004
+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
+#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
+#define PCI_SCS_0_BASE_ADDRESS 0x010
+#define PCI_SCS_1_BASE_ADDRESS 0x014
+#define PCI_SCS_2_BASE_ADDRESS 0x018
+#define PCI_SCS_3_BASE_ADDRESS 0x01C
+#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
+#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
+#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
+#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
+#define PCI_CAPABILTY_LIST_POINTER 0x034
+#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
+#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
+#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
+#define PCI_VPD_ADDRESS 0x048
+#define PCI_VPD_DATA 0x04c
+#define PCI_MSI_MESSAGE_CONTROL 0x050
+#define PCI_MSI_MESSAGE_ADDRESS 0x054
+#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
+#define PCI_MSI_MESSAGE_DATA 0x05c
+#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
/****************************************/
-/* PCI Configuration Function 1 */
+/* PCI Configuration Function 1 */
/****************************************/
-#define PCI_CS_0_BASE_ADDRESS 0x110
-#define PCI_CS_1_BASE_ADDRESS 0x114
-#define PCI_CS_2_BASE_ADDRESS 0x118
-#define PCI_CS_3_BASE_ADDRESS 0x11c
-#define PCI_BOOTCS_BASE_ADDRESS 0x120
+#define PCI_CS_0_BASE_ADDRESS 0x110
+#define PCI_CS_1_BASE_ADDRESS 0x114
+#define PCI_CS_2_BASE_ADDRESS 0x118
+#define PCI_CS_3_BASE_ADDRESS 0x11c
+#define PCI_BOOTCS_BASE_ADDRESS 0x120
/****************************************/
-/* PCI Configuration Function 2 */
+/* PCI Configuration Function 2 */
/****************************************/
-#define PCI_P2P_MEM0_BASE_ADDRESS 0x210
-#define PCI_P2P_MEM1_BASE_ADDRESS 0x214
-#define PCI_P2P_I_O_BASE_ADDRESS 0x218
-#define PCI_CPU_BASE_ADDRESS 0x21c
+#define PCI_P2P_MEM0_BASE_ADDRESS 0x210
+#define PCI_P2P_MEM1_BASE_ADDRESS 0x214
+#define PCI_P2P_I_O_BASE_ADDRESS 0x218
+#define PCI_CPU_BASE_ADDRESS 0x21c
/****************************************/
-/* PCI Configuration Function 4 */
+/* PCI Configuration Function 4 */
/****************************************/
-#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
-#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
-#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
-#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
-
-
-/****************************************/
-/* PCI Configuration Function 5 */
-/****************************************/
-
-#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
-#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
-#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
-#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
+#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
+#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
+#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
+#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
+
+
+/****************************************/
+/* PCI Configuration Function 5 */
+/****************************************/
+
+#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
+#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
+#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
+#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
-/****************************************/
-/* PCI Configuration Function 6 */
-/****************************************/
-
-#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
-#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
-#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
-#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
-#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
-#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
-
-/****************************************/
-/* PCI Configuration Function 7 */
-/****************************************/
-
-#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
-#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
-#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
-#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
-
-/****************************************/
-/* Interrupts */
-/****************************************/
-
-#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18
-#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68
-#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c
-#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c
-#define CPU_SELECT_CAUSE_REGISTER 0xc70
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64
-#define PCI_0SELECT_CAUSE 0xc74
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4
-#define PCI_1SELECT_CAUSE 0xcf4
-#define CPU_INT_0_MASK 0xe60
-#define CPU_INT_1_MASK 0xe64
-#define CPU_INT_2_MASK 0xe68
-#define CPU_INT_3_MASK 0xe6c
-
-/****************************************/
-/* I20 Support registers */
-/****************************************/
-
-#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
-#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
-#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
-#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C
-#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
-#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
-#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
-#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
-#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
-#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
-#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C
-
-#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10
-#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14
-#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18
-#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C
-#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24
-#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28
-#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44
-#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50
-#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64
-#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68
-#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C
-
-/****************************************/
-/* Communication Unit Registers */
-/****************************************/
-
-#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200
-#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
-#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
-#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
-#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
-#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
-#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
-#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
-#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
-#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
-#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
-#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
-#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
-#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
-#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
-#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
-#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
-#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
-#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
-#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
-#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
-#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
-#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
-#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
-#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
-#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
-#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
-#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0
-#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4
-#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
-#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
-#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
-#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
-#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320
-#define SERIAL_INIT_LAST_DATA 0xf324
-#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328
-#define COMM_UNIT_ARBITER_CONTROL 0xf300
-#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
-#define COMM_UNIT_INTERRUPT_CAUSE 0xf310
-#define COMM_UNIT_INTERRUPT_MASK 0xf314
-#define COMM_UNIT_ERROR_ADDRESS 0xf314
-
-/****************************************/
-/* Cunit Debug (for internal use) */
-/****************************************/
-
-#define CUNIT_ADDRESS 0xf340
-#define CUNIT_COMMAND_AND_ID 0xf344
-#define CUNIT_WRITE_DATA_LOW 0xf348
-#define CUNIT_WRITE_DATA_HIGH 0xf34c
-#define CUNIT_WRITE_BYTE_ENABLE 0xf358
-#define CUNIT_READ_DATA_LOW 0xf350
-#define CUNIT_READ_DATA_HIGH 0xf354
-#define CUNIT_READ_ID 0xf35c
-
-/****************************************/
-/* Fast Ethernet Unit Registers */
+/****************************************/
+/* PCI Configuration Function 6 */
+/****************************************/
+
+#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
+#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
+#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
+#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
+#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
+#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
+
+/****************************************/
+/* PCI Configuration Function 7 */
+/****************************************/
+
+#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
+#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
+#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
+#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
+
+/****************************************/
+/* Interrupts */
+/****************************************/
+
+#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18
+#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68
+#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c
+#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c
+#define CPU_SELECT_CAUSE_REGISTER 0xc70
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64
+#define PCI_0SELECT_CAUSE 0xc74
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4
+#define PCI_1SELECT_CAUSE 0xcf4
+#define CPU_INT_0_MASK 0xe60
+#define CPU_INT_1_MASK 0xe64
+#define CPU_INT_2_MASK 0xe68
+#define CPU_INT_3_MASK 0xe6c
+
+/****************************************/
+/* I20 Support registers */
+/****************************************/
+
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C
+
+/****************************************/
+/* Communication Unit Registers */
+/****************************************/
+
+#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200
+#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
+#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
+#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
+#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
+#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
+#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
+#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
+#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
+#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
+#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
+#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
+#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
+#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
+#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
+#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
+#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
+#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
+#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
+#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
+#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
+#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
+#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
+#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
+#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
+#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
+#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
+#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0
+#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4
+#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
+#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
+#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
+#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
+#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320
+#define SERIAL_INIT_LAST_DATA 0xf324
+#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328
+#define COMM_UNIT_ARBITER_CONTROL 0xf300
+#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
+#define COMM_UNIT_INTERRUPT_CAUSE 0xf310
+#define COMM_UNIT_INTERRUPT_MASK 0xf314
+#define COMM_UNIT_ERROR_ADDRESS 0xf314
+
+/****************************************/
+/* Cunit Debug (for internal use) */
+/****************************************/
+
+#define CUNIT_ADDRESS 0xf340
+#define CUNIT_COMMAND_AND_ID 0xf344
+#define CUNIT_WRITE_DATA_LOW 0xf348
+#define CUNIT_WRITE_DATA_HIGH 0xf34c
+#define CUNIT_WRITE_BYTE_ENABLE 0xf358
+#define CUNIT_READ_DATA_LOW 0xf350
+#define CUNIT_READ_DATA_HIGH 0xf354
+#define CUNIT_READ_ID 0xf35c
+
+/****************************************/
+/* Fast Ethernet Unit Registers */
/****************************************/
/* Ethernet */
-#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
-#define ETHERNET_SMI_REGISTER 0x2010
+#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
+#define ETHERNET_SMI_REGISTER 0x2010
/* Ethernet 0 */
-#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
-#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
-#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
-#define ETHERNET0_PORT_STATUS_REGISTER 0x2418
-#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
-#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
-#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
-#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
-#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
-#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
-#define ETHERNET0_MIB_COUNTER_BASE 0x2500
+#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
+#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
+#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
+#define ETHERNET0_PORT_STATUS_REGISTER 0x2418
+#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
+#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
+#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
+#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
+#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
+#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
+#define ETHERNET0_MIB_COUNTER_BASE 0x2500
/* Ethernet 1 */
-#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
-#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
-#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
-#define ETHERNET1_PORT_STATUS_REGISTER 0x2818
-#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
-#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
-#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
-#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
-#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
-#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
-#define ETHERNET1_MIB_COUNTER_BASE 0x2900
+#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
+#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
+#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
+#define ETHERNET1_PORT_STATUS_REGISTER 0x2818
+#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
+#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
+#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
+#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
+#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
+#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
+#define ETHERNET1_MIB_COUNTER_BASE 0x2900
/* Ethernet 2 */
-#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
-#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
-#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
-#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
-#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
-#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
-#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
-#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
-#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
-#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
-#define ETHERNET2_MIB_COUNTER_BASE 0x2d00
-
-/****************************************/
-/* SDMA Registers */
-/****************************************/
-
-#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
-#define CHANNEL0_CONFIGURATION_REGISTER 0x4000
-#define CHANNEL0_COMMAND_REGISTER 0x4008
-#define CHANNEL0_RX_CMD_STATUS 0x4800
-#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
-#define CHANNEL0_RX_BUFFER_POINTER 0x4808
-#define CHANNEL0_RX_NEXT_POINTER 0x480c
-#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
-#define CHANNEL0_TX_CMD_STATUS 0x4C00
-#define CHANNEL0_TX_PACKET_SIZE 0x4C04
-#define CHANNEL0_TX_BUFFER_POINTER 0x4C08
-#define CHANNEL0_TX_NEXT_POINTER 0x4C0c
-#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
-#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
-#define CHANNEL1_CONFIGURATION_REGISTER 0x5000
-#define CHANNEL1_COMMAND_REGISTER 0x5008
-#define CHANNEL1_RX_CMD_STATUS 0x5800
-#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804
-#define CHANNEL1_RX_BUFFER_POINTER 0x5808
-#define CHANNEL1_RX_NEXT_POINTER 0x580c
-#define CHANNEL1_TX_CMD_STATUS 0x5C00
-#define CHANNEL1_TX_PACKET_SIZE 0x5C04
-#define CHANNEL1_TX_BUFFER_POINTER 0x5C08
-#define CHANNEL1_TX_NEXT_POINTER 0x5C0c
-#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810
-#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10
-#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14
-#define CHANNEL2_CONFIGURATION_REGISTER 0x6000
-#define CHANNEL2_COMMAND_REGISTER 0x6008
-#define CHANNEL2_RX_CMD_STATUS 0x6800
-#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804
-#define CHANNEL2_RX_BUFFER_POINTER 0x6808
-#define CHANNEL2_RX_NEXT_POINTER 0x680c
-#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
-#define CHANNEL2_TX_CMD_STATUS 0x6C00
-#define CHANNEL2_TX_PACKET_SIZE 0x6C04
-#define CHANNEL2_TX_BUFFER_POINTER 0x6C08
-#define CHANNEL2_TX_NEXT_POINTER 0x6C0c
-#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
-#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
-#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
+#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
+#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
+#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
+#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
+#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
+#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
+#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
+#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
+#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
+#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
+#define ETHERNET2_MIB_COUNTER_BASE 0x2d00
+
+/****************************************/
+/* SDMA Registers */
+/****************************************/
+
+#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
+#define CHANNEL0_CONFIGURATION_REGISTER 0x4000
+#define CHANNEL0_COMMAND_REGISTER 0x4008
+#define CHANNEL0_RX_CMD_STATUS 0x4800
+#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
+#define CHANNEL0_RX_BUFFER_POINTER 0x4808
+#define CHANNEL0_RX_NEXT_POINTER 0x480c
+#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
+#define CHANNEL0_TX_CMD_STATUS 0x4C00
+#define CHANNEL0_TX_PACKET_SIZE 0x4C04
+#define CHANNEL0_TX_BUFFER_POINTER 0x4C08
+#define CHANNEL0_TX_NEXT_POINTER 0x4C0c
+#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
+#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
+#define CHANNEL1_CONFIGURATION_REGISTER 0x5000
+#define CHANNEL1_COMMAND_REGISTER 0x5008
+#define CHANNEL1_RX_CMD_STATUS 0x5800
+#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804
+#define CHANNEL1_RX_BUFFER_POINTER 0x5808
+#define CHANNEL1_RX_NEXT_POINTER 0x580c
+#define CHANNEL1_TX_CMD_STATUS 0x5C00
+#define CHANNEL1_TX_PACKET_SIZE 0x5C04
+#define CHANNEL1_TX_BUFFER_POINTER 0x5C08
+#define CHANNEL1_TX_NEXT_POINTER 0x5C0c
+#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810
+#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10
+#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14
+#define CHANNEL2_CONFIGURATION_REGISTER 0x6000
+#define CHANNEL2_COMMAND_REGISTER 0x6008
+#define CHANNEL2_RX_CMD_STATUS 0x6800
+#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804
+#define CHANNEL2_RX_BUFFER_POINTER 0x6808
+#define CHANNEL2_RX_NEXT_POINTER 0x680c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
+#define CHANNEL2_TX_CMD_STATUS 0x6C00
+#define CHANNEL2_TX_PACKET_SIZE 0x6C04
+#define CHANNEL2_TX_BUFFER_POINTER 0x6C08
+#define CHANNEL2_TX_NEXT_POINTER 0x6C0c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
+#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
+#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
/* SDMA Interrupt */
-#define SDMA_CAUSE 0xb820
-#define SDMA_MASK 0xb8a0
+#define SDMA_CAUSE 0xb820
+#define SDMA_MASK 0xb8a0
/****************************************/
-/* Baude Rate Generators Registers */
+/* Baude Rate Generators Registers */
/****************************************/
/* BRG 0 */
-#define BRG0_CONFIGURATION_REGISTER 0xb200
-#define BRG0_BAUDE_TUNING_REGISTER 0xb204
+#define BRG0_CONFIGURATION_REGISTER 0xb200
+#define BRG0_BAUDE_TUNING_REGISTER 0xb204
/* BRG 1 */
-#define BRG1_CONFIGURATION_REGISTER 0xb208
-#define BRG1_BAUDE_TUNING_REGISTER 0xb20c
+#define BRG1_CONFIGURATION_REGISTER 0xb208
+#define BRG1_BAUDE_TUNING_REGISTER 0xb20c
/* BRG 2 */
-#define BRG2_CONFIGURATION_REGISTER 0xb210
-#define BRG2_BAUDE_TUNING_REGISTER 0xb214
+#define BRG2_CONFIGURATION_REGISTER 0xb210
+#define BRG2_BAUDE_TUNING_REGISTER 0xb214
/* BRG Interrupts */
-#define BRG_CAUSE_REGISTER 0xb834
-#define BRG_MASK_REGISTER 0xb8b4
+#define BRG_CAUSE_REGISTER 0xb834
+#define BRG_MASK_REGISTER 0xb8b4
/* MISC */
-#define MAIN_ROUTING_REGISTER 0xb400
-#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
-#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
-#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
-#define WATCHDOG_CONFIGURATION_REGISTER 0xb410
-#define WATCHDOG_VALUE_REGISTER 0xb414
+#define MAIN_ROUTING_REGISTER 0xb400
+#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
+#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
+#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
+#define WATCHDOG_CONFIGURATION_REGISTER 0xb410
+#define WATCHDOG_VALUE_REGISTER 0xb414
/****************************************/
-/* Flex TDM Registers */
+/* Flex TDM Registers */
/****************************************/
/* FTDM Port */
-#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
-#define FLEXTDM_RECEIVE_READ_POINTER 0xa804
-#define FLEXTDM_CONFIGURATION_REGISTER 0xa808
-#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
-#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
-#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
-#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
+#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
+#define FLEXTDM_RECEIVE_READ_POINTER 0xa804
+#define FLEXTDM_CONFIGURATION_REGISTER 0xa808
+#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
+#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
+#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
+#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
/* FTDM Interrupts */
-#define FTDM_CAUSE_REGISTER 0xb830
-#define FTDM_MASK_REGISTER 0xb8b0
+#define FTDM_CAUSE_REGISTER 0xb830
+#define FTDM_MASK_REGISTER 0xb8b0
/****************************************/
-/* GPP Interface Registers */
+/* GPP Interface Registers */
/****************************************/
-#define GPP_IO_CONTROL 0xf100
-#define GPP_LEVEL_CONTROL 0xf110
-#define GPP_VALUE 0xf104
-#define GPP_INTERRUPT_CAUSE 0xf108
-#define GPP_INTERRUPT_MASK 0xf10c
+#define GPP_IO_CONTROL 0xf100
+#define GPP_LEVEL_CONTROL 0xf110
+#define GPP_VALUE 0xf104
+#define GPP_INTERRUPT_CAUSE 0xf108
+#define GPP_INTERRUPT_MASK 0xf10c
-#define MPP_CONTROL0 0xf000
-#define MPP_CONTROL1 0xf004
-#define MPP_CONTROL2 0xf008
-#define MPP_CONTROL3 0xf00c
-#define DEBUG_PORT_MULTIPLEX 0xf014
-#define SERIAL_PORT_MULTIPLEX 0xf010
+#define MPP_CONTROL0 0xf000
+#define MPP_CONTROL1 0xf004
+#define MPP_CONTROL2 0xf008
+#define MPP_CONTROL3 0xf00c
+#define DEBUG_PORT_MULTIPLEX 0xf014
+#define SERIAL_PORT_MULTIPLEX 0xf010
/****************************************/
-/* I2C Registers */
+/* I2C Registers */
/****************************************/
-#define I2C_SLAVE_ADDRESS 0xc000
-#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
-#define I2C_DATA 0xc004
-#define I2C_CONTROL 0xc008
-#define I2C_STATUS_BAUDE_RATE 0xc00C
-#define I2C_SOFT_RESET 0xc01c
+#define I2C_SLAVE_ADDRESS 0xc000
+#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
+#define I2C_DATA 0xc004
+#define I2C_CONTROL 0xc008
+#define I2C_STATUS_BAUDE_RATE 0xc00C
+#define I2C_SOFT_RESET 0xc01c
/****************************************/
-/* MPSC Registers */
+/* MPSC Registers */
/****************************************/
/* MPSC0 */
-#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
-#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
-#define MPSC0_PROTOCOL_CONFIGURATION 0x8008
-#define CHANNEL0_REGISTER1 0x800c
-#define CHANNEL0_REGISTER2 0x8010
-#define CHANNEL0_REGISTER3 0x8014
-#define CHANNEL0_REGISTER4 0x8018
-#define CHANNEL0_REGISTER5 0x801c
-#define CHANNEL0_REGISTER6 0x8020
-#define CHANNEL0_REGISTER7 0x8024
-#define CHANNEL0_REGISTER8 0x8028
-#define CHANNEL0_REGISTER9 0x802c
-#define CHANNEL0_REGISTER10 0x8030
-#define CHANNEL0_REGISTER11 0x8034
+#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
+#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
+#define MPSC0_PROTOCOL_CONFIGURATION 0x8008
+#define CHANNEL0_REGISTER1 0x800c
+#define CHANNEL0_REGISTER2 0x8010
+#define CHANNEL0_REGISTER3 0x8014
+#define CHANNEL0_REGISTER4 0x8018
+#define CHANNEL0_REGISTER5 0x801c
+#define CHANNEL0_REGISTER6 0x8020
+#define CHANNEL0_REGISTER7 0x8024
+#define CHANNEL0_REGISTER8 0x8028
+#define CHANNEL0_REGISTER9 0x802c
+#define CHANNEL0_REGISTER10 0x8030
+#define CHANNEL0_REGISTER11 0x8034
/* MPSC1 */
-#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840
-#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844
-#define MPSC1_PROTOCOL_CONFIGURATION 0x8848
-#define CHANNEL1_REGISTER1 0x884c
-#define CHANNEL1_REGISTER2 0x8850
-#define CHANNEL1_REGISTER3 0x8854
-#define CHANNEL1_REGISTER4 0x8858
-#define CHANNEL1_REGISTER5 0x885c
-#define CHANNEL1_REGISTER6 0x8860
-#define CHANNEL1_REGISTER7 0x8864
-#define CHANNEL1_REGISTER8 0x8868
-#define CHANNEL1_REGISTER9 0x886c
-#define CHANNEL1_REGISTER10 0x8870
-#define CHANNEL1_REGISTER11 0x8874
+#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840
+#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844
+#define MPSC1_PROTOCOL_CONFIGURATION 0x8848
+#define CHANNEL1_REGISTER1 0x884c
+#define CHANNEL1_REGISTER2 0x8850
+#define CHANNEL1_REGISTER3 0x8854
+#define CHANNEL1_REGISTER4 0x8858
+#define CHANNEL1_REGISTER5 0x885c
+#define CHANNEL1_REGISTER6 0x8860
+#define CHANNEL1_REGISTER7 0x8864
+#define CHANNEL1_REGISTER8 0x8868
+#define CHANNEL1_REGISTER9 0x886c
+#define CHANNEL1_REGISTER10 0x8870
+#define CHANNEL1_REGISTER11 0x8874
/* MPSC2 */
-#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040
-#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044
-#define MPSC2_PROTOCOL_CONFIGURATION 0x9048
-#define CHANNEL2_REGISTER1 0x904c
-#define CHANNEL2_REGISTER2 0x9050
-#define CHANNEL2_REGISTER3 0x9054
-#define CHANNEL2_REGISTER4 0x9058
-#define CHANNEL2_REGISTER5 0x905c
-#define CHANNEL2_REGISTER6 0x9060
-#define CHANNEL2_REGISTER7 0x9064
-#define CHANNEL2_REGISTER8 0x9068
-#define CHANNEL2_REGISTER9 0x906c
-#define CHANNEL2_REGISTER10 0x9070
-#define CHANNEL2_REGISTER11 0x9074
+#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040
+#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044
+#define MPSC2_PROTOCOL_CONFIGURATION 0x9048
+#define CHANNEL2_REGISTER1 0x904c
+#define CHANNEL2_REGISTER2 0x9050
+#define CHANNEL2_REGISTER3 0x9054
+#define CHANNEL2_REGISTER4 0x9058
+#define CHANNEL2_REGISTER5 0x905c
+#define CHANNEL2_REGISTER6 0x9060
+#define CHANNEL2_REGISTER7 0x9064
+#define CHANNEL2_REGISTER8 0x9068
+#define CHANNEL2_REGISTER9 0x906c
+#define CHANNEL2_REGISTER10 0x9070
+#define CHANNEL2_REGISTER11 0x9074
/* MPSCs Interupts */
-#define MPSC0_CAUSE 0xb824
-#define MPSC0_MASK 0xb8a4
-#define MPSC1_CAUSE 0xb828
-#define MPSC1_MASK 0xb8a8
-#define MPSC2_CAUSE 0xb82c
-#define MPSC2_MASK 0xb8ac
+#define MPSC0_CAUSE 0xb824
+#define MPSC0_MASK 0xb8a4
+#define MPSC1_CAUSE 0xb828
+#define MPSC1_MASK 0xb8a8
+#define MPSC2_CAUSE 0xb82c
+#define MPSC2_MASK 0xb8ac
#endif /* __INCgt64260rh */
diff --git a/include/i2c.h b/include/i2c.h
index 6e6c845..a51c164 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -113,9 +113,9 @@ void i2c_reg_write(uchar chip, uchar reg, uchar val);
* Change the active I2C bus. Subsequent read/write calls will
* go to this one.
*
- * bus - bus index, zero based
+ * bus - bus index, zero based
*
- * Returns: 0 on success, not 0 on failure
+ * Returns: 0 on success, not 0 on failure
*
*/
int i2c_set_bus_num(unsigned int bus);
@@ -133,9 +133,9 @@ unsigned int i2c_get_bus_num(void);
*
* Change the speed of the active I2C bus
*
- * speed - bus speed in Hz
+ * speed - bus speed in Hz
*
- * Returns: 0 on success, not 0 on failure
+ * Returns: 0 on success, not 0 on failure
*
*/
int i2c_set_bus_speed(unsigned int);
diff --git a/include/lcd.h b/include/lcd.h
index 8a4273c..44ac8ef 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -155,7 +155,35 @@ typedef struct vidinfo {
u_char vl_bpix; /* Bits per pixel, 0 = 1 */
} vidinfo_t;
-#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 */
+
+#elif defined(CONFIG_ATMEL_LCD)
+
+typedef struct vidinfo {
+ u_long vl_col; /* Number of columns (i.e. 640) */
+ u_long vl_row; /* Number of rows (i.e. 480) */
+ u_long vl_clk; /* pixel clock in ps */
+
+ /* LCD configuration register */
+ u_long vl_sync; /* Horizontal / vertical sync */
+ u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
+ u_long vl_tft; /* 0 = passive, 1 = TFT */
+
+ /* Horizontal control register. */
+ u_long vl_hsync_len; /* Length of horizontal sync */
+ u_long vl_left_margin; /* Time from sync to picture */
+ u_long vl_right_margin; /* Time from picture to sync */
+
+ /* Vertical control register. */
+ u_long vl_vsync_len; /* Length of vertical sync */
+ u_long vl_upper_margin; /* Time from sync to picture */
+ u_long vl_lower_margin; /* Time from picture to sync */
+
+ u_long mmio; /* Memory mapped registers */
+} vidinfo_t;
+
+extern vidinfo_t panel_info;
+
+#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */
/* Video functions */
diff --git a/include/libfdt.h b/include/libfdt.h
index beeacb2..2a2b23d 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -142,15 +142,15 @@ int fdt_next_node(const void *fdt, int offset, int *depth);
#define fdt_get_header(fdt, field) \
(fdt32_to_cpu(((const struct fdt_header *)(fdt))->field))
-#define fdt_magic(fdt) (fdt_get_header(fdt, magic))
+#define fdt_magic(fdt) (fdt_get_header(fdt, magic))
#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize))
#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct))
#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings))
#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap))
#define fdt_version(fdt) (fdt_get_header(fdt, version))
-#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version))
-#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys))
-#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings))
+#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version))
+#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys))
+#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings))
#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct))
#define __fdt_set_hdr(name) \
@@ -445,7 +445,7 @@ uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
* 0, on success
* buf contains the absolute path of the node at
* nodeoffset, as a NUL-terminated string.
- * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1)
* characters and will not fit in the given buffer.
* -FDT_ERR_BADMAGIC,
@@ -478,7 +478,7 @@ int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen);
* structure block offset of the node at node offset's ancestor
* of depth supernodedepth (>=0), on success
- * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
@@ -501,7 +501,7 @@ int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
*
* returns:
* depth of the node at nodeoffset (>=0), on success
- * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
@@ -524,7 +524,7 @@ int fdt_node_depth(const void *fdt, int nodeoffset);
* returns:
* stucture block offset of the parent of the node at nodeoffset
* (>=0), on success
- * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
@@ -564,7 +564,7 @@ int fdt_parent_offset(const void *fdt, int nodeoffset);
* on success
* -FDT_ERR_NOTFOUND, no node matching the criterion exists in the
* tree after startoffset
- * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
@@ -611,7 +611,7 @@ int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);
* 1, if the node has a 'compatible' property, but it does not list
* the given string
* -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property
- * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
+ * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
@@ -648,7 +648,7 @@ int fdt_node_check_compatible(const void *fdt, int nodeoffset,
* on success
* -FDT_ERR_NOTFOUND, no node matching the criterion exists in the
* tree after startoffset
- * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
index f194cf1..bffb25b 100644
--- a/include/linux/mtd/bbm.h
+++ b/include/linux/mtd/bbm.h
@@ -26,8 +26,8 @@
* struct nand_bbt_descr - bad block table descriptor
* @param options options for this descriptor
* @param pages the page(s) where we find the bbt, used with
- * option BBT_ABSPAGE when bbt is searched,
- * then we store the found bbts pages here.
+ * option BBT_ABSPAGE when bbt is searched,
+ * then we store the found bbts pages here.
* Its an array and supports up to 8 chips now
* @param offs offset of the pattern in the oob area of the page
* @param veroffs offset of the bbt version counter in the oob are of the page
diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
index eeb1d7e..29f6767 100644
--- a/include/linux/mtd/doc2000.h
+++ b/include/linux/mtd/doc2000.h
@@ -19,8 +19,8 @@ struct DiskOnChip;
#define DoC_DOCControl 0x1002
#define DoC_FloorSelect 0x1003
#define DoC_CDSNControl 0x1004
-#define DoC_CDSNDeviceSelect 0x1005
-#define DoC_ECCConf 0x1006
+#define DoC_CDSNDeviceSelect 0x1005
+#define DoC_ECCConf 0x1006
#define DoC_2k_ECCStatus 0x1007
#define DoC_CDSNSlowIO 0x100d
@@ -30,15 +30,15 @@ struct DiskOnChip;
#define DoC_ECCSyndrome3 0x1013
#define DoC_ECCSyndrome4 0x1014
#define DoC_ECCSyndrome5 0x1015
-#define DoC_AliasResolution 0x101b
+#define DoC_AliasResolution 0x101b
#define DoC_ConfigInput 0x101c
-#define DoC_ReadPipeInit 0x101d
-#define DoC_WritePipeTerm 0x101e
-#define DoC_LastDataRead 0x101f
-#define DoC_NOP 0x1020
+#define DoC_ReadPipeInit 0x101d
+#define DoC_WritePipeTerm 0x101e
+#define DoC_LastDataRead 0x101f
+#define DoC_NOP 0x1020
-#define DoC_Mil_CDSN_IO 0x0800
-#define DoC_2k_CDSN_IO 0x1800
+#define DoC_Mil_CDSN_IO 0x0800
+#define DoC_2k_CDSN_IO 0x1800
#define ReadDOC_(adr, reg) ((volatile unsigned char)(*(volatile __u8 *)(((unsigned long)adr)+((reg)))))
#define WriteDOC_(d, adr, reg) do{ *(volatile __u8 *)(((unsigned long)adr)+((reg))) = (__u8)d; eieio();} while(0)
@@ -49,32 +49,32 @@ struct DiskOnChip;
#define ReadDOC(adr, reg) ReadDOC_(adr,DoC_##reg)
#define WriteDOC(d, adr, reg) WriteDOC_(d,adr,DoC_##reg)
-#define DOC_MODE_RESET 0
-#define DOC_MODE_NORMAL 1
-#define DOC_MODE_RESERVED1 2
-#define DOC_MODE_RESERVED2 3
-
-#define DOC_MODE_MDWREN 4
-#define DOC_MODE_CLR_ERR 0x80
-
-#define DOC_ChipID_UNKNOWN 0x00
-#define DOC_ChipID_Doc2k 0x20
-#define DOC_ChipID_DocMil 0x30
-
-#define CDSN_CTRL_FR_B 0x80
-#define CDSN_CTRL_ECC_IO 0x20
-#define CDSN_CTRL_FLASH_IO 0x10
-#define CDSN_CTRL_WP 0x08
-#define CDSN_CTRL_ALE 0x04
-#define CDSN_CTRL_CLE 0x02
-#define CDSN_CTRL_CE 0x01
-
-#define DOC_ECC_RESET 0
-#define DOC_ECC_ERROR 0x80
-#define DOC_ECC_RW 0x20
-#define DOC_ECC__EN 0x08
-#define DOC_TOGGLE_BIT 0x04
-#define DOC_ECC_RESV 0x02
+#define DOC_MODE_RESET 0
+#define DOC_MODE_NORMAL 1
+#define DOC_MODE_RESERVED1 2
+#define DOC_MODE_RESERVED2 3
+
+#define DOC_MODE_MDWREN 4
+#define DOC_MODE_CLR_ERR 0x80
+
+#define DOC_ChipID_UNKNOWN 0x00
+#define DOC_ChipID_Doc2k 0x20
+#define DOC_ChipID_DocMil 0x30
+
+#define CDSN_CTRL_FR_B 0x80
+#define CDSN_CTRL_ECC_IO 0x20
+#define CDSN_CTRL_FLASH_IO 0x10
+#define CDSN_CTRL_WP 0x08
+#define CDSN_CTRL_ALE 0x04
+#define CDSN_CTRL_CLE 0x02
+#define CDSN_CTRL_CE 0x01
+
+#define DOC_ECC_RESET 0
+#define DOC_ECC_ERROR 0x80
+#define DOC_ECC_RW 0x20
+#define DOC_ECC__EN 0x08
+#define DOC_TOGGLE_BIT 0x04
+#define DOC_ECC_RESV 0x02
#define DOC_ECC_IGNORE 0x01
/* We have to also set the reserved bit 1 for enable */
diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
index 3d1d416..72d7341 100644
--- a/include/linux/mtd/mtd-abi.h
+++ b/include/linux/mtd/mtd-abi.h
@@ -46,7 +46,7 @@ struct mtd_oob_buf {
/* Types of automatic ECC/Checksum available */
-#define MTD_ECC_NONE 0 /* No automatic ECC available */
+#define MTD_ECC_NONE 0 /* No automatic ECC available */
#define MTD_ECC_RS_DiskOnChip 1 /* Automatic ECC on DiskOnChip */
#define MTD_ECC_SW 2 /* SW ECC for Toshiba & Samsung devices */
@@ -55,7 +55,7 @@ struct mtd_oob_buf {
#define MTD_NANDECC_PLACE 1 /* Use the given placement in the structure (YAFFS1 legacy mode) */
#define MTD_NANDECC_AUTOPLACE 2 /* Use the default placement scheme */
#define MTD_NANDECC_PLACEONLY 3 /* Use the given placement in the structure (Do not store ecc result on read) */
-#define MTD_NANDECC_AUTOPL_USR 4 /* Use the given autoplacement scheme rather than using the default */
+#define MTD_NANDECC_AUTOPL_USR 4 /* Use the given autoplacement scheme rather than using the default */
struct mtd_info_user {
uint8_t type;
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 13e9080..71cb2d5 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -13,7 +13,7 @@
#define MAX_MTD_DEVICES 16
-#define MTD_ERASE_PENDING 0x01
+#define MTD_ERASE_PENDING 0x01
#define MTD_ERASING 0x02
#define MTD_ERASE_SUSPEND 0x04
#define MTD_ERASE_DONE 0x08
@@ -202,7 +202,7 @@ static inline void mtd_erase_callback(struct erase_info *instr)
#ifdef CONFIG_MTD_DEBUG
#define DEBUG(n, args...) \
- do { \
+ do { \
if (n <= CONFIG_MTD_DEBUG_VERBOSE) \
printk(KERN_INFO args); \
} while(0)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 4cc4a7d..e2a25a6 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -385,6 +385,10 @@ struct nand_manufacturers {
extern struct nand_flash_dev nand_flash_ids[];
extern struct nand_manufacturers nand_manuf_ids[];
+#ifndef NAND_MAX_CHIPS
+#define NAND_MAX_CHIPS 8
+#endif
+
/**
* struct nand_bbt_descr - bad block table descriptor
* @options: options for this descriptor
diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h
index a8769e7..b05e726 100644
--- a/include/linux/mtd/nand_legacy.h
+++ b/include/linux/mtd/nand_legacy.h
@@ -104,12 +104,12 @@ struct Nand {
};
struct nand_chip {
- int page_shift;
- u_char *data_buf;
- u_char *data_cache;
+ int page_shift;
+ u_char *data_buf;
+ u_char *data_cache;
int cache_page;
- u_char ecc_code_buf[6];
- u_char reserved[2];
+ u_char ecc_code_buf[6];
+ u_char reserved[2];
char ChipID; /* Type of DiskOnChip */
struct Nand *chips;
int chipshift;
diff --git a/include/linux/mtd/nftl.h b/include/linux/mtd/nftl.h
index 4381306..b0337c3 100644
--- a/include/linux/mtd/nftl.h
+++ b/include/linux/mtd/nftl.h
@@ -89,11 +89,11 @@ struct NFTLrecord {
__u16 numvunits;
__u16 lastEUN; /* should be suppressed */
__u16 numfreeEUNs;
- __u16 LastFreeEUN; /* To speed up finding a free EUN */
+ __u16 LastFreeEUN; /* To speed up finding a free EUN */
__u32 nr_sects;
int head,sect,cyl;
- __u16 *EUNtable; /* [numvunits]: First EUN for each virtual unit */
- __u16 *ReplUnitTable; /* [numEUNs]: ReplUnitNumber for each */
+ __u16 *EUNtable; /* [numvunits]: First EUN for each virtual unit */
+ __u16 *ReplUnitTable; /* [numEUNs]: ReplUnitNumber for each */
unsigned int nb_blocks; /* number of physical blocks */
unsigned int nb_boot_blocks; /* number of blocks used by the bios */
};
diff --git a/include/lists.h b/include/lists.h
index 804b5cd..10a2a19 100644
--- a/include/lists.h
+++ b/include/lists.h
@@ -1,8 +1,8 @@
#ifndef _LISTS_H_
#define _LISTS_H_
-#define LIST_START -1 /* Handy Constants that substitute for item positions */
-#define LIST_END 0 /* END_OF_LIST means one past current length of list when */
+#define LIST_START -1 /* Handy Constants that substitute for item positions */
+#define LIST_END 0 /* END_OF_LIST means one past current length of list when */
/* inserting. Otherwise it refers the last item in the list. */
typedef struct
diff --git a/include/logbuff.h b/include/logbuff.h
index d415729..ae7908c 100644
--- a/include/logbuff.h
+++ b/include/logbuff.h
@@ -31,8 +31,6 @@
#define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */
#define LOGBUFF_RESERVE (LOGBUFF_LEN+LOGBUFF_OVERHEAD)
-#define LOGBUFF_INITIALIZED (1<<31)
-
/* The mapping used here has to be the same as in setup_ext_logbuff ()
in linux/kernel/printk */
@@ -60,6 +58,7 @@ int drv_logbuff_init (void);
void logbuff_init_ptrs (void);
void logbuff_log(char *msg);
void logbuff_reset (void);
+unsigned long logbuffer_base (void);
#endif /* CONFIG_LOGBUFFER */
diff --git a/include/lxt971a.h b/include/lxt971a.h
index 2b5b6d4..f76c336 100644
--- a/include/lxt971a.h
+++ b/include/lxt971a.h
@@ -30,75 +30,75 @@
#define __LXT971A_H__
/* PHY definitions (LXT971A) [2] */
-#define PHY_COMMON_CTRL (0x00)
-#define PHY_COMMON_STAT (0x01)
-#define PHY_COMMON_ID1 (0x02)
-#define PHY_COMMON_ID2 (0x03)
-#define PHY_COMMON_AUTO_ADV (0x04)
-#define PHY_COMMON_AUTO_LNKB (0x05)
-#define PHY_COMMON_AUTO_EXP (0x06)
-#define PHY_COMMON_AUTO_NEXT (0x07)
-#define PHY_COMMON_AUTO_LNKN (0x08)
-#define PHY_LXT971_PORT_CFG (0x10)
-#define PHY_LXT971_STAT2 (0x11)
-#define PHY_LXT971_INT_ENABLE (0x12)
-#define PHY_LXT971_INT_STATUS (0x13)
-#define PHY_LXT971_LED_CFG (0x14)
-#define PHY_LXT971_DIG_CFG (0x1A)
-#define PHY_LXT971_TX_CTRL (0x1E)
+#define PHY_COMMON_CTRL (0x00)
+#define PHY_COMMON_STAT (0x01)
+#define PHY_COMMON_ID1 (0x02)
+#define PHY_COMMON_ID2 (0x03)
+#define PHY_COMMON_AUTO_ADV (0x04)
+#define PHY_COMMON_AUTO_LNKB (0x05)
+#define PHY_COMMON_AUTO_EXP (0x06)
+#define PHY_COMMON_AUTO_NEXT (0x07)
+#define PHY_COMMON_AUTO_LNKN (0x08)
+#define PHY_LXT971_PORT_CFG (0x10)
+#define PHY_LXT971_STAT2 (0x11)
+#define PHY_LXT971_INT_ENABLE (0x12)
+#define PHY_LXT971_INT_STATUS (0x13)
+#define PHY_LXT971_LED_CFG (0x14)
+#define PHY_LXT971_DIG_CFG (0x1A)
+#define PHY_LXT971_TX_CTRL (0x1E)
/* CTRL PHY Control Register Bit Fields */
-#define PHY_COMMON_CTRL_RESET (0x8000)
-#define PHY_COMMON_CTRL_LOOPBACK (0x4000)
-#define PHY_COMMON_CTRL_SPD_MA (0x2040)
-#define PHY_COMMON_CTRL_SPD_10 (0x0000)
-#define PHY_COMMON_CTRL_SPD_100 (0x2000)
-#define PHY_COMMON_CTRL_SPD_1000 (0x0040)
-#define PHY_COMMON_CTRL_SPD_RES (0x2040)
-#define PHY_COMMON_CTRL_AUTO_NEG (0x1000)
-#define PHY_COMMON_CTRL_POWER_DN (0x0800)
-#define PHY_COMMON_CTRL_ISOLATE (0x0400)
-#define PHY_COMMON_CTRL_RES_AUTO (0x0200)
-#define PHY_COMMON_CTRL_DUPLEX (0x0100)
-#define PHY_COMMON_CTRL_COL_TEST (0x0080)
-#define PHY_COMMON_CTRL_RES1 (0x003F)
+#define PHY_COMMON_CTRL_RESET (0x8000)
+#define PHY_COMMON_CTRL_LOOPBACK (0x4000)
+#define PHY_COMMON_CTRL_SPD_MA (0x2040)
+#define PHY_COMMON_CTRL_SPD_10 (0x0000)
+#define PHY_COMMON_CTRL_SPD_100 (0x2000)
+#define PHY_COMMON_CTRL_SPD_1000 (0x0040)
+#define PHY_COMMON_CTRL_SPD_RES (0x2040)
+#define PHY_COMMON_CTRL_AUTO_NEG (0x1000)
+#define PHY_COMMON_CTRL_POWER_DN (0x0800)
+#define PHY_COMMON_CTRL_ISOLATE (0x0400)
+#define PHY_COMMON_CTRL_RES_AUTO (0x0200)
+#define PHY_COMMON_CTRL_DUPLEX (0x0100)
+#define PHY_COMMON_CTRL_COL_TEST (0x0080)
+#define PHY_COMMON_CTRL_RES1 (0x003F)
/* STAT Status Register Bit Fields */
-#define PHY_COMMON_STAT_100BT4 (0x8000)
-#define PHY_COMMON_STAT_100BXFD (0x4000)
-#define PHY_COMMON_STAT_100BXHD (0x2000)
-#define PHY_COMMON_STAT_10BTFD (0x1000)
-#define PHY_COMMON_STAT_10BTHD (0x0800)
-#define PHY_COMMON_STAT_100BT2FD (0x0400)
-#define PHY_COMMON_STAT_100BT2HD (0x0200)
-#define PHY_COMMON_STAT_EXT_STAT (0x0100)
-#define PHY_COMMON_STAT_RES1 (0x0080)
-#define PHY_COMMON_STAT_MF_PSUP (0x0040)
-#define PHY_COMMON_STAT_AN_COMP (0x0020)
-#define PHY_COMMON_STAT_RMT_FLT (0x0010)
-#define PHY_COMMON_STAT_AN_CAP (0x0008)
-#define PHY_COMMON_STAT_LNK_STAT (0x0004)
-#define PHY_COMMON_STAT_JAB_DTCT (0x0002)
-#define PHY_COMMON_STAT_EXT_CAP (0x0001)
+#define PHY_COMMON_STAT_100BT4 (0x8000)
+#define PHY_COMMON_STAT_100BXFD (0x4000)
+#define PHY_COMMON_STAT_100BXHD (0x2000)
+#define PHY_COMMON_STAT_10BTFD (0x1000)
+#define PHY_COMMON_STAT_10BTHD (0x0800)
+#define PHY_COMMON_STAT_100BT2FD (0x0400)
+#define PHY_COMMON_STAT_100BT2HD (0x0200)
+#define PHY_COMMON_STAT_EXT_STAT (0x0100)
+#define PHY_COMMON_STAT_RES1 (0x0080)
+#define PHY_COMMON_STAT_MF_PSUP (0x0040)
+#define PHY_COMMON_STAT_AN_COMP (0x0020)
+#define PHY_COMMON_STAT_RMT_FLT (0x0010)
+#define PHY_COMMON_STAT_AN_CAP (0x0008)
+#define PHY_COMMON_STAT_LNK_STAT (0x0004)
+#define PHY_COMMON_STAT_JAB_DTCT (0x0002)
+#define PHY_COMMON_STAT_EXT_CAP (0x0001)
/* AUTO_ADV Auto-neg Advert Register Bit Fields */
-#define PHY_COMMON_AUTO_ADV_NP (0x8000)
+#define PHY_COMMON_AUTO_ADV_NP (0x8000)
#define PHY_COMMON_AUTO_ADV_RES1 (0x4000)
#define PHY_COMMON_AUTO_ADV_RMT_FLT (0x2000)
#define PHY_COMMON_AUTO_ADV_RES2 (0x1000)
#define PHY_COMMON_AUTO_ADV_AS_PAUSE (0x0800)
#define PHY_COMMON_AUTO_ADV_PAUSE (0x0400)
#define PHY_COMMON_AUTO_ADV_100BT4 (0x0200)
-#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100)
+#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100)
#define PHY_COMMON_AUTO_ADV_100BTX (0x0080)
-#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040)
-#define PHY_COMMON_AUTO_ADV_10BT (0x0020)
+#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040)
+#define PHY_COMMON_AUTO_ADV_10BT (0x0020)
#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA (0x001F)
#define PHY_COMMON_AUTO_ADV_802_9 (0x0002)
#define PHY_COMMON_AUTO_ADV_802_3 (0x0001)
/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */
-#define PHY_COMMON_AUTO_LNKB_NP (0x8000)
+#define PHY_COMMON_AUTO_LNKB_NP (0x8000)
#define PHY_COMMON_AUTO_LNKB_ACK (0x4000)
#define PHY_COMMON_AUTO_LNKB_RMT_FLT (0x2000)
#define PHY_COMMON_AUTO_LNKB_RES2 (0x1000)
@@ -107,8 +107,8 @@
#define PHY_COMMON_AUTO_LNKB_100BT4 (0x0200)
#define PHY_COMMON_AUTO_LNKB_100BTXFD (0x0100)
#define PHY_COMMON_AUTO_LNKB_100BTX (0x0080)
-#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040)
-#define PHY_COMMON_AUTO_LNKB_10BT (0x0020)
+#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040)
+#define PHY_COMMON_AUTO_LNKB_10BT (0x0020)
#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
#define PHY_COMMON_AUTO_LNKB_802_9 (0x0002)
#define PHY_COMMON_AUTO_LNKB_802_3 (0x0001)
@@ -159,20 +159,20 @@
#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
/* STAT2 Status Register #2 Bit Fields */
-#define PHY_LXT971_STAT2_RES1 (0x8000)
-#define PHY_LXT971_STAT2_100BTX (0x4000)
+#define PHY_LXT971_STAT2_RES1 (0x8000)
+#define PHY_LXT971_STAT2_100BTX (0x4000)
#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
-#define PHY_LXT971_STAT2_LINK (0x0400)
+#define PHY_LXT971_STAT2_LINK (0x0400)
#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
-#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
-#define PHY_LXT971_STAT2_RES2 (0x0040)
+#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
+#define PHY_LXT971_STAT2_RES2 (0x0040)
#define PHY_LXT971_STAT2_POLARITY (0x0020)
-#define PHY_LXT971_STAT2_PAUSE (0x0010)
-#define PHY_LXT971_STAT2_ERROR (0x0008)
-#define PHY_LXT971_STAT2_RES3 (0x0007)
+#define PHY_LXT971_STAT2_PAUSE (0x0010)
+#define PHY_LXT971_STAT2_ERROR (0x0008)
+#define PHY_LXT971_STAT2_RES3 (0x0007)
/* INT_ENABLE Interrupt Enable Register Bit Fields */
#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
@@ -225,11 +225,11 @@
#define PHY_LXT971_LED_CFG_SPEED (0x0000)
/* DIG_CFG Digitial Configuration Register Bit Fields */
-#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
+#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
-#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
+#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
-#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
+#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
#define PHY_LXT971_MDIO_MAX_CLK (8000000)
#define PHY_MDIO_MAX_CLK (2500000)
diff --git a/include/mpc106.h b/include/mpc106.h
index ab6d57e..10ed0f4 100644
--- a/include/mpc106.h
+++ b/include/mpc106.h
@@ -28,7 +28,7 @@
* Defines for the MPC106 PCI Config address and data registers followed by
* defines for the standard PCI device configuration header.
*/
-#define PCIDEVID_MPC106 0x0
+#define PCIDEVID_MPC106 0x0
/*
* MPC106 Registers
@@ -36,7 +36,7 @@
#define MPC106_REG 0x80000000
#ifdef CFG_ADDRESS_MAP_A
-#define MPC106_REG_ADDR 0x80000cf8
+#define MPC106_REG_ADDR 0x80000cf8
#define MPC106_REG_DATA 0x80000cfc
#define MPC106_ISA_IO_PHYS 0x80000000
#define MPC106_ISA_IO_BUS 0x00000000
@@ -51,7 +51,7 @@
#define MPC106_PCI_MEMORY_BUS 0x80000000
#define MPC106_PCI_MEMORY_SIZE 0x80000000
#else
-#define MPC106_REG_ADDR 0xfec00cf8
+#define MPC106_REG_ADDR 0xfec00cf8
#define MPC106_REG_DATA 0xfee00cfc
#define MPC106_ISA_MEM_PHYS 0xfd000000
#define MPC106_ISA_MEM_BUS 0x00000000
@@ -77,9 +77,9 @@
#define PCI_STAT_NO_RSV_BITS 0xffff
-#define PCI_BUSNUM 0x40
-#define PCI_SUBBUSNUM 0x41
-#define PCI_DISCOUNT 0x42
+#define PCI_BUSNUM 0x40
+#define PCI_SUBBUSNUM 0x41
+#define PCI_DISCOUNT 0x42
#define PCI_PICR1 0xA8
#define PICR1_CF_CBA(value) ((value & 0xff) << 24)
diff --git a/include/net.h b/include/net.h
index 9a2f03f..79ddfa2 100644
--- a/include/net.h
+++ b/include/net.h
@@ -240,7 +240,7 @@ typedef struct
/*
* ICMP stuff (just enough to handle (host) redirect messages)
*/
-#define ICMP_ECHO_REPLY 0 /* Echo reply */
+#define ICMP_ECHO_REPLY 0 /* Echo reply */
#define ICMP_REDIRECT 5 /* Redirect (change route) */
#define ICMP_ECHO_REQUEST 8 /* Echo request */
@@ -327,12 +327,12 @@ extern unsigned NetIPID; /* IP ID (counting) */
extern uchar NetBcastAddr[6]; /* Ethernet boardcast address */
extern uchar NetEtherNullAddr[6];
-#define VLAN_NONE 4095 /* untagged */
-#define VLAN_IDMASK 0x0fff /* mask of valid vlan id */
-extern ushort NetOurVLAN; /* Our VLAN */
-extern ushort NetOurNativeVLAN; /* Our Native VLAN */
+#define VLAN_NONE 4095 /* untagged */
+#define VLAN_IDMASK 0x0fff /* mask of valid vlan id */
+extern ushort NetOurVLAN; /* Our VLAN */
+extern ushort NetOurNativeVLAN; /* Our Native VLAN */
-extern uchar NetCDPAddr[6]; /* Ethernet CDP address */
+extern uchar NetCDPAddr[6]; /* Ethernet CDP address */
extern ushort CDPNativeVLAN; /* CDP returned native VLAN */
extern ushort CDPApplianceVLAN; /* CDP returned appliance VLAN */
@@ -352,7 +352,7 @@ typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP
extern char BootFile[128]; /* Boot File name */
#if defined(CONFIG_CMD_PING)
-extern IPaddr_t NetPingIP; /* the ip address to ping */
+extern IPaddr_t NetPingIP; /* the ip address to ping */
#endif
#if defined(CONFIG_CMD_CDP)
@@ -362,7 +362,7 @@ extern ushort CDPApplianceVLAN;
#endif
#if defined(CONFIG_CMD_SNTP)
-extern IPaddr_t NetNtpServerIP; /* the ip address to NTP */
+extern IPaddr_t NetNtpServerIP; /* the ip address to NTP */
extern int NetTimeOffset; /* offset time from UTC */
#endif
@@ -376,7 +376,7 @@ extern void NetStop(void);
extern void NetStartAgain(void);
/* Get size of the ethernet header when we send */
-extern int NetEthHdrSize(void);
+extern int NetEthHdrSize(void);
/* Set ethernet header; returns the size of the header */
extern int NetSetEther(volatile uchar *, uchar *, uint);
diff --git a/include/nios2-epcs.h b/include/nios2-epcs.h
index 20e0c87..325cf71 100644
--- a/include/nios2-epcs.h
+++ b/include/nios2-epcs.h
@@ -29,7 +29,7 @@
#define __NIOS2_EPCS_H__
typedef struct epcs_devinfo_t {
- const char *name; /* Device name */
+ const char *name; /* Device name */
unsigned char id; /* Device silicon id */
unsigned char size; /* Total size log2(bytes)*/
unsigned char num_sects; /* Number of sectors */
diff --git a/include/nios2-io.h b/include/nios2-io.h
index d5c8652..dc87f1f 100644
--- a/include/nios2-io.h
+++ b/include/nios2-io.h
@@ -156,14 +156,14 @@ typedef volatile struct nios_jtag_t {
#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/
#define NIOS_JTAG_AC (1 << 10) /* activity indicator */
#define NIOS_JTAG_RRDY (1 << 12) /* read available */
-#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */
+#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */
/*------------------------------------------------------------------------
* SYSTEM ID
*----------------------------------------------------------------------*/
typedef volatile struct nios_sysid_t {
- unsigned id; /* The system build id*/
- unsigned timestamp; /* Timestamp */
+ unsigned id; /* The system build id*/
+ unsigned timestamp; /* Timestamp */
}nios_sysid_t;
#endif /* __NIOS2IO_H__ */
diff --git a/include/ns7520_eth.h b/include/ns7520_eth.h
index 5019802..123e6f4 100644
--- a/include/ns7520_eth.h
+++ b/include/ns7520_eth.h
@@ -28,7 +28,7 @@
/* The port addresses */
-#define NS7520_ETH_MODULE_BASE (0xFF800000)
+#define NS7520_ETH_MODULE_BASE (0xFF800000)
#define get_eth_reg_addr(c) \
((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c)))
@@ -153,7 +153,7 @@
/* MAC1 MAC Configuration Register 1 Bit Fields*/
-#define NS7520_ETH_MAC1_RES1 (0xFFFF0000) /* Reserved */
+#define NS7520_ETH_MAC1_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_MAC1_SRST (0x00008000) /* Soft Reset */
#define NS7520_ETH_MAC1_SIMMRST (0x00004000) /* Simulation Reset */
#define NS7520_ETH_MAC1_RES2 (0x00003000) /* Reserved */
@@ -170,7 +170,7 @@
/* MAC Configuration Register 2 Bit Fields*/
-#define NS7520_ETH_MAC2_RES1 (0xFFFF8000) /* Reserved */
+#define NS7520_ETH_MAC2_RES1 (0xFFFF8000) /* Reserved */
#define NS7520_ETH_MAC2_EDEFER (0x00004000) /* Excess Deferral */
#define NS7520_ETH_MAC2_BACKP (0x00002000) /* Backpressure/NO back off */
#define NS7520_ETH_MAC2_NOBO (0x00001000) /* No back off */
@@ -179,7 +179,7 @@
#define NS7520_ETH_MAC2_PUREP (0x00000100) /* Pure preamble enforcement */
#define NS7520_ETH_MAC2_AUTOP (0x00000080) /* Auto detect PAD enable */
#define NS7520_ETH_MAC2_VLANP (0x00000040) /* VLAN pad enable */
-#define NS7520_ETH_MAC2_PADEN (0x00000020) /* PAD/CRC enable */
+#define NS7520_ETH_MAC2_PADEN (0x00000020) /* PAD/CRC enable */
#define NS7520_ETH_MAC2_CRCEN (0x00000010) /* CRC enable */
#define NS7520_ETH_MAC2_DELCRC (0x00000008) /* Delayed CRC */
#define NS7520_ETH_MAC2_HUGE (0x00000004) /* Huge frame enable */
diff --git a/include/ns9750_bbus.h b/include/ns9750_bbus.h
index 0918931..9485338 100644
--- a/include/ns9750_bbus.h
+++ b/include/ns9750_bbus.h
@@ -44,7 +44,7 @@
They should be wrapped by cli()/sti() */
#define set_gpio_cfg_reg_val(pin,cfg) \
*get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \
- ~NS9750_GPIO_CFG_MASK((pin))) |\
+ ~NS9750_GPIO_CFG_MASK((pin))) |\
NS9750_GPIO_CFG_VAL((pin),(cfg));
#define NS9750_GPIO_CFG_MASK(pin) (NS9750_GPIO_CFG_VAL(pin, \
@@ -93,16 +93,16 @@
#define NS9750_BBUS_DMA_INT_BINT12 (0x00001000)
#define NS9750_BBUS_DMA_INT_BINT11 (0x00000800)
#define NS9750_BBUS_DMA_INT_BINT10 (0x00000400)
-#define NS9750_BBUS_DMA_INT_BINT9 (0x00000200)
-#define NS9750_BBUS_DMA_INT_BINT8 (0x00000100)
-#define NS9750_BBUS_DMA_INT_BINT7 (0x00000080)
-#define NS9750_BBUS_DMA_INT_BINT6 (0x00000040)
-#define NS9750_BBUS_DMA_INT_BINT5 (0x00000020)
-#define NS9750_BBUS_DMA_INT_BINT4 (0x00000010)
-#define NS9750_BBUS_DMA_INT_BINT3 (0x00000008)
-#define NS9750_BBUS_DMA_INT_BINT2 (0x00000004)
-#define NS9750_BBUS_DMA_INT_BINT1 (0x00000002)
-#define NS9750_BBUS_DMA_INT_BINT0 (0x00000001)
+#define NS9750_BBUS_DMA_INT_BINT9 (0x00000200)
+#define NS9750_BBUS_DMA_INT_BINT8 (0x00000100)
+#define NS9750_BBUS_DMA_INT_BINT7 (0x00000080)
+#define NS9750_BBUS_DMA_INT_BINT6 (0x00000040)
+#define NS9750_BBUS_DMA_INT_BINT5 (0x00000020)
+#define NS9750_BBUS_DMA_INT_BINT4 (0x00000010)
+#define NS9750_BBUS_DMA_INT_BINT3 (0x00000008)
+#define NS9750_BBUS_DMA_INT_BINT2 (0x00000004)
+#define NS9750_BBUS_DMA_INT_BINT1 (0x00000002)
+#define NS9750_BBUS_DMA_INT_BINT0 (0x00000001)
#define NS9750_BBUS_USB_CFG_OUTEN (0x00000008)
#define NS9750_BBUS_USB_CFG_SPEED (0x00000004)
diff --git a/include/ns9750_eth.h b/include/ns9750_eth.h
index 978c0bb..a6e5889 100644
--- a/include/ns9750_eth.h
+++ b/include/ns9750_eth.h
@@ -33,19 +33,19 @@
#include "lxt971a.h"
-#define NS9750_ETH_MODULE_BASE (0xA0600000)
+#define NS9750_ETH_MODULE_BASE (0xA0600000)
#define get_eth_reg_addr(c) \
((volatile unsigned int*) ( NS9750_ETH_MODULE_BASE+(unsigned int) (c)))
-#define NS9750_ETH_EGCR1 (0x0000)
-#define NS9750_ETH_EGCR2 (0x0004)
-#define NS9750_ETH_EGSR (0x0008)
-#define NS9750_ETH_FIFORX (0x000C)
-#define NS9750_ETH_FIFOTX (0x0010)
-#define NS9750_ETH_FIFOTXS (0x0014)
-#define NS9750_ETH_ETSR (0x0018)
-#define NS9750_ETH_ERSR (0x001C)
+#define NS9750_ETH_EGCR1 (0x0000)
+#define NS9750_ETH_EGCR2 (0x0004)
+#define NS9750_ETH_EGSR (0x0008)
+#define NS9750_ETH_FIFORX (0x000C)
+#define NS9750_ETH_FIFOTX (0x0010)
+#define NS9750_ETH_FIFOTXS (0x0014)
+#define NS9750_ETH_ETSR (0x0018)
+#define NS9750_ETH_ERSR (0x001C)
#define NS9750_ETH_MAC1 (0x0400)
#define NS9750_ETH_MAC2 (0x0404)
#define NS9750_ETH_IPGT (0x0408)
@@ -64,9 +64,9 @@
#define NS9750_ETH_SA2 (0x0444)
#define NS9750_ETH_SA3 (0x0448)
#define NS9750_ETH_SAFR (0x0500)
-#define NS9750_ETH_HT1 (0x0504)
-#define NS9750_ETH_HT2 (0x0508)
-#define NS9750_ETH_STAT_BASE (0x0680)
+#define NS9750_ETH_HT1 (0x0504)
+#define NS9750_ETH_HT2 (0x0508)
+#define NS9750_ETH_STAT_BASE (0x0680)
#define NS9750_ETH_RXAPTR (0x0A00)
#define NS9750_ETH_RXBPTR (0x0A04)
#define NS9750_ETH_RXCPTR (0x0A08)
@@ -87,26 +87,26 @@
/* register bit fields */
-#define NS9750_ETH_EGCR1_ERX (0x80000000)
-#define NS9750_ETH_EGCR1_ERXDMA (0x40000000)
-#define NS9750_ETH_EGCR1_ERXSHT (0x10000000)
-#define NS9750_ETH_EGCR1_ERXSIZ (0x08000000)
-#define NS9750_ETH_EGCR1_ETXSIZ (0x04000000)
+#define NS9750_ETH_EGCR1_ERX (0x80000000)
+#define NS9750_ETH_EGCR1_ERXDMA (0x40000000)
+#define NS9750_ETH_EGCR1_ERXSHT (0x10000000)
+#define NS9750_ETH_EGCR1_ERXSIZ (0x08000000)
+#define NS9750_ETH_EGCR1_ETXSIZ (0x04000000)
#define NS9750_ETH_EGCR1_ETXDIAG (0x02000000)
-#define NS9750_ETH_EGCR1_ERXBAD (0x01000000)
-#define NS9750_ETH_EGCR1_ETX (0x00800000)
-#define NS9750_ETH_EGCR1_ETXDMA (0x00400000)
-#define NS9750_ETH_EGCR1_ETXWM (0x00200000)
-#define NS9750_ETH_EGCR1_ERXADV (0x00100000)
+#define NS9750_ETH_EGCR1_ERXBAD (0x01000000)
+#define NS9750_ETH_EGCR1_ETX (0x00800000)
+#define NS9750_ETH_EGCR1_ETXDMA (0x00400000)
+#define NS9750_ETH_EGCR1_ETXWM (0x00200000)
+#define NS9750_ETH_EGCR1_ERXADV (0x00100000)
#define NS9750_ETH_EGCR1_ERXINIT (0x00080000)
-#define NS9750_ETH_EGCR1_PHY_MODE_MA (0x0000C000)
-#define NS9750_ETH_EGCR1_PHY_MODE_MII (0x00008000)
-#define NS9750_ETH_EGCR1_PHY_MODE_RMII (0x00004000)
-#define NS9750_ETH_EGCR1_RXCINV (0x00001000)
-#define NS9750_ETH_EGCR1_TXCINV (0x00000800)
+#define NS9750_ETH_EGCR1_PHY_MODE_MA (0x0000C000)
+#define NS9750_ETH_EGCR1_PHY_MODE_MII (0x00008000)
+#define NS9750_ETH_EGCR1_PHY_MODE_RMII (0x00004000)
+#define NS9750_ETH_EGCR1_RXCINV (0x00001000)
+#define NS9750_ETH_EGCR1_TXCINV (0x00000800)
#define NS9750_ETH_EGCR1_RXALIGN (0x00000400)
-#define NS9750_ETH_EGCR1_MAC_HRST (0x00000200)
-#define NS9750_ETH_EGCR1_ITXA (0x00000100)
+#define NS9750_ETH_EGCR1_MAC_HRST (0x00000200)
+#define NS9750_ETH_EGCR1_ITXA (0x00000100)
#define NS9750_ETH_EGCR2_TPTV_MA (0xFFFF0000)
#define NS9750_ETH_EGCR2_TPCF (0x00000040)
@@ -116,10 +116,10 @@
#define NS9750_ETH_EGCR2_CLRCNT (0x00000002)
#define NS9750_ETH_EGCR2_STEN (0x00000001)
-#define NS9750_ETH_EGSR_RXINIT (0x00100000)
-#define NS9750_ETH_EGSR_TXFIFONF (0x00080000)
-#define NS9750_ETH_EGSR_TXFIFOH (0x00040000)
-#define NS9750_ETH_EGSR_TXFIFOE (0x00010000)
+#define NS9750_ETH_EGSR_RXINIT (0x00100000)
+#define NS9750_ETH_EGSR_TXFIFONF (0x00080000)
+#define NS9750_ETH_EGSR_TXFIFOH (0x00040000)
+#define NS9750_ETH_EGSR_TXFIFOE (0x00010000)
#define NS9750_ETH_FIFOTXS_ALL (0x00000055)
#define NS9750_ETH_FIFOTXS_3 (0x000000d5)
@@ -127,116 +127,116 @@
#define NS9750_ETH_FIFOTXS_1 (0x0000000D)
#define NS9750_ETH_FIFOTXS_0 (0x00000003)
-#define NS9750_ETH_ETSR_TXOK (0x00008000)
-#define NS9750_ETH_ETSR_TXBR (0x00004000)
-#define NS9750_ETH_ETSR_TXMC (0x00002000)
-#define NS9750_ETH_ETSR_TXAL (0x00001000)
-#define NS9750_ETH_ETSR_TXAED (0x00000800)
-#define NS9750_ETH_ETSR_TXAEC (0x00000400)
-#define NS9750_ETH_ETSR_TXAUR (0x00000200)
-#define NS9750_ETH_ETSR_TXAJ (0x00000100)
-#define NS9750_ETH_ETSR_TXDEF (0x00000040)
-#define NS9750_ETH_ETSR_TXCRC (0x00000020)
-#define NS9750_ETH_ETSR_TXCOLC (0x0000000F)
+#define NS9750_ETH_ETSR_TXOK (0x00008000)
+#define NS9750_ETH_ETSR_TXBR (0x00004000)
+#define NS9750_ETH_ETSR_TXMC (0x00002000)
+#define NS9750_ETH_ETSR_TXAL (0x00001000)
+#define NS9750_ETH_ETSR_TXAED (0x00000800)
+#define NS9750_ETH_ETSR_TXAEC (0x00000400)
+#define NS9750_ETH_ETSR_TXAUR (0x00000200)
+#define NS9750_ETH_ETSR_TXAJ (0x00000100)
+#define NS9750_ETH_ETSR_TXDEF (0x00000040)
+#define NS9750_ETH_ETSR_TXCRC (0x00000020)
+#define NS9750_ETH_ETSR_TXCOLC (0x0000000F)
#define NS9750_ETH_ERSR_RXSIZE_MA (0x0FFF0000)
-#define NS9750_ETH_ERSR_RXCE (0x00008000)
-#define NS9750_ETH_ERSR_RXDV (0x00004000)
-#define NS9750_ETH_ERSR_RXOK (0x00002000)
-#define NS9750_ETH_ERSR_RXBR (0x00001000)
-#define NS9750_ETH_ERSR_RXMC (0x00000800)
-#define NS9750_ETH_ERSR_RXCRC (0x00000400)
-#define NS9750_ETH_ERSR_RXDR (0x00000200)
-#define NS9750_ETH_ERSR_RXCV (0x00000100)
-#define NS9750_ETH_ERSR_RXSHT (0x00000040)
-
-#define NS9750_ETH_MAC1_SRST (0x00008000)
-#define NS9750_ETH_MAC1_SIMMRST (0x00004000)
-#define NS9750_ETH_MAC1_RPEMCSR (0x00000800)
-#define NS9750_ETH_MAC1_RPERFUN (0x00000400)
-#define NS9750_ETH_MAC1_RPEMCST (0x00000200)
-#define NS9750_ETH_MAC1_RPETFUN (0x00000100)
-#define NS9750_ETH_MAC1_LOOPBK (0x00000010)
-#define NS9750_ETH_MAC1_TXFLOW (0x00000008)
-#define NS9750_ETH_MAC1_RXFLOW (0x00000004)
-#define NS9750_ETH_MAC1_PALLRX (0x00000002)
-#define NS9750_ETH_MAC1_RXEN (0x00000001)
-
-#define NS9750_ETH_MAC2_EDEFER (0x00004000)
-#define NS9750_ETH_MAC2_BACKP (0x00002000)
-#define NS9750_ETH_MAC2_NOBO (0x00001000)
-#define NS9750_ETH_MAC2_LONGP (0x00000200)
-#define NS9750_ETH_MAC2_PUREP (0x00000100)
-#define NS9750_ETH_MAC2_AUTOP (0x00000080)
-#define NS9750_ETH_MAC2_VLANP (0x00000040)
-#define NS9750_ETH_MAC2_PADEN (0x00000020)
-#define NS9750_ETH_MAC2_CRCEN (0x00000010)
-#define NS9750_ETH_MAC2_DELCRC (0x00000008)
-#define NS9750_ETH_MAC2_HUGE (0x00000004)
-#define NS9750_ETH_MAC2_FLENC (0x00000002)
-#define NS9750_ETH_MAC2_FULLD (0x00000001)
-
-#define NS9750_ETH_IPGT_MA (0x0000007F)
-
-#define NS9750_ETH_IPGR_IPGR1 (0x00007F00)
-#define NS9750_ETH_IPGR_IPGR2 (0x0000007F)
-
-#define NS9750_ETH_CLRT_CWIN (0x00003F00)
-#define NS9750_ETH_CLRT_RETX (0x0000000F)
-
-#define NS9750_ETH_MAXF_MAXF (0x0000FFFF)
-
-#define NS9750_ETH_SUPP_RPERMII (0x00008000)
-#define NS9750_ETH_SUPP_SPEED (0x00000080)
-
-#define NS9750_ETH_TEST_TBACK (0x00000004)
-#define NS9750_ETH_TEST_TPAUSE (0x00000002)
-#define NS9750_ETH_TEST_SPQ (0x00000001)
-
-#define NS9750_ETH_MCFG_RMIIM (0x00008000)
-#define NS9750_ETH_MCFG_CLKS_MA (0x0000001C)
-#define NS9750_ETH_MCFG_CLKS_4 (0x00000004)
-#define NS9750_ETH_MCFG_CLKS_6 (0x00000008)
-#define NS9750_ETH_MCFG_CLKS_8 (0x0000000C)
-#define NS9750_ETH_MCFG_CLKS_10 (0x00000010)
-#define NS9750_ETH_MCFG_CLKS_20 (0x00000014)
-#define NS9750_ETH_MCFG_CLKS_30 (0x00000018)
-#define NS9750_ETH_MCFG_CLKS_40 (0x0000001C)
-#define NS9750_ETH_MCFG_SPRE (0x00000002)
-#define NS9750_ETH_MCFG_SCANI (0x00000001)
-
-#define NS9750_ETH_MCMD_SCAN (0x00000002)
-#define NS9750_ETH_MCMD_READ (0x00000001)
-
-#define NS9750_ETH_MADR_DADR_MA (0x00001F00)
-#define NS9750_ETH_MADR_RADR_MA (0x0000001F)
-
-#define NS9750_ETH_MWTD_MA (0x0000FFFF)
-
-#define NS9750_ETH_MRRD_MA (0x0000FFFF)
+#define NS9750_ETH_ERSR_RXCE (0x00008000)
+#define NS9750_ETH_ERSR_RXDV (0x00004000)
+#define NS9750_ETH_ERSR_RXOK (0x00002000)
+#define NS9750_ETH_ERSR_RXBR (0x00001000)
+#define NS9750_ETH_ERSR_RXMC (0x00000800)
+#define NS9750_ETH_ERSR_RXCRC (0x00000400)
+#define NS9750_ETH_ERSR_RXDR (0x00000200)
+#define NS9750_ETH_ERSR_RXCV (0x00000100)
+#define NS9750_ETH_ERSR_RXSHT (0x00000040)
+
+#define NS9750_ETH_MAC1_SRST (0x00008000)
+#define NS9750_ETH_MAC1_SIMMRST (0x00004000)
+#define NS9750_ETH_MAC1_RPEMCSR (0x00000800)
+#define NS9750_ETH_MAC1_RPERFUN (0x00000400)
+#define NS9750_ETH_MAC1_RPEMCST (0x00000200)
+#define NS9750_ETH_MAC1_RPETFUN (0x00000100)
+#define NS9750_ETH_MAC1_LOOPBK (0x00000010)
+#define NS9750_ETH_MAC1_TXFLOW (0x00000008)
+#define NS9750_ETH_MAC1_RXFLOW (0x00000004)
+#define NS9750_ETH_MAC1_PALLRX (0x00000002)
+#define NS9750_ETH_MAC1_RXEN (0x00000001)
+
+#define NS9750_ETH_MAC2_EDEFER (0x00004000)
+#define NS9750_ETH_MAC2_BACKP (0x00002000)
+#define NS9750_ETH_MAC2_NOBO (0x00001000)
+#define NS9750_ETH_MAC2_LONGP (0x00000200)
+#define NS9750_ETH_MAC2_PUREP (0x00000100)
+#define NS9750_ETH_MAC2_AUTOP (0x00000080)
+#define NS9750_ETH_MAC2_VLANP (0x00000040)
+#define NS9750_ETH_MAC2_PADEN (0x00000020)
+#define NS9750_ETH_MAC2_CRCEN (0x00000010)
+#define NS9750_ETH_MAC2_DELCRC (0x00000008)
+#define NS9750_ETH_MAC2_HUGE (0x00000004)
+#define NS9750_ETH_MAC2_FLENC (0x00000002)
+#define NS9750_ETH_MAC2_FULLD (0x00000001)
+
+#define NS9750_ETH_IPGT_MA (0x0000007F)
+
+#define NS9750_ETH_IPGR_IPGR1 (0x00007F00)
+#define NS9750_ETH_IPGR_IPGR2 (0x0000007F)
+
+#define NS9750_ETH_CLRT_CWIN (0x00003F00)
+#define NS9750_ETH_CLRT_RETX (0x0000000F)
+
+#define NS9750_ETH_MAXF_MAXF (0x0000FFFF)
+
+#define NS9750_ETH_SUPP_RPERMII (0x00008000)
+#define NS9750_ETH_SUPP_SPEED (0x00000080)
+
+#define NS9750_ETH_TEST_TBACK (0x00000004)
+#define NS9750_ETH_TEST_TPAUSE (0x00000002)
+#define NS9750_ETH_TEST_SPQ (0x00000001)
+
+#define NS9750_ETH_MCFG_RMIIM (0x00008000)
+#define NS9750_ETH_MCFG_CLKS_MA (0x0000001C)
+#define NS9750_ETH_MCFG_CLKS_4 (0x00000004)
+#define NS9750_ETH_MCFG_CLKS_6 (0x00000008)
+#define NS9750_ETH_MCFG_CLKS_8 (0x0000000C)
+#define NS9750_ETH_MCFG_CLKS_10 (0x00000010)
+#define NS9750_ETH_MCFG_CLKS_20 (0x00000014)
+#define NS9750_ETH_MCFG_CLKS_30 (0x00000018)
+#define NS9750_ETH_MCFG_CLKS_40 (0x0000001C)
+#define NS9750_ETH_MCFG_SPRE (0x00000002)
+#define NS9750_ETH_MCFG_SCANI (0x00000001)
+
+#define NS9750_ETH_MCMD_SCAN (0x00000002)
+#define NS9750_ETH_MCMD_READ (0x00000001)
+
+#define NS9750_ETH_MADR_DADR_MA (0x00001F00)
+#define NS9750_ETH_MADR_RADR_MA (0x0000001F)
+
+#define NS9750_ETH_MWTD_MA (0x0000FFFF)
+
+#define NS9750_ETH_MRRD_MA (0x0000FFFF)
#define NS9750_ETH_MIND_MIILF (0x00000008)
#define NS9750_ETH_MIND_NVALID (0x00000004)
-#define NS9750_ETH_MIND_SCAN (0x00000002)
-#define NS9750_ETH_MIND_BUSY (0x00000001)
+#define NS9750_ETH_MIND_SCAN (0x00000002)
+#define NS9750_ETH_MIND_BUSY (0x00000001)
-#define NS9750_ETH_SA1_OCTET1_MA (0x0000FF00)
-#define NS9750_ETH_SA1_OCTET2_MA (0x000000FF)
+#define NS9750_ETH_SA1_OCTET1_MA (0x0000FF00)
+#define NS9750_ETH_SA1_OCTET2_MA (0x000000FF)
-#define NS9750_ETH_SA2_OCTET3_MA (0x0000FF00)
-#define NS9750_ETH_SA2_OCTET4_MA (0x000000FF)
+#define NS9750_ETH_SA2_OCTET3_MA (0x0000FF00)
+#define NS9750_ETH_SA2_OCTET4_MA (0x000000FF)
-#define NS9750_ETH_SA3_OCTET5_MA (0x0000FF00)
-#define NS9750_ETH_SA3_OCTET6_MA (0x000000FF)
+#define NS9750_ETH_SA3_OCTET5_MA (0x0000FF00)
+#define NS9750_ETH_SA3_OCTET6_MA (0x000000FF)
-#define NS9750_ETH_SAFR_PRO (0x00000008)
-#define NS9750_ETH_SAFR_PRM (0x00000004)
-#define NS9750_ETH_SAFR_PRA (0x00000002)
-#define NS9750_ETH_SAFR_BROAD (0x00000001)
+#define NS9750_ETH_SAFR_PRO (0x00000008)
+#define NS9750_ETH_SAFR_PRM (0x00000004)
+#define NS9750_ETH_SAFR_PRA (0x00000002)
+#define NS9750_ETH_SAFR_BROAD (0x00000001)
-#define NS9750_ETH_HT1_MA (0x0000FFFF)
+#define NS9750_ETH_HT1_MA (0x0000FFFF)
-#define NS9750_ETH_HT2_MA (0x0000FFFF)
+#define NS9750_ETH_HT2_MA (0x0000FFFF)
/* also valid for EINTREN */
#define NS9750_ETH_EINTR_RXOVL_DATA (0x02000000)
@@ -254,7 +254,7 @@
#define NS9750_ETH_EINTR_TXBUFC (0x00000010)
#define NS9750_ETH_EINTR_TXBUFNR (0x00000008)
#define NS9750_ETH_EINTR_TXDONE (0x00000004)
-#define NS9750_ETH_EINTR_TXERR (0x00000002)
+#define NS9750_ETH_EINTR_TXERR (0x00000002)
#define NS9750_ETH_EINTR_TXIDLE (0x00000001)
#define NS9750_ETH_EINTR_RX_MA \
(NS9750_ETH_EINTR_RXOVL_DATA | \
@@ -289,7 +289,7 @@
#define NS9750_ETH_RXFREE_A (0x00000001)
#ifndef NS9750_ETH_PHY_ADDRESS
-# define NS9750_ETH_PHY_ADDRESS (0x0001) /* suitable for UNC20 */
+# define NS9750_ETH_PHY_ADDRESS (0x0001) /* suitable for UNC20 */
#endif /* NETARM_ETH_PHY_ADDRESS */
#endif /* CONFIG_DRIVER_NS9750_ETHERNET */
diff --git a/include/ns9750_mem.h b/include/ns9750_mem.h
index 44c8ddc..666e412 100644
--- a/include/ns9750_mem.h
+++ b/include/ns9750_mem.h
@@ -35,23 +35,23 @@
/* the register addresses */
-#define NS9750_MEM_CTRL (0x0000)
-#define NS9750_MEM_STATUS (0x0004)
-#define NS9750_MEM_CFG (0x0008)
-#define NS9750_MEM_DYN_CTRL (0x0020)
-#define NS9750_MEM_DYN_REFRESH (0x0024)
+#define NS9750_MEM_CTRL (0x0000)
+#define NS9750_MEM_STATUS (0x0004)
+#define NS9750_MEM_CFG (0x0008)
+#define NS9750_MEM_DYN_CTRL (0x0020)
+#define NS9750_MEM_DYN_REFRESH (0x0024)
#define NS9750_MEM_DYN_READ_CFG (0x0028)
-#define NS9750_MEM_DYN_TRP (0x0030)
-#define NS9750_MEM_DYN_TRAS (0x0034)
-#define NS9750_MEM_DYN_TSREX (0x0038)
-#define NS9750_MEM_DYN_TAPR (0x003C)
-#define NS9750_MEM_DYN_TDAL (0x0040)
-#define NS9750_MEM_DYN_TWR (0x0044)
-#define NS9750_MEM_DYN_TRC (0x0048)
-#define NS9750_MEM_DYN_TRFC (0x004C)
-#define NS9750_MEM_DYN_TXSR (0x0050)
-#define NS9750_MEM_DYN_TRRD (0x0054)
-#define NS9750_MEM_DYN_TMRD (0x0058)
+#define NS9750_MEM_DYN_TRP (0x0030)
+#define NS9750_MEM_DYN_TRAS (0x0034)
+#define NS9750_MEM_DYN_TSREX (0x0038)
+#define NS9750_MEM_DYN_TAPR (0x003C)
+#define NS9750_MEM_DYN_TDAL (0x0040)
+#define NS9750_MEM_DYN_TWR (0x0044)
+#define NS9750_MEM_DYN_TRC (0x0048)
+#define NS9750_MEM_DYN_TRFC (0x004C)
+#define NS9750_MEM_DYN_TXSR (0x0050)
+#define NS9750_MEM_DYN_TRRD (0x0054)
+#define NS9750_MEM_DYN_TMRD (0x0058)
#define NS9750_MEM_STAT_EXT_WAIT (0x0080)
#define NS9750_MEM_DYN_CFG_BASE (0x0100)
#define NS9750_MEM_DYN_RAS_CAS_BASE (0x0104)
@@ -102,7 +102,7 @@
#define NS9750_MEM_DYN_REFRESH_MA (0x000007FF)
#define NS9750_MEM_DYN_READ_CFG_MA (0x00000003)
-#define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001)
+#define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001)
#define NS9750_MEM_DYN_READ_CFG_DELAY1 (0x00000002)
#define NS9750_MEM_DYN_READ_CFG_DELAY2 (0x00000003)
@@ -137,13 +137,13 @@
#define NS9750_MEM_DYN_CFG_MD (0x00000018)
#define NS9750_MEM_DYN_RAS_CAS_CAS_MA (0x00000300)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_1 (0x00000100)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_2 (0x00000200)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_3 (0x00000300)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_1 (0x00000100)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_2 (0x00000200)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_3 (0x00000300)
#define NS9750_MEM_DYN_RAS_CAS_RAS_MA (0x00000003)
#define NS9750_MEM_DYN_RAS_CAS_RAS_1 (0x00000001)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_2 (0x00000002)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_3 (0x00000003)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_2 (0x00000002)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_3 (0x00000003)
#define NS9750_MEM_STAT_CFG_PSMC (0x00100000)
#define NS9750_MEM_STAT_CFG_BSMC (0x00080000)
@@ -153,7 +153,7 @@
#define NS9750_MEM_STAT_CFG_PM (0x00000008)
#define NS9750_MEM_STAT_CFG_MW_MA (0x00000003)
#define NS9750_MEM_STAT_CFG_MW_8 (0x00000000)
-#define NS9750_MEM_STAT_CFG_MW_16 (0x00000001)
+#define NS9750_MEM_STAT_CFG_MW_16 (0x00000001)
#define NS9750_MEM_STAT_CFG_MW_32 (0x00000002)
#define NS9750_MEM_STAT_WAIT_WEN_MA (0x0000000F)
diff --git a/include/ns9750_ser.h b/include/ns9750_ser.h
index e6ff3e1..b5c297e 100644
--- a/include/ns9750_ser.h
+++ b/include/ns9750_ser.h
@@ -75,7 +75,7 @@
#define NS9750_SER_CTRL_A_ERXDMA (0x00000100)
#define NS9750_SER_CTRL_A_RIC_MA (0x000000E0)
#define NS9750_SER_CTRL_A_TIC_MA (0x0000001E)
-#define NS9750_SER_CTRL_A_ETXDMA (0x00000001)
+#define NS9750_SER_CTRL_A_ETXDMA (0x00000001)
/* control B register */
@@ -130,21 +130,21 @@
#define NS9750_SER_STAT_A_TEMPTY (0x00000001)
#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \
- NS9750_SER_STAT_A_ROVER | \
+ NS9750_SER_STAT_A_ROVER | \
NS9750_SER_STAT_A_RPE )
#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \
NS9750_SER_STAT_A_RBRK | \
NS9750_SER_STAT_A_RRDY | \
- NS9750_SER_STAT_A_RHALF | \
- NS9750_SER_STAT_A_RBC | \
- NS9750_SER_STAT_A_DCDI | \
- NS9750_SER_STAT_A_RII | \
- NS9750_SER_STAT_A_DSRI | \
- NS9750_SER_STAT_A_CTSI )
+ NS9750_SER_STAT_A_RHALF | \
+ NS9750_SER_STAT_A_RBC | \
+ NS9750_SER_STAT_A_DCDI | \
+ NS9750_SER_STAT_A_RII | \
+ NS9750_SER_STAT_A_DSRI | \
+ NS9750_SER_STAT_A_CTSI )
#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \
NS9750_SER_STAT_A_THALF | \
NS9750_SER_STAT_A_TBC | \
- NS9750_SER_STAT_A_TEMPTY )
+ NS9750_SER_STAT_A_TEMPTY )
/* bit rate register */
#define NS9750_SER_BITRATE_EBIT (0x80000000)
@@ -161,13 +161,13 @@
#define NS9750_SER_BITRATE_TXCINV (0x00800000)
#define NS9750_SER_BITRATE_RXCINV (0x00400000)
#define NS9750_SER_BITRATE_TCDR_MA (0x00180000)
-#define NS9750_SER_BITRATE_TCDR_1 (0x00000000)
-#define NS9750_SER_BITRATE_TCDR_8 (0x00080000)
+#define NS9750_SER_BITRATE_TCDR_1 (0x00000000)
+#define NS9750_SER_BITRATE_TCDR_8 (0x00080000)
#define NS9750_SER_BITRATE_TCDR_16 (0x00100000)
#define NS9750_SER_BITRATE_TCDR_32 (0x00180000)
#define NS9750_SER_BITRATE_RCDR_MA (0x00070000)
-#define NS9750_SER_BITRATE_RCDR_1 (0x00000000)
-#define NS9750_SER_BITRATE_RCDR_8 (0x00020000)
+#define NS9750_SER_BITRATE_RCDR_1 (0x00000000)
+#define NS9750_SER_BITRATE_RCDR_8 (0x00020000)
#define NS9750_SER_BITRATE_RCDR_16 (0x00040000)
#define NS9750_SER_BITRATE_RCDR_32 (0x00060000)
#define NS9750_SER_BITRATE_TICS (0x00010000)
diff --git a/include/ns9750_sys.h b/include/ns9750_sys.h
index c563cad..f1dc2b2 100644
--- a/include/ns9750_sys.h
+++ b/include/ns9750_sys.h
@@ -38,9 +38,9 @@
#define NS9750_SYS_AHB_GEN (0x0000)
#define NS9750_SYS_BRC_BASE (0x0004)
#define NS9750_SYS_AHB_TIMEOUT (0x0014)
-#define NS9750_SYS_AHB_ERROR1 (0x0018)
-#define NS9750_SYS_AHB_ERROR2 (0x001C)
-#define NS9750_SYS_AHB_MON (0x0020)
+#define NS9750_SYS_AHB_ERROR1 (0x0018)
+#define NS9750_SYS_AHB_ERROR2 (0x001C)
+#define NS9750_SYS_AHB_MON (0x0020)
#define NS9750_SYS_TIMER_COUNT_BASE (0x0044)
#define NS9750_SYS_TIMER_READ_BASE (0x0084)
#define NS9750_SYS_INT_VEC_ADR_BASE (0x00C4)
@@ -120,27 +120,27 @@
/* need to be n*8bit to Int Level */
#define NS9750_SYS_INT_CFG_IE (0x00000080)
-#define NS9750_SYS_INT_CFG_IT (0x00000020)
+#define NS9750_SYS_INT_CFG_IT (0x00000020)
#define NS9750_SYS_INT_CFG_IAD_MA (0x0000001F)
-#define NS9750_SYS_TIMER_INT_STAT_MA (0x0000FFFF)
+#define NS9750_SYS_TIMER_INT_STAT_MA (0x0000FFFF)
#define NS9750_SYS_SW_WDOG_CFG_SWWE (0x00000080)
#define NS9750_SYS_SW_WDOG_CFG_SWWI (0x00000020)
#define NS9750_SYS_SW_WDOG_CFG_SWWIC (0x00000010)
#define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA (0x00000007)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2 (0x00000000)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4 (0x00000001)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8 (0x00000002)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2 (0x00000000)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4 (0x00000001)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8 (0x00000002)
#define NS9750_SYS_SW_WDOG_CFG_SWTCS_16 (0x00000003)
#define NS9750_SYS_SW_WDOG_CFG_SWTCS_32 (0x00000004)
#define NS9750_SYS_SW_WDOG_CFG_SWTCS_64 (0x00000005)
#define NS9750_SYS_CLOCK_LPCS_MA (0x00000380)
-#define NS9750_SYS_CLOCK_LPCS_1 (0x00000000)
-#define NS9750_SYS_CLOCK_LPCS_2 (0x00000080)
-#define NS9750_SYS_CLOCK_LPCS_4 (0x00000100)
-#define NS9750_SYS_CLOCK_LPCS_8 (0x00000180)
+#define NS9750_SYS_CLOCK_LPCS_1 (0x00000000)
+#define NS9750_SYS_CLOCK_LPCS_2 (0x00000080)
+#define NS9750_SYS_CLOCK_LPCS_4 (0x00000100)
+#define NS9750_SYS_CLOCK_LPCS_8 (0x00000180)
#define NS9750_SYS_CLOCK_LPCS_EXT (0x00000200)
#define NS9750_SYS_CLOCK_BBC (0x00000040)
#define NS9750_SYS_CLOCK_LCC (0x00000020)
@@ -185,22 +185,22 @@
#define NS9750_SYS_PLL_CPCC_MA (0x00000060)
#define NS9750_SYS_PLL_NDSW_MA (0x0000001F)
-#define NS9750_SYS_ACT_INT_STAT_MA (0x0000FFFF)
+#define NS9750_SYS_ACT_INT_STAT_MA (0x0000FFFF)
#define NS9750_SYS_TIMER_CTRL_TEN (0x00008000)
#define NS9750_SYS_TIMER_CTRL_INTC (0x00000200)
#define NS9750_SYS_TIMER_CTRL_TLCS_MA (0x000001C0)
-#define NS9750_SYS_TIMER_CTRL_TLCS_1 (0x00000000)
-#define NS9750_SYS_TIMER_CTRL_TLCS_2 (0x00000040)
-#define NS9750_SYS_TIMER_CTRL_TLCS_4 (0x00000080)
-#define NS9750_SYS_TIMER_CTRL_TLCS_8 (0x000000C0)
+#define NS9750_SYS_TIMER_CTRL_TLCS_1 (0x00000000)
+#define NS9750_SYS_TIMER_CTRL_TLCS_2 (0x00000040)
+#define NS9750_SYS_TIMER_CTRL_TLCS_4 (0x00000080)
+#define NS9750_SYS_TIMER_CTRL_TLCS_8 (0x000000C0)
#define NS9750_SYS_TIMER_CTRL_TLCS_16 (0x00000100)
#define NS9750_SYS_TIMER_CTRL_TLCS_32 (0x00000140)
#define NS9750_SYS_TIMER_CTRL_TLCS_64 (0x00000180)
#define NS9750_SYS_TIMER_CTRL_TLCS_EXT (0x000001C0)
#define NS9750_SYS_TIMER_CTRL_TM_MA (0x00000030)
-#define NS9750_SYS_TIMER_CTRL_TM_INT (0x00000000)
-#define NS9750_SYS_TIMER_CTRL_TM_LOW (0x00000010)
+#define NS9750_SYS_TIMER_CTRL_TM_INT (0x00000000)
+#define NS9750_SYS_TIMER_CTRL_TM_LOW (0x00000010)
#define NS9750_SYS_TIMER_CTRL_TM_HIGH (0x00000020)
#define NS9750_SYS_TIMER_CTRL_INTS (0x00000008)
#define NS9750_SYS_TIMER_CTRL_UDS (0x00000004)
diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h
index bd1831e..4449f98 100644
--- a/include/onenand_uboot.h
+++ b/include/onenand_uboot.h
@@ -14,6 +14,8 @@
#ifndef __UBOOT_ONENAND_H
#define __UBOOT_ONENAND_H
+#include <linux/types.h>
+
struct kvec {
void *iov_base;
size_t iov_len;
@@ -22,6 +24,9 @@ struct kvec {
typedef int spinlock_t;
typedef int wait_queue_head_t;
+struct mtd_info;
+struct erase_info;
+
/* Functions */
extern void onenand_init(void);
extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
diff --git a/include/pc_keyb.h b/include/pc_keyb.h
index ab51703..5ba99e3 100644
--- a/include/pc_keyb.h
+++ b/include/pc_keyb.h
@@ -68,14 +68,14 @@ extern unsigned char aux_device_present;
/*
* Status Register Bits
*/
-#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
-#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
+#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
+#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
-#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
-#define KBD_STAT_PERR 0x80 /* Parity error */
+#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
+#define KBD_STAT_PERR 0x80 /* Parity error */
#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
@@ -84,11 +84,11 @@ extern unsigned char aux_device_present;
*/
#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
-#define KBD_MODE_SYS 0x04 /* The system flag (?) */
+#define KBD_MODE_SYS 0x04 /* The system flag (?) */
#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
-#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
+#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
#define KBD_MODE_RFU 0x80
/*
diff --git a/include/post.h b/include/post.h
index ee07d2c..123623f 100644
--- a/include/post.h
+++ b/include/post.h
@@ -43,6 +43,7 @@
#define POST_PREREL 0x1000 /* test runs before relocation */
#define POST_CRITICAL 0x2000 /* Use failbootcmd if test failed */
+#define POST_STOP 0x4000 /* Interrupt POST sequence on fail */
#define POST_MEM (POST_RAM | POST_ROM)
#define POST_ALWAYS (POST_NORMAL | \
@@ -94,7 +95,7 @@ extern int post_hotkeys_pressed(void);
#define CFG_POST_SPR 0x00000400
#define CFG_POST_SYSMON 0x00000800
#define CFG_POST_DSP 0x00001000
-#define CFG_POST_CODEC 0x00002000
+#define CFG_POST_OCM 0x00002000
#define CFG_POST_FPU 0x00004000
#define CFG_POST_ECC 0x00008000
#define CFG_POST_BSPEC1 0x00010000
@@ -102,6 +103,7 @@ extern int post_hotkeys_pressed(void);
#define CFG_POST_BSPEC3 0x00040000
#define CFG_POST_BSPEC4 0x00080000
#define CFG_POST_BSPEC5 0x00100000
+#define CFG_POST_CODEC 0x00200000
#endif /* CONFIG_POST */
diff --git a/include/ppc405.h b/include/ppc405.h
index 37b121c..d953378 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -1,22 +1,22 @@
/*----------------------------------------------------------------------------+
|
-| This source code has been made available to you by IBM on an AS-IS
-| basis. Anyone receiving this source is licensed under IBM
-| copyrights to use it in any way he or she deems fit, including
-| copying it, modifying it, compiling it, and redistributing it either
-| with or without modifications. No license under IBM patents or
-| patent applications is to be implied by the copyright license.
+| This source code has been made available to you by IBM on an AS-IS
+| basis. Anyone receiving this source is licensed under IBM
+| copyrights to use it in any way he or she deems fit, including
+| copying it, modifying it, compiling it, and redistributing it either
+| with or without modifications. No license under IBM patents or
+| patent applications is to be implied by the copyright license.
|
-| Any user of this software should understand that IBM cannot provide
-| technical support for this software and will not be responsible for
-| any consequences resulting from the use of this software.
+| Any user of this software should understand that IBM cannot provide
+| technical support for this software and will not be responsible for
+| any consequences resulting from the use of this software.
|
-| Any person who transfers this source code or any derivative work
-| must include the IBM copyright notice, this paragraph, and the
-| preceding two paragraphs in the transferred software.
+| Any person who transfers this source code or any derivative work
+| must include the IBM copyright notice, this paragraph, and the
+| preceding two paragraphs in the transferred software.
|
-| COPYRIGHT I B M CORPORATION 1999
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+| COPYRIGHT I B M CORPORATION 1999
+| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+----------------------------------------------------------------------------*/
#ifndef __PPC405_H__
@@ -31,8 +31,8 @@
/*--------------------------------------------------------------------- */
/* Special Purpose Registers */
/*--------------------------------------------------------------------- */
- #define srr2 0x3de /* save/restore register 2 */
- #define srr3 0x3df /* save/restore register 3 */
+ #define srr2 0x3de /* save/restore register 2 */
+ #define srr3 0x3df /* save/restore register 3 */
/*
* 405 does not really have CSRR0/1 but SRR2/3 are used during critical
@@ -42,46 +42,46 @@
#define csrr0 srr2
#define csrr1 srr3
- #define dbsr 0x3f0 /* debug status register */
- #define dbcr0 0x3f2 /* debug control register 0 */
- #define dbcr1 0x3bd /* debug control register 1 */
- #define iac1 0x3f4 /* instruction address comparator 1 */
- #define iac2 0x3f5 /* instruction address comparator 2 */
- #define iac3 0x3b4 /* instruction address comparator 3 */
- #define iac4 0x3b5 /* instruction address comparator 4 */
- #define dac1 0x3f6 /* data address comparator 1 */
- #define dac2 0x3f7 /* data address comparator 2 */
- #define dccr 0x3fa /* data cache control register */
- #define iccr 0x3fb /* instruction cache control register */
- #define esr 0x3d4 /* execption syndrome register */
- #define dear 0x3d5 /* data exeption address register */
- #define evpr 0x3d6 /* exeption vector prefix register */
- #define tsr 0x3d8 /* timer status register */
- #define tcr 0x3da /* timer control register */
- #define pit 0x3db /* programmable interval timer */
- #define sgr 0x3b9 /* storage guarded reg */
- #define dcwr 0x3ba /* data cache write-thru reg*/
- #define sler 0x3bb /* storage little-endian reg */
- #define cdbcr 0x3d7 /* cache debug cntrl reg */
- #define icdbdr 0x3d3 /* instr cache dbug data reg*/
- #define ccr0 0x3b3 /* core configuration register */
- #define dvc1 0x3b6 /* data value compare register 1 */
- #define dvc2 0x3b7 /* data value compare register 2 */
- #define pid 0x3b1 /* process ID */
- #define su0r 0x3bc /* storage user-defined register 0 */
- #define zpr 0x3b0 /* zone protection regsiter */
-
- #define tbl 0x11c /* time base lower - privileged write */
- #define tbu 0x11d /* time base upper - privileged write */
-
- #define sprg4r 0x104 /* Special purpose general 4 - read only */
- #define sprg5r 0x105 /* Special purpose general 5 - read only */
- #define sprg6r 0x106 /* Special purpose general 6 - read only */
- #define sprg7r 0x107 /* Special purpose general 7 - read only */
- #define sprg4w 0x114 /* Special purpose general 4 - write only */
- #define sprg5w 0x115 /* Special purpose general 5 - write only */
- #define sprg6w 0x116 /* Special purpose general 6 - write only */
- #define sprg7w 0x117 /* Special purpose general 7 - write only */
+ #define dbsr 0x3f0 /* debug status register */
+ #define dbcr0 0x3f2 /* debug control register 0 */
+ #define dbcr1 0x3bd /* debug control register 1 */
+ #define iac1 0x3f4 /* instruction address comparator 1 */
+ #define iac2 0x3f5 /* instruction address comparator 2 */
+ #define iac3 0x3b4 /* instruction address comparator 3 */
+ #define iac4 0x3b5 /* instruction address comparator 4 */
+ #define dac1 0x3f6 /* data address comparator 1 */
+ #define dac2 0x3f7 /* data address comparator 2 */
+ #define dccr 0x3fa /* data cache control register */
+ #define iccr 0x3fb /* instruction cache control register */
+ #define esr 0x3d4 /* execption syndrome register */
+ #define dear 0x3d5 /* data exeption address register */
+ #define evpr 0x3d6 /* exeption vector prefix register */
+ #define tsr 0x3d8 /* timer status register */
+ #define tcr 0x3da /* timer control register */
+ #define pit 0x3db /* programmable interval timer */
+ #define sgr 0x3b9 /* storage guarded reg */
+ #define dcwr 0x3ba /* data cache write-thru reg*/
+ #define sler 0x3bb /* storage little-endian reg */
+ #define cdbcr 0x3d7 /* cache debug cntrl reg */
+ #define icdbdr 0x3d3 /* instr cache dbug data reg*/
+ #define ccr0 0x3b3 /* core configuration register */
+ #define dvc1 0x3b6 /* data value compare register 1 */
+ #define dvc2 0x3b7 /* data value compare register 2 */
+ #define pid 0x3b1 /* process ID */
+ #define su0r 0x3bc /* storage user-defined register 0 */
+ #define zpr 0x3b0 /* zone protection regsiter */
+
+ #define tbl 0x11c /* time base lower - privileged write */
+ #define tbu 0x11d /* time base upper - privileged write */
+
+ #define sprg4r 0x104 /* Special purpose general 4 - read only */
+ #define sprg5r 0x105 /* Special purpose general 5 - read only */
+ #define sprg6r 0x106 /* Special purpose general 6 - read only */
+ #define sprg7r 0x107 /* Special purpose general 7 - read only */
+ #define sprg4w 0x114 /* Special purpose general 4 - write only */
+ #define sprg5w 0x115 /* Special purpose general 5 - write only */
+ #define sprg6w 0x116 /* Special purpose general 6 - write only */
+ #define sprg7w 0x117 /* Special purpose general 7 - write only */
/******************************************************************************
* Special for PPC405GP
@@ -91,29 +91,29 @@
* DMA
******************************************************************************/
#define DMA_DCR_BASE 0x100
-#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
-#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
-#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
-#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
-#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
-#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
-#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
-#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
-#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
-#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
-#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
-#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
-#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
-#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
-#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
-#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
-#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
-#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
-#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
-#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
-#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
-#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
-#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
+#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
+#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
+#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
+#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
+#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
+#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
+#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
+#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
+#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
+#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
+#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
+#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
+#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
+#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
+#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
+#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
+#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
+#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
+#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
+#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
+#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
+#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
+#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
/******************************************************************************
* Universal interrupt controller
@@ -129,49 +129,49 @@
#define UIC_DCR_BASE 0xc0
#define UIC0_DCR_BASE UIC_DCR_BASE
-#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
-#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
-#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
-#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
-#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
-#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
-#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
-#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
-#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
+#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
+#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
+#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
+#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
+#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
+#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
+#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
+#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
+#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
#if defined(CONFIG_405EX)
-#define uic0sr uicsr /* UIC status */
-#define uic0srs uicsrs /* UIC status set */
-#define uic0er uicer /* UIC enable */
-#define uic0cr uiccr /* UIC critical */
-#define uic0pr uicpr /* UIC polarity */
-#define uic0tr uictr /* UIC triggering */
-#define uic0msr uicmsr /* UIC masked status */
-#define uic0vr uicvr /* UIC vector */
+#define uic0sr uicsr /* UIC status */
+#define uic0srs uicsrs /* UIC status set */
+#define uic0er uicer /* UIC enable */
+#define uic0cr uiccr /* UIC critical */
+#define uic0pr uicpr /* UIC polarity */
+#define uic0tr uictr /* UIC triggering */
+#define uic0msr uicmsr /* UIC masked status */
+#define uic0vr uicvr /* UIC vector */
#define uic0vcr uicvcr /* UIC vector configuration*/
#define UIC_DCR_BASE1 0xd0
#define UIC1_DCR_BASE 0xd0
-#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */
-#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */
-#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */
-#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */
-#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */
-#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */
+#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */
+#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */
+#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */
+#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */
+#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */
+#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */
#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */
-#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */
+#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */
#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/
#define UIC_DCR_BASE2 0xe0
#define UIC2_DCR_BASE 0xe0
-#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */
-#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */
-#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */
-#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */
-#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */
-#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */
+#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */
+#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */
+#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */
+#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */
+#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */
+#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */
#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */
-#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */
+#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */
#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/
#endif
@@ -221,145 +221,145 @@
#elif defined(CONFIG_405EX)
/* UIC 0 */
-#define UIC_U0 0x80000000 /* */
-#define UIC_U1 0x40000000 /* */
-#define UIC_IIC0 0x20000000 /* */
-#define UIC_PKA 0x10000000 /* */
-#define UIC_TRNG 0x08000000 /* */
-#define UIC_EBM 0x04000000 /* */
-#define UIC_BGI 0x02000000 /* */
-#define UIC_IIC1 0x01000000 /* */
-#define UIC_SPI 0x00800000 /* */
-#define UIC_EIRQ0 0x00400000 /**/
-#define UIC_MTE 0x00200000 /*MAL Tx EOB */
-#define UIC_MRE 0x00100000 /*MAL Rx EOB */
-#define UIC_DMA0 0x00080000 /* */
-#define UIC_DMA1 0x00040000 /* */
-#define UIC_DMA2 0x00020000 /* */
-#define UIC_DMA3 0x00010000 /* */
-#define UIC_PCIE0AL 0x00008000 /* */
-#define UIC_PCIE0VPD 0x00004000 /* */
-#define UIC_RPCIE0HRST 0x00002000 /* */
-#define UIC_FPCIE0HRST 0x00001000 /* */
-#define UIC_PCIE0TCR 0x00000800 /* */
-#define UIC_PCIEMSI0 0x00000400 /* */
-#define UIC_PCIEMSI1 0x00000200 /* */
-#define UIC_SECURITY 0x00000100 /* */
-#define UIC_ENET 0x00000080 /* */
-#define UIC_ENET1 0x00000040 /* */
-#define UIC_PCIEMSI2 0x00000020 /* */
-#define UIC_EIRQ4 0x00000010 /**/
-#define UICB0_UIC2NCI 0x00000008 /* */
-#define UICB0_UIC2CI 0x00000004 /* */
-#define UICB0_UIC1NCI 0x00000002 /* */
-#define UICB0_UIC1CI 0x00000001 /* */
+#define UIC_U0 0x80000000 /* */
+#define UIC_U1 0x40000000 /* */
+#define UIC_IIC0 0x20000000 /* */
+#define UIC_PKA 0x10000000 /* */
+#define UIC_TRNG 0x08000000 /* */
+#define UIC_EBM 0x04000000 /* */
+#define UIC_BGI 0x02000000 /* */
+#define UIC_IIC1 0x01000000 /* */
+#define UIC_SPI 0x00800000 /* */
+#define UIC_EIRQ0 0x00400000 /**/
+#define UIC_MTE 0x00200000 /*MAL Tx EOB */
+#define UIC_MRE 0x00100000 /*MAL Rx EOB */
+#define UIC_DMA0 0x00080000 /* */
+#define UIC_DMA1 0x00040000 /* */
+#define UIC_DMA2 0x00020000 /* */
+#define UIC_DMA3 0x00010000 /* */
+#define UIC_PCIE0AL 0x00008000 /* */
+#define UIC_PCIE0VPD 0x00004000 /* */
+#define UIC_RPCIE0HRST 0x00002000 /* */
+#define UIC_FPCIE0HRST 0x00001000 /* */
+#define UIC_PCIE0TCR 0x00000800 /* */
+#define UIC_PCIEMSI0 0x00000400 /* */
+#define UIC_PCIEMSI1 0x00000200 /* */
+#define UIC_SECURITY 0x00000100 /* */
+#define UIC_ENET 0x00000080 /* */
+#define UIC_ENET1 0x00000040 /* */
+#define UIC_PCIEMSI2 0x00000020 /* */
+#define UIC_EIRQ4 0x00000010 /**/
+#define UICB0_UIC2NCI 0x00000008 /* */
+#define UICB0_UIC2CI 0x00000004 /* */
+#define UICB0_UIC1NCI 0x00000002 /* */
+#define UICB0_UIC1CI 0x00000001 /* */
#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
UICB0_UIC1CI | UICB0_UIC2NCI)
-#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */
-#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */
+#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */
+#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */
/* UIC 1 */
-#define UIC_MS 0x80000000 /* MAL SERR */
-#define UIC_MTDE 0x40000000 /* MAL TXDE */
-#define UIC_MRDE 0x20000000 /* MAL RXDE */
-#define UIC_PCIE0BMVC0 0x10000000 /* */
-#define UIC_PCIE0DCRERR 0x08000000 /* */
-#define UIC_EBC 0x04000000 /* */
-#define UIC_NDFC 0x02000000 /* */
-#define UIC_PCEI1DCRERR 0x01000000 /* */
-#define UIC_GPTCMPT8 0x00800000 /* */
-#define UIC_GPTCMPT9 0x00400000 /* */
-#define UIC_PCIE1AL 0x00200000 /* */
-#define UIC_PCIE1VPD 0x00100000 /* */
-#define UIC_RPCE1HRST 0x00080000 /* */
-#define UIC_FPCE1HRST 0x00040000 /* */
-#define UIC_PCIE1TCR 0x00020000 /* */
-#define UIC_PCIE1VC0 0x00010000 /* */
-#define UIC_GPTCMPT3 0x00008000 /* */
-#define UIC_GPTCMPT4 0x00004000 /* */
-#define UIC_EIRQ7 0x00002000 /* */
-#define UIC_EIRQ8 0x00001000 /* */
-#define UIC_EIRQ9 0x00000800 /* */
-#define UIC_GPTCMP5 0x00000400 /* */
-#define UIC_GPTCMP6 0x00000200 /* */
-#define UIC_GPTCMP7 0x00000100 /* */
-#define UIC_SROM 0x00000080 /* SERIAL ROM*/
-#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/
-#define UIC_EIRQ2 0x00000020 /* */
-#define UIC_EIRQ5 0x00000010 /* */
-#define UIC_EIRQ6 0x00000008 /* */
-#define UIC_EMAC0WAKE 0x00000004 /* */
-#define UIC_EIRQ1 0x00000002 /* */
-#define UIC_EMAC1WAKE 0x00000001 /* */
-#define UIC_MAL_SERR UIC_MS /* MAL SERR */
-#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */
-#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */
+#define UIC_MS 0x80000000 /* MAL SERR */
+#define UIC_MTDE 0x40000000 /* MAL TXDE */
+#define UIC_MRDE 0x20000000 /* MAL RXDE */
+#define UIC_PCIE0BMVC0 0x10000000 /* */
+#define UIC_PCIE0DCRERR 0x08000000 /* */
+#define UIC_EBC 0x04000000 /* */
+#define UIC_NDFC 0x02000000 /* */
+#define UIC_PCEI1DCRERR 0x01000000 /* */
+#define UIC_GPTCMPT8 0x00800000 /* */
+#define UIC_GPTCMPT9 0x00400000 /* */
+#define UIC_PCIE1AL 0x00200000 /* */
+#define UIC_PCIE1VPD 0x00100000 /* */
+#define UIC_RPCE1HRST 0x00080000 /* */
+#define UIC_FPCE1HRST 0x00040000 /* */
+#define UIC_PCIE1TCR 0x00020000 /* */
+#define UIC_PCIE1VC0 0x00010000 /* */
+#define UIC_GPTCMPT3 0x00008000 /* */
+#define UIC_GPTCMPT4 0x00004000 /* */
+#define UIC_EIRQ7 0x00002000 /* */
+#define UIC_EIRQ8 0x00001000 /* */
+#define UIC_EIRQ9 0x00000800 /* */
+#define UIC_GPTCMP5 0x00000400 /* */
+#define UIC_GPTCMP6 0x00000200 /* */
+#define UIC_GPTCMP7 0x00000100 /* */
+#define UIC_SROM 0x00000080 /* SERIAL ROM*/
+#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/
+#define UIC_EIRQ2 0x00000020 /* */
+#define UIC_EIRQ5 0x00000010 /* */
+#define UIC_EIRQ6 0x00000008 /* */
+#define UIC_EMAC0WAKE 0x00000004 /* */
+#define UIC_EIRQ1 0x00000002 /* */
+#define UIC_EMAC1WAKE 0x00000001 /* */
+#define UIC_MAL_SERR UIC_MS /* MAL SERR */
+#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */
+#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */
/* UIC 2 */
-#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/
-#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/
-#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/
-#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/
-#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/
-#define UIC_DDRMCUE 0x04000000 /* */
-#define UIC_DDRMCCE 0x02000000 /* */
-#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/
-#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/
-#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/
-#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/
-#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/
-#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/
-#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/
-#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/
-#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/
-#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/
-#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/
-#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/
-#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/
-#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/
-#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/
-#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/
-#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/
-#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/
-#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/
-#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/
-#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/
-#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/
-#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/
-#define UIC_USBWAKE 0x00000002 /* USB wakup*/
-#define UIC_USBOTG 0x00000001 /* USB OTG*/
+#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/
+#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/
+#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/
+#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/
+#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/
+#define UIC_DDRMCUE 0x04000000 /* */
+#define UIC_DDRMCCE 0x02000000 /* */
+#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/
+#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/
+#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/
+#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/
+#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/
+#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/
+#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/
+#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/
+#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/
+#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/
+#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/
+#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/
+#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/
+#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/
+#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/
+#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/
+#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/
+#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/
+#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/
+#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/
+#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/
+#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/
+#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/
+#define UIC_USBWAKE 0x00000002 /* USB wakup*/
+#define UIC_USBOTG 0x00000001 /* USB OTG*/
#define UIC_ETH0 UIC_ENET
#define UIC_ETH1 UIC_ENET1
#else /* !defined(CONFIG_405EZ) */
-#define UIC_UART0 0x80000000 /* UART 0 */
-#define UIC_UART1 0x40000000 /* UART 1 */
-#define UIC_IIC 0x20000000 /* IIC */
-#define UIC_EXT_MAST 0x10000000 /* External Master */
-#define UIC_PCI 0x08000000 /* PCI write to command reg */
-#define UIC_DMA0 0x04000000 /* DMA chan. 0 */
-#define UIC_DMA1 0x02000000 /* DMA chan. 1 */
-#define UIC_DMA2 0x01000000 /* DMA chan. 2 */
-#define UIC_DMA3 0x00800000 /* DMA chan. 3 */
-#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
-#define UIC_MAL_SERR 0x00200000 /* MAL SERR */
-#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
-#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
-#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
-#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
-#define UIC_ENET 0x00010000 /* Ethernet0 */
-#define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */
+#define UIC_UART0 0x80000000 /* UART 0 */
+#define UIC_UART1 0x40000000 /* UART 1 */
+#define UIC_IIC 0x20000000 /* IIC */
+#define UIC_EXT_MAST 0x10000000 /* External Master */
+#define UIC_PCI 0x08000000 /* PCI write to command reg */
+#define UIC_DMA0 0x04000000 /* DMA chan. 0 */
+#define UIC_DMA1 0x02000000 /* DMA chan. 1 */
+#define UIC_DMA2 0x01000000 /* DMA chan. 2 */
+#define UIC_DMA3 0x00800000 /* DMA chan. 3 */
+#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
+#define UIC_MAL_SERR 0x00200000 /* MAL SERR */
+#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
+#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
+#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
+#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
+#define UIC_ENET 0x00010000 /* Ethernet0 */
+#define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */
#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */
-#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
-#define UIC_PCI_PM 0x00002000 /* PCI Power Management */
-#define UIC_EXT0 0x00000040 /* External interrupt 0 */
-#define UIC_EXT1 0x00000020 /* External interrupt 1 */
-#define UIC_EXT2 0x00000010 /* External interrupt 2 */
-#define UIC_EXT3 0x00000008 /* External interrupt 3 */
-#define UIC_EXT4 0x00000004 /* External interrupt 4 */
-#define UIC_EXT5 0x00000002 /* External interrupt 5 */
-#define UIC_EXT6 0x00000001 /* External interrupt 6 */
+#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
+#define UIC_PCI_PM 0x00002000 /* PCI Power Management */
+#define UIC_EXT0 0x00000040 /* External interrupt 0 */
+#define UIC_EXT1 0x00000020 /* External interrupt 1 */
+#define UIC_EXT2 0x00000010 /* External interrupt 2 */
+#define UIC_EXT3 0x00000008 /* External interrupt 3 */
+#define UIC_EXT4 0x00000004 /* External interrupt 4 */
+#define UIC_EXT5 0x00000002 /* External interrupt 5 */
+#define UIC_EXT6 0x00000001 /* External interrupt 6 */
#endif /* defined(CONFIG_405EZ) */
/******************************************************************************
@@ -404,15 +404,15 @@
#define kaddr0 0x04 /* address decode definition regsiter 0 */
#define kaddr1 0x05 /* address decode definition regsiter 1 */
#define kconf 0x40 /* decompression core config register */
- #define kid 0x41 /* decompression core ID register */
- #define kver 0x42 /* decompression core version # reg */
- #define kpear 0x50 /* bus error addr reg (PLB addr) */
+ #define kid 0x41 /* decompression core ID register */
+ #define kver 0x42 /* decompression core version # reg */
+ #define kpear 0x50 /* bus error addr reg (PLB addr) */
#define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
#define kesr0 0x52 /* bus error status reg 0 (R/clear) */
- #define kesr0s 0x53 /* bus error status reg 0 (set) */
+ #define kesr0s 0x53 /* bus error status reg 0 (set) */
/* There are 0x400 of the following registers, from krom0 to krom3ff*/
- /* Only the first one is given here. */
- #define krom0 0x400 /* SRAM/ROM read/write */
+ /* Only the first one is given here. */
+ #define krom0 0x400 /* SRAM/ROM read/write */
#endif
/******************************************************************************
@@ -423,23 +423,23 @@
#else
#define POWERMAN_DCR_BASE 0xb8
#endif
-#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
-#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
-#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
+#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
+#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
+#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
/******************************************************************************
* Extrnal Bus Controller
******************************************************************************/
/* values for ebccfga register - indirect addressing of these regs */
- #define pb0cr 0x00 /* periph bank 0 config reg */
- #define pb1cr 0x01 /* periph bank 1 config reg */
- #define pb2cr 0x02 /* periph bank 2 config reg */
- #define pb3cr 0x03 /* periph bank 3 config reg */
- #define pb4cr 0x04 /* periph bank 4 config reg */
+ #define pb0cr 0x00 /* periph bank 0 config reg */
+ #define pb1cr 0x01 /* periph bank 1 config reg */
+ #define pb2cr 0x02 /* periph bank 2 config reg */
+ #define pb3cr 0x03 /* periph bank 3 config reg */
+ #define pb4cr 0x04 /* periph bank 4 config reg */
#ifndef CONFIG_405EP
- #define pb5cr 0x05 /* periph bank 5 config reg */
- #define pb6cr 0x06 /* periph bank 6 config reg */
- #define pb7cr 0x07 /* periph bank 7 config reg */
+ #define pb5cr 0x05 /* periph bank 5 config reg */
+ #define pb6cr 0x06 /* periph bank 6 config reg */
+ #define pb7cr 0x07 /* periph bank 7 config reg */
#endif
#define pb0ap 0x10 /* periph bank 0 access parameters */
#define pb1ap 0x11 /* periph bank 1 access parameters */
@@ -451,10 +451,10 @@
#define pb6ap 0x16 /* periph bank 6 access parameters */
#define pb7ap 0x17 /* periph bank 7 access parameters */
#endif
- #define pbear 0x20 /* periph bus error addr reg */
- #define pbesr0 0x21 /* periph bus error status reg 0 */
- #define pbesr1 0x22 /* periph bus error status reg 1 */
- #define epcr 0x23 /* external periph control reg */
+ #define pbear 0x20 /* periph bus error addr reg */
+ #define pbesr0 0x21 /* periph bus error status reg 0 */
+ #define pbesr1 0x22 /* periph bus error status reg 1 */
+ #define epcr 0x23 /* external periph control reg */
#define EBC0_CFG 0x23 /* external bus configuration reg */
#ifdef CONFIG_405EP
@@ -462,210 +462,210 @@
* Control
******************************************************************************/
#define CNTRL_DCR_BASE 0x0f0
-#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
-#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
-#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
-#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
-#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
-#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
-
-#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
+#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
+#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
+#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
+#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
+#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
+#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
+
+#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
-#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
+#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
-#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
-#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
-#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
-#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
-#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
-#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
+#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
+#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
+#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
+#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
+#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
+#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
/* Bit definitions */
-#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
-#define PLLMR0_CPU_DIV_BYPASS 0x00000000
-#define PLLMR0_CPU_DIV_2 0x00100000
-#define PLLMR0_CPU_DIV_3 0x00200000
-#define PLLMR0_CPU_DIV_4 0x00300000
-
-#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
-#define PLLMR0_CPU_PLB_DIV_1 0x00000000
-#define PLLMR0_CPU_PLB_DIV_2 0x00010000
-#define PLLMR0_CPU_PLB_DIV_3 0x00020000
-#define PLLMR0_CPU_PLB_DIV_4 0x00030000
-
-#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
-#define PLLMR0_OPB_PLB_DIV_1 0x00000000
-#define PLLMR0_OPB_PLB_DIV_2 0x00001000
-#define PLLMR0_OPB_PLB_DIV_3 0x00002000
-#define PLLMR0_OPB_PLB_DIV_4 0x00003000
-
-#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
-#define PLLMR0_EXB_PLB_DIV_2 0x00000000
-#define PLLMR0_EXB_PLB_DIV_3 0x00000100
-#define PLLMR0_EXB_PLB_DIV_4 0x00000200
-#define PLLMR0_EXB_PLB_DIV_5 0x00000300
-
-#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
-#define PLLMR0_MAL_PLB_DIV_1 0x00000000
-#define PLLMR0_MAL_PLB_DIV_2 0x00000010
-#define PLLMR0_MAL_PLB_DIV_3 0x00000020
-#define PLLMR0_MAL_PLB_DIV_4 0x00000030
-
-#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
-#define PLLMR0_PCI_PLB_DIV_1 0x00000000
-#define PLLMR0_PCI_PLB_DIV_2 0x00000001
-#define PLLMR0_PCI_PLB_DIV_3 0x00000002
-#define PLLMR0_PCI_PLB_DIV_4 0x00000003
-
-#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
-#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
-#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
-#define PLLMR1_FBMUL_DIV_16 0x00000000
-#define PLLMR1_FBMUL_DIV_1 0x00100000
-#define PLLMR1_FBMUL_DIV_2 0x00200000
-#define PLLMR1_FBMUL_DIV_3 0x00300000
-#define PLLMR1_FBMUL_DIV_4 0x00400000
-#define PLLMR1_FBMUL_DIV_5 0x00500000
-#define PLLMR1_FBMUL_DIV_6 0x00600000
-#define PLLMR1_FBMUL_DIV_7 0x00700000
-#define PLLMR1_FBMUL_DIV_8 0x00800000
-#define PLLMR1_FBMUL_DIV_9 0x00900000
-#define PLLMR1_FBMUL_DIV_10 0x00A00000
-#define PLLMR1_FBMUL_DIV_11 0x00B00000
-#define PLLMR1_FBMUL_DIV_12 0x00C00000
-#define PLLMR1_FBMUL_DIV_13 0x00D00000
-#define PLLMR1_FBMUL_DIV_14 0x00E00000
-#define PLLMR1_FBMUL_DIV_15 0x00F00000
-
-#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
-#define PLLMR1_FWDVA_DIV_8 0x00000000
-#define PLLMR1_FWDVA_DIV_7 0x00010000
-#define PLLMR1_FWDVA_DIV_6 0x00020000
-#define PLLMR1_FWDVA_DIV_5 0x00030000
-#define PLLMR1_FWDVA_DIV_4 0x00040000
-#define PLLMR1_FWDVA_DIV_3 0x00050000
-#define PLLMR1_FWDVA_DIV_2 0x00060000
-#define PLLMR1_FWDVA_DIV_1 0x00070000
-#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
-#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
+#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
+#define PLLMR0_CPU_DIV_BYPASS 0x00000000
+#define PLLMR0_CPU_DIV_2 0x00100000
+#define PLLMR0_CPU_DIV_3 0x00200000
+#define PLLMR0_CPU_DIV_4 0x00300000
+
+#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
+#define PLLMR0_CPU_PLB_DIV_1 0x00000000
+#define PLLMR0_CPU_PLB_DIV_2 0x00010000
+#define PLLMR0_CPU_PLB_DIV_3 0x00020000
+#define PLLMR0_CPU_PLB_DIV_4 0x00030000
+
+#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
+#define PLLMR0_OPB_PLB_DIV_1 0x00000000
+#define PLLMR0_OPB_PLB_DIV_2 0x00001000
+#define PLLMR0_OPB_PLB_DIV_3 0x00002000
+#define PLLMR0_OPB_PLB_DIV_4 0x00003000
+
+#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
+#define PLLMR0_EXB_PLB_DIV_2 0x00000000
+#define PLLMR0_EXB_PLB_DIV_3 0x00000100
+#define PLLMR0_EXB_PLB_DIV_4 0x00000200
+#define PLLMR0_EXB_PLB_DIV_5 0x00000300
+
+#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
+#define PLLMR0_MAL_PLB_DIV_1 0x00000000
+#define PLLMR0_MAL_PLB_DIV_2 0x00000010
+#define PLLMR0_MAL_PLB_DIV_3 0x00000020
+#define PLLMR0_MAL_PLB_DIV_4 0x00000030
+
+#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
+#define PLLMR0_PCI_PLB_DIV_1 0x00000000
+#define PLLMR0_PCI_PLB_DIV_2 0x00000001
+#define PLLMR0_PCI_PLB_DIV_3 0x00000002
+#define PLLMR0_PCI_PLB_DIV_4 0x00000003
+
+#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
+#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
+#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
+#define PLLMR1_FBMUL_DIV_16 0x00000000
+#define PLLMR1_FBMUL_DIV_1 0x00100000
+#define PLLMR1_FBMUL_DIV_2 0x00200000
+#define PLLMR1_FBMUL_DIV_3 0x00300000
+#define PLLMR1_FBMUL_DIV_4 0x00400000
+#define PLLMR1_FBMUL_DIV_5 0x00500000
+#define PLLMR1_FBMUL_DIV_6 0x00600000
+#define PLLMR1_FBMUL_DIV_7 0x00700000
+#define PLLMR1_FBMUL_DIV_8 0x00800000
+#define PLLMR1_FBMUL_DIV_9 0x00900000
+#define PLLMR1_FBMUL_DIV_10 0x00A00000
+#define PLLMR1_FBMUL_DIV_11 0x00B00000
+#define PLLMR1_FBMUL_DIV_12 0x00C00000
+#define PLLMR1_FBMUL_DIV_13 0x00D00000
+#define PLLMR1_FBMUL_DIV_14 0x00E00000
+#define PLLMR1_FBMUL_DIV_15 0x00F00000
+
+#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
+#define PLLMR1_FWDVA_DIV_8 0x00000000
+#define PLLMR1_FWDVA_DIV_7 0x00010000
+#define PLLMR1_FWDVA_DIV_6 0x00020000
+#define PLLMR1_FWDVA_DIV_5 0x00030000
+#define PLLMR1_FWDVA_DIV_4 0x00040000
+#define PLLMR1_FWDVA_DIV_3 0x00050000
+#define PLLMR1_FWDVA_DIV_2 0x00060000
+#define PLLMR1_FWDVA_DIV_1 0x00070000
+#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
+#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
/* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE 0x80000000
-#define CPC0_EPRCSR_E1NFE 0x40000000
-#define CPC0_EPRCSR_E1RPP 0x00000080
-#define CPC0_EPRCSR_E0RPP 0x00000040
-#define CPC0_EPRCSR_E1ERP 0x00000020
-#define CPC0_EPRCSR_E0ERP 0x00000010
-#define CPC0_EPRCSR_E1PCI 0x00000002
-#define CPC0_EPRCSR_E0PCI 0x00000001
+#define CPC0_EPRCSR_E0NFE 0x80000000
+#define CPC0_EPRCSR_E1NFE 0x40000000
+#define CPC0_EPRCSR_E1RPP 0x00000080
+#define CPC0_EPRCSR_E0RPP 0x00000040
+#define CPC0_EPRCSR_E1ERP 0x00000020
+#define CPC0_EPRCSR_E0ERP 0x00000010
+#define CPC0_EPRCSR_E1PCI 0x00000002
+#define CPC0_EPRCSR_E0PCI 0x00000001
/* Defines for CPC0_PCI Register */
-#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
-#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
-#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
+#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
+#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
+#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
/* Defines for CPC0_BOOR Register */
-#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
+#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE 0x80000000
-#define CPC0_PLLMR1_SSCS 0x80000000
-#define PLL_RESET 0x40000000
-#define CPC0_PLLMR1_PLLR 0x40000000
+#define PLL_ACTIVE 0x80000000
+#define CPC0_PLLMR1_SSCS 0x80000000
+#define PLL_RESET 0x40000000
+#define CPC0_PLLMR1_PLLR 0x40000000
/* Feedback multiplier */
-#define PLL_FBKDIV 0x00F00000
-#define CPC0_PLLMR1_FBDV 0x00F00000
-#define PLL_FBKDIV_16 0x00000000
-#define PLL_FBKDIV_1 0x00100000
-#define PLL_FBKDIV_2 0x00200000
-#define PLL_FBKDIV_3 0x00300000
-#define PLL_FBKDIV_4 0x00400000
-#define PLL_FBKDIV_5 0x00500000
-#define PLL_FBKDIV_6 0x00600000
-#define PLL_FBKDIV_7 0x00700000
-#define PLL_FBKDIV_8 0x00800000
-#define PLL_FBKDIV_9 0x00900000
-#define PLL_FBKDIV_10 0x00A00000
-#define PLL_FBKDIV_11 0x00B00000
-#define PLL_FBKDIV_12 0x00C00000
-#define PLL_FBKDIV_13 0x00D00000
-#define PLL_FBKDIV_14 0x00E00000
-#define PLL_FBKDIV_15 0x00F00000
+#define PLL_FBKDIV 0x00F00000
+#define CPC0_PLLMR1_FBDV 0x00F00000
+#define PLL_FBKDIV_16 0x00000000
+#define PLL_FBKDIV_1 0x00100000
+#define PLL_FBKDIV_2 0x00200000
+#define PLL_FBKDIV_3 0x00300000
+#define PLL_FBKDIV_4 0x00400000
+#define PLL_FBKDIV_5 0x00500000
+#define PLL_FBKDIV_6 0x00600000
+#define PLL_FBKDIV_7 0x00700000
+#define PLL_FBKDIV_8 0x00800000
+#define PLL_FBKDIV_9 0x00900000
+#define PLL_FBKDIV_10 0x00A00000
+#define PLL_FBKDIV_11 0x00B00000
+#define PLL_FBKDIV_12 0x00C00000
+#define PLL_FBKDIV_13 0x00D00000
+#define PLL_FBKDIV_14 0x00E00000
+#define PLL_FBKDIV_15 0x00F00000
/* Forward A divisor */
-#define PLL_FWDDIVA 0x00070000
-#define CPC0_PLLMR1_FWDVA 0x00070000
-#define PLL_FWDDIVA_8 0x00000000
-#define PLL_FWDDIVA_7 0x00010000
-#define PLL_FWDDIVA_6 0x00020000
-#define PLL_FWDDIVA_5 0x00030000
-#define PLL_FWDDIVA_4 0x00040000
-#define PLL_FWDDIVA_3 0x00050000
-#define PLL_FWDDIVA_2 0x00060000
-#define PLL_FWDDIVA_1 0x00070000
+#define PLL_FWDDIVA 0x00070000
+#define CPC0_PLLMR1_FWDVA 0x00070000
+#define PLL_FWDDIVA_8 0x00000000
+#define PLL_FWDDIVA_7 0x00010000
+#define PLL_FWDDIVA_6 0x00020000
+#define PLL_FWDDIVA_5 0x00030000
+#define PLL_FWDDIVA_4 0x00040000
+#define PLL_FWDDIVA_3 0x00050000
+#define PLL_FWDDIVA_2 0x00060000
+#define PLL_FWDDIVA_1 0x00070000
/* Forward B divisor */
-#define PLL_FWDDIVB 0x00007000
-#define CPC0_PLLMR1_FWDVB 0x00007000
-#define PLL_FWDDIVB_8 0x00000000
-#define PLL_FWDDIVB_7 0x00001000
-#define PLL_FWDDIVB_6 0x00002000
-#define PLL_FWDDIVB_5 0x00003000
-#define PLL_FWDDIVB_4 0x00004000
-#define PLL_FWDDIVB_3 0x00005000
-#define PLL_FWDDIVB_2 0x00006000
-#define PLL_FWDDIVB_1 0x00007000
+#define PLL_FWDDIVB 0x00007000
+#define CPC0_PLLMR1_FWDVB 0x00007000
+#define PLL_FWDDIVB_8 0x00000000
+#define PLL_FWDDIVB_7 0x00001000
+#define PLL_FWDDIVB_6 0x00002000
+#define PLL_FWDDIVB_5 0x00003000
+#define PLL_FWDDIVB_4 0x00004000
+#define PLL_FWDDIVB_3 0x00005000
+#define PLL_FWDDIVB_2 0x00006000
+#define PLL_FWDDIVB_1 0x00007000
/* PLL tune bits */
-#define PLL_TUNE_MASK 0x000003FF
-#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
-#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
-#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
-#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
-#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
-#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
-#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
+#define PLL_TUNE_MASK 0x000003FF
+#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
+#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
+#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
+#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
+#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
+#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
+#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
/* Defines for CPC0_PLLMR0 Register fields */
/* CPU divisor */
-#define PLL_CPUDIV 0x00300000
-#define CPC0_PLLMR0_CCDV 0x00300000
-#define PLL_CPUDIV_1 0x00000000
-#define PLL_CPUDIV_2 0x00100000
-#define PLL_CPUDIV_3 0x00200000
-#define PLL_CPUDIV_4 0x00300000
+#define PLL_CPUDIV 0x00300000
+#define CPC0_PLLMR0_CCDV 0x00300000
+#define PLL_CPUDIV_1 0x00000000
+#define PLL_CPUDIV_2 0x00100000
+#define PLL_CPUDIV_3 0x00200000
+#define PLL_CPUDIV_4 0x00300000
/* PLB divisor */
-#define PLL_PLBDIV 0x00030000
-#define CPC0_PLLMR0_CBDV 0x00030000
-#define PLL_PLBDIV_1 0x00000000
-#define PLL_PLBDIV_2 0x00010000
-#define PLL_PLBDIV_3 0x00020000
-#define PLL_PLBDIV_4 0x00030000
+#define PLL_PLBDIV 0x00030000
+#define CPC0_PLLMR0_CBDV 0x00030000
+#define PLL_PLBDIV_1 0x00000000
+#define PLL_PLBDIV_2 0x00010000
+#define PLL_PLBDIV_3 0x00020000
+#define PLL_PLBDIV_4 0x00030000
/* OPB divisor */
-#define PLL_OPBDIV 0x00003000
-#define CPC0_PLLMR0_OPDV 0x00003000
-#define PLL_OPBDIV_1 0x00000000
-#define PLL_OPBDIV_2 0x00001000
-#define PLL_OPBDIV_3 0x00002000
-#define PLL_OPBDIV_4 0x00003000
+#define PLL_OPBDIV 0x00003000
+#define CPC0_PLLMR0_OPDV 0x00003000
+#define PLL_OPBDIV_1 0x00000000
+#define PLL_OPBDIV_2 0x00001000
+#define PLL_OPBDIV_3 0x00002000
+#define PLL_OPBDIV_4 0x00003000
/* EBC divisor */
-#define PLL_EXTBUSDIV 0x00000300
-#define CPC0_PLLMR0_EPDV 0x00000300
-#define PLL_EXTBUSDIV_2 0x00000000
-#define PLL_EXTBUSDIV_3 0x00000100
-#define PLL_EXTBUSDIV_4 0x00000200
-#define PLL_EXTBUSDIV_5 0x00000300
+#define PLL_EXTBUSDIV 0x00000300
+#define CPC0_PLLMR0_EPDV 0x00000300
+#define PLL_EXTBUSDIV_2 0x00000000
+#define PLL_EXTBUSDIV_3 0x00000100
+#define PLL_EXTBUSDIV_4 0x00000200
+#define PLL_EXTBUSDIV_5 0x00000300
/* MAL divisor */
-#define PLL_MALDIV 0x00000030
-#define CPC0_PLLMR0_MPDV 0x00000030
-#define PLL_MALDIV_1 0x00000000
-#define PLL_MALDIV_2 0x00000010
-#define PLL_MALDIV_3 0x00000020
-#define PLL_MALDIV_4 0x00000030
+#define PLL_MALDIV 0x00000030
+#define CPC0_PLLMR0_MPDV 0x00000030
+#define PLL_MALDIV_1 0x00000000
+#define PLL_MALDIV_2 0x00000010
+#define PLL_MALDIV_3 0x00000020
+#define PLL_MALDIV_4 0x00000030
/* PCI divisor */
-#define PLL_PCIDIV 0x00000003
-#define CPC0_PLLMR0_PPFD 0x00000003
-#define PLL_PCIDIV_1 0x00000000
-#define PLL_PCIDIV_2 0x00000001
-#define PLL_PCIDIV_3 0x00000002
-#define PLL_PCIDIV_4 0x00000003
+#define PLL_PCIDIV 0x00000003
+#define CPC0_PLLMR0_PPFD 0x00000003
+#define PLL_PCIDIV_1 0x00000000
+#define PLL_PCIDIV_2 0x00000001
+#define PLL_PCIDIV_3 0x00000002
+#define PLL_PCIDIV_4 0x00000003
/*
*-------------------------------------------------------------------------------
@@ -681,37 +681,37 @@
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
PLL_MALDIV_1 | PLL_PCIDIV_2)
#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
PLL_MALDIV_1 | PLL_PCIDIV_3)
-#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
+#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
PLL_MALDIV_1 | PLL_PCIDIV_1)
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
@@ -758,23 +758,23 @@
* Control
******************************************************************************/
/* CPR Registers */
-#define cprclkupd 0x020 /* CPR_CLKUPD */
-#define cprpllc 0x040 /* CPR_PLLC */
-#define cprplld 0x060 /* CPR_PLLD */
-#define cprprimad 0x080 /* CPR_PRIMAD */
-#define cprperd0 0x0e0 /* CPR_PERD0 */
-#define cprperd1 0x0e1 /* CPR_PERD1 */
-#define cprperc0 0x180 /* CPR_PERC0 */
-#define cprmisc0 0x181 /* CPR_MISC0 */
-#define cprmisc1 0x182 /* CPR_MISC1 */
+#define cprclkupd 0x020 /* CPR_CLKUPD */
+#define cprpllc 0x040 /* CPR_PLLC */
+#define cprplld 0x060 /* CPR_PLLD */
+#define cprprimad 0x080 /* CPR_PRIMAD */
+#define cprperd0 0x0e0 /* CPR_PERD0 */
+#define cprperd1 0x0e1 /* CPR_PERD1 */
+#define cprperc0 0x180 /* CPR_PERC0 */
+#define cprmisc0 0x181 /* CPR_MISC0 */
+#define cprmisc1 0x182 /* CPR_MISC1 */
#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
-#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
+#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
-#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
+#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
@@ -793,77 +793,77 @@
* Control
******************************************************************************/
#define CNTRL_DCR_BASE 0x0b0
-#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
-#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
-#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
-#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
-#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
+#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
+#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
+#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
+#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
+#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
-#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */
-#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */
-#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */
+#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */
+#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */
+#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */
/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */
#define CPC0_ECR (0xaa) /* edge conditioner register */
-#define ecr (0xaa) /* edge conditioner register (405gpr) */
+#define ecr (0xaa) /* edge conditioner register (405gpr) */
/* Bit definitions */
-#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
-#define PLLMR_FWD_DIV_BYPASS 0xE0000000
-#define PLLMR_FWD_DIV_3 0xA0000000
-#define PLLMR_FWD_DIV_4 0x80000000
-#define PLLMR_FWD_DIV_6 0x40000000
-
-#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
-#define PLLMR_FB_DIV_1 0x02000000
-#define PLLMR_FB_DIV_2 0x04000000
-#define PLLMR_FB_DIV_3 0x06000000
-#define PLLMR_FB_DIV_4 0x08000000
-
-#define PLLMR_TUNING_MASK 0x01F80000
-
-#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
-#define PLLMR_CPU_PLB_DIV_1 0x00000000
-#define PLLMR_CPU_PLB_DIV_2 0x00020000
-#define PLLMR_CPU_PLB_DIV_3 0x00040000
-#define PLLMR_CPU_PLB_DIV_4 0x00060000
-
-#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
-#define PLLMR_OPB_PLB_DIV_1 0x00000000
-#define PLLMR_OPB_PLB_DIV_2 0x00008000
-#define PLLMR_OPB_PLB_DIV_3 0x00010000
-#define PLLMR_OPB_PLB_DIV_4 0x00018000
-
-#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
-#define PLLMR_PCI_PLB_DIV_1 0x00000000
-#define PLLMR_PCI_PLB_DIV_2 0x00002000
-#define PLLMR_PCI_PLB_DIV_3 0x00004000
-#define PLLMR_PCI_PLB_DIV_4 0x00006000
-
-#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
-#define PLLMR_EXB_PLB_DIV_2 0x00000000
-#define PLLMR_EXB_PLB_DIV_3 0x00000800
-#define PLLMR_EXB_PLB_DIV_4 0x00001000
-#define PLLMR_EXB_PLB_DIV_5 0x00001800
+#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
+#define PLLMR_FWD_DIV_BYPASS 0xE0000000
+#define PLLMR_FWD_DIV_3 0xA0000000
+#define PLLMR_FWD_DIV_4 0x80000000
+#define PLLMR_FWD_DIV_6 0x40000000
+
+#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
+#define PLLMR_FB_DIV_1 0x02000000
+#define PLLMR_FB_DIV_2 0x04000000
+#define PLLMR_FB_DIV_3 0x06000000
+#define PLLMR_FB_DIV_4 0x08000000
+
+#define PLLMR_TUNING_MASK 0x01F80000
+
+#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
+#define PLLMR_CPU_PLB_DIV_1 0x00000000
+#define PLLMR_CPU_PLB_DIV_2 0x00020000
+#define PLLMR_CPU_PLB_DIV_3 0x00040000
+#define PLLMR_CPU_PLB_DIV_4 0x00060000
+
+#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
+#define PLLMR_OPB_PLB_DIV_1 0x00000000
+#define PLLMR_OPB_PLB_DIV_2 0x00008000
+#define PLLMR_OPB_PLB_DIV_3 0x00010000
+#define PLLMR_OPB_PLB_DIV_4 0x00018000
+
+#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
+#define PLLMR_PCI_PLB_DIV_1 0x00000000
+#define PLLMR_PCI_PLB_DIV_2 0x00002000
+#define PLLMR_PCI_PLB_DIV_3 0x00004000
+#define PLLMR_PCI_PLB_DIV_4 0x00006000
+
+#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
+#define PLLMR_EXB_PLB_DIV_2 0x00000000
+#define PLLMR_EXB_PLB_DIV_3 0x00000800
+#define PLLMR_EXB_PLB_DIV_4 0x00001000
+#define PLLMR_EXB_PLB_DIV_5 0x00001800
/* definitions for PPC405GPr (new mode strapping) */
-#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
-
-#define PSR_PLL_FWD_MASK 0xC0000000
-#define PSR_PLL_FDBACK_MASK 0x30000000
-#define PSR_PLL_TUNING_MASK 0x0E000000
-#define PSR_PLB_CPU_MASK 0x01800000
-#define PSR_OPB_PLB_MASK 0x00600000
-#define PSR_PCI_PLB_MASK 0x00180000
-#define PSR_EB_PLB_MASK 0x00060000
-#define PSR_ROM_WIDTH_MASK 0x00018000
-#define PSR_ROM_LOC 0x00004000
-#define PSR_PCI_ASYNC_EN 0x00001000
+#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
+
+#define PSR_PLL_FWD_MASK 0xC0000000
+#define PSR_PLL_FDBACK_MASK 0x30000000
+#define PSR_PLL_TUNING_MASK 0x0E000000
+#define PSR_PLB_CPU_MASK 0x01800000
+#define PSR_OPB_PLB_MASK 0x00600000
+#define PSR_PCI_PLB_MASK 0x00180000
+#define PSR_EB_PLB_MASK 0x00060000
+#define PSR_ROM_WIDTH_MASK 0x00018000
+#define PSR_ROM_LOC 0x00004000
+#define PSR_PCI_ASYNC_EN 0x00001000
#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
-#define PSR_PCI_ARBIT_EN 0x00000400
-#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
+#define PSR_PCI_ARBIT_EN 0x00000400
+#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
#ifndef CONFIG_IOP480
/*
@@ -994,44 +994,44 @@
#else /* !defined(CONFIG_405EZ) */
#define MAL_DCR_BASE 0x180
-#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
-#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
-#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
-#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
-#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
-#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
+#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
+#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
+#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
+#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
+#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
+#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
-#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
-#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
-#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
+#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
+#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
+#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
-#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
-#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
-#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
-#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
-#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
-#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
-#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
-#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
+#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
+#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
+#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
+#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
+#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
+#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
+#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
+#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
#endif /* defined(CONFIG_405EZ) */
/*-----------------------------------------------------------------------------
| IIC Register Offsets
'----------------------------------------------------------------------------*/
-#define IICMDBUF 0x00
-#define IICSDBUF 0x02
-#define IICLMADR 0x04
-#define IICHMADR 0x05
-#define IICCNTL 0x06
-#define IICMDCNTL 0x07
-#define IICSTS 0x08
-#define IICEXTSTS 0x09
-#define IICLSADR 0x0A
-#define IICHSADR 0x0B
-#define IICCLKDIV 0x0C
-#define IICINTRMSK 0x0D
-#define IICXFRCNT 0x0E
-#define IICXTCNTLSS 0x0F
+#define IICMDBUF 0x00
+#define IICSDBUF 0x02
+#define IICLMADR 0x04
+#define IICHMADR 0x05
+#define IICCNTL 0x06
+#define IICMDCNTL 0x07
+#define IICSTS 0x08
+#define IICEXTSTS 0x09
+#define IICLSADR 0x0A
+#define IICHSADR 0x0B
+#define IICCLKDIV 0x0C
+#define IICINTRMSK 0x0D
+#define IICXFRCNT 0x0E
+#define IICXTCNTLSS 0x0F
#define IICDIRECTCNTL 0x10
/*-----------------------------------------------------------------------------
@@ -1040,40 +1040,40 @@
#define DATA_REG 0x00
#define DL_LSB 0x00
#define DL_MSB 0x01
-#define INT_ENABLE 0x01
-#define FIFO_CONTROL 0x02
-#define LINE_CONTROL 0x03
-#define MODEM_CONTROL 0x04
+#define INT_ENABLE 0x01
+#define FIFO_CONTROL 0x02
+#define LINE_CONTROL 0x03
+#define MODEM_CONTROL 0x04
#define LINE_STATUS 0x05
-#define MODEM_STATUS 0x06
-#define SCRATCH 0x07
+#define MODEM_STATUS 0x06
+#define SCRATCH 0x07
/******************************************************************************
* On Chip Memory
******************************************************************************/
#if defined(CONFIG_405EZ)
#define OCM_DCR_BASE 0x020
-#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
-#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
-#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
-#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
-#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
-#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
-#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
-#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
-#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
-#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
-#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
-#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
-#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
-#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
-#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
+#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
+#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
+#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
+#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
+#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
+#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
+#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
+#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
+#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
+#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
+#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
+#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
+#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
+#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
+#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
#else
#define OCM_DCR_BASE 0x018
-#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
-#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
-#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
-#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
+#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
+#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
+#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
+#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
#endif /* CONFIG_405EZ */
/******************************************************************************
@@ -1121,40 +1121,40 @@
#elif defined(CONFIG_405EX)
#define GPIO_BASE 0xEF600800
-#define GPIO0_OR (GPIO_BASE+0x0)
-#define GPIO0_TCR (GPIO_BASE+0x4)
-#define GPIO0_OSRL (GPIO_BASE+0x8)
-#define GPIO0_OSRH (GPIO_BASE+0xC)
-#define GPIO0_TSRL (GPIO_BASE+0x10)
-#define GPIO0_TSRH (GPIO_BASE+0x14)
-#define GPIO0_ODR (GPIO_BASE+0x18)
-#define GPIO0_IR (GPIO_BASE+0x1C)
-#define GPIO0_RR1 (GPIO_BASE+0x20)
-#define GPIO0_RR2 (GPIO_BASE+0x24)
-#define GPIO0_ISR1L (GPIO_BASE+0x30)
-#define GPIO0_ISR1H (GPIO_BASE+0x34)
-#define GPIO0_ISR2L (GPIO_BASE+0x38)
-#define GPIO0_ISR2H (GPIO_BASE+0x3C)
-#define GPIO0_ISR3L (GPIO_BASE+0x40)
-#define GPIO0_ISR3H (GPIO_BASE+0x44)
+#define GPIO0_OR (GPIO_BASE+0x0)
+#define GPIO0_TCR (GPIO_BASE+0x4)
+#define GPIO0_OSRL (GPIO_BASE+0x8)
+#define GPIO0_OSRH (GPIO_BASE+0xC)
+#define GPIO0_TSRL (GPIO_BASE+0x10)
+#define GPIO0_TSRH (GPIO_BASE+0x14)
+#define GPIO0_ODR (GPIO_BASE+0x18)
+#define GPIO0_IR (GPIO_BASE+0x1C)
+#define GPIO0_RR1 (GPIO_BASE+0x20)
+#define GPIO0_RR2 (GPIO_BASE+0x24)
+#define GPIO0_ISR1L (GPIO_BASE+0x30)
+#define GPIO0_ISR1H (GPIO_BASE+0x34)
+#define GPIO0_ISR2L (GPIO_BASE+0x38)
+#define GPIO0_ISR2H (GPIO_BASE+0x3C)
+#define GPIO0_ISR3L (GPIO_BASE+0x40)
+#define GPIO0_ISR3H (GPIO_BASE+0x44)
#else /* !405EZ */
#define GPIO_BASE 0xEF600700
-#define GPIO0_OR (GPIO_BASE+0x0)
-#define GPIO0_TCR (GPIO_BASE+0x4)
-#define GPIO0_OSRH (GPIO_BASE+0x8)
-#define GPIO0_OSRL (GPIO_BASE+0xC)
-#define GPIO0_TSRH (GPIO_BASE+0x10)
-#define GPIO0_TSRL (GPIO_BASE+0x14)
-#define GPIO0_ODR (GPIO_BASE+0x18)
-#define GPIO0_IR (GPIO_BASE+0x1C)
-#define GPIO0_RR1 (GPIO_BASE+0x20)
-#define GPIO0_RR2 (GPIO_BASE+0x24)
-#define GPIO0_ISR1H (GPIO_BASE+0x30)
-#define GPIO0_ISR1L (GPIO_BASE+0x34)
-#define GPIO0_ISR2H (GPIO_BASE+0x38)
-#define GPIO0_ISR2L (GPIO_BASE+0x3C)
+#define GPIO0_OR (GPIO_BASE+0x0)
+#define GPIO0_TCR (GPIO_BASE+0x4)
+#define GPIO0_OSRH (GPIO_BASE+0x8)
+#define GPIO0_OSRL (GPIO_BASE+0xC)
+#define GPIO0_TSRH (GPIO_BASE+0x10)
+#define GPIO0_TSRL (GPIO_BASE+0x14)
+#define GPIO0_ODR (GPIO_BASE+0x18)
+#define GPIO0_IR (GPIO_BASE+0x1C)
+#define GPIO0_RR1 (GPIO_BASE+0x20)
+#define GPIO0_RR2 (GPIO_BASE+0x24)
+#define GPIO0_ISR1H (GPIO_BASE+0x30)
+#define GPIO0_ISR1L (GPIO_BASE+0x34)
+#define GPIO0_ISR2H (GPIO_BASE+0x38)
+#define GPIO0_ISR2L (GPIO_BASE+0x3C)
#endif /* CONFIG_405EZ */
@@ -1169,376 +1169,376 @@
#define SDRAM_WMIRQ 0x06 /**/
#define SDRAM_PLBOPT 0x08 /**/
#define SDRAM_PUABA 0x09 /**/
-#define SDRAM_MCSTAT 0x1F /* memory controller status */
-#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
-#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
-#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
-#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
-#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
-#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
-#define SDRAM_CODT 0x26 /* on die termination for controller */
-#define SDRAM_VVPR 0x27 /* variable VRef programmming */
-#define SDRAM_OPARS 0x28 /* on chip driver control setup */
-#define SDRAM_OPART 0x29 /* on chip driver control trigger */
-#define SDRAM_RTR 0x30 /* refresh timer */
-#define SDRAM_PMIT 0x34 /* power management idle timer */
-#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
-#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
-#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */
-#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */
-#define SDRAM_INITPLR0 0x50 /* manual initialization control */
-#define SDRAM_INITPLR1 0x51 /* manual initialization control */
-#define SDRAM_INITPLR2 0x52 /* manual initialization control */
-#define SDRAM_INITPLR3 0x53 /* manual initialization control */
-#define SDRAM_INITPLR4 0x54 /* manual initialization control */
-#define SDRAM_INITPLR5 0x55 /* manual initialization control */
-#define SDRAM_INITPLR6 0x56 /* manual initialization control */
-#define SDRAM_INITPLR7 0x57 /* manual initialization control */
-#define SDRAM_INITPLR8 0x58 /* manual initialization control */
-#define SDRAM_INITPLR9 0x59 /* manual initialization control */
-#define SDRAM_INITPLR10 0x5a /* manual initialization control */
-#define SDRAM_INITPLR11 0x5b /* manual initialization control */
-#define SDRAM_INITPLR12 0x5c /* manual initialization control */
-#define SDRAM_INITPLR13 0x5d /* manual initialization control */
-#define SDRAM_INITPLR14 0x5e /* manual initialization control */
-#define SDRAM_INITPLR15 0x5f /* manual initialization control */
-#define SDRAM_RQDC 0x70 /* read DQS delay control */
-#define SDRAM_RFDC 0x74 /* read feedback delay control */
-#define SDRAM_RDCC 0x78 /* read data capture control */
-#define SDRAM_DLCR 0x7A /* delay line calibration */
-#define SDRAM_CLKTR 0x80 /* DDR clock timing */
-#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
-#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
-#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
-#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
-#define SDRAM_MMODE 0x88 /* memory mode */
-#define SDRAM_MEMODE 0x89 /* memory extended mode */
-#define SDRAM_ECCCR 0x98 /* ECC error status */
-#define SDRAM_RID 0xF8 /* revision ID */
+#define SDRAM_MCSTAT 0x1F /* memory controller status */
+#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
+#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
+#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
+#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
+#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
+#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
+#define SDRAM_CODT 0x26 /* on die termination for controller */
+#define SDRAM_VVPR 0x27 /* variable VRef programmming */
+#define SDRAM_OPARS 0x28 /* on chip driver control setup */
+#define SDRAM_OPART 0x29 /* on chip driver control trigger */
+#define SDRAM_RTR 0x30 /* refresh timer */
+#define SDRAM_PMIT 0x34 /* power management idle timer */
+#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
+#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
+#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */
+#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */
+#define SDRAM_INITPLR0 0x50 /* manual initialization control */
+#define SDRAM_INITPLR1 0x51 /* manual initialization control */
+#define SDRAM_INITPLR2 0x52 /* manual initialization control */
+#define SDRAM_INITPLR3 0x53 /* manual initialization control */
+#define SDRAM_INITPLR4 0x54 /* manual initialization control */
+#define SDRAM_INITPLR5 0x55 /* manual initialization control */
+#define SDRAM_INITPLR6 0x56 /* manual initialization control */
+#define SDRAM_INITPLR7 0x57 /* manual initialization control */
+#define SDRAM_INITPLR8 0x58 /* manual initialization control */
+#define SDRAM_INITPLR9 0x59 /* manual initialization control */
+#define SDRAM_INITPLR10 0x5a /* manual initialization control */
+#define SDRAM_INITPLR11 0x5b /* manual initialization control */
+#define SDRAM_INITPLR12 0x5c /* manual initialization control */
+#define SDRAM_INITPLR13 0x5d /* manual initialization control */
+#define SDRAM_INITPLR14 0x5e /* manual initialization control */
+#define SDRAM_INITPLR15 0x5f /* manual initialization control */
+#define SDRAM_RQDC 0x70 /* read DQS delay control */
+#define SDRAM_RFDC 0x74 /* read feedback delay control */
+#define SDRAM_RDCC 0x78 /* read data capture control */
+#define SDRAM_DLCR 0x7A /* delay line calibration */
+#define SDRAM_CLKTR 0x80 /* DDR clock timing */
+#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
+#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
+#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
+#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
+#define SDRAM_MMODE 0x88 /* memory mode */
+#define SDRAM_MEMODE 0x89 /* memory extended mode */
+#define SDRAM_ECCCR 0x98 /* ECC error status */
+#define SDRAM_RID 0xF8 /* revision ID */
/*-----------------------------------------------------------------------------+
| Memory Bank 0-7 configuration
+-----------------------------------------------------------------------------*/
-#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */
-#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */
-#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */
-#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */
-#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */
-#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */
-#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */
-#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */
-#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */
-#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */
-#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */
-#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */
+#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */
+#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */
+#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */
+#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */
+#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */
+#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */
+#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */
+#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */
+#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */
+#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */
+#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */
+#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */
/*-----------------------------------------------------------------------------+
| Memory Controller Status
+-----------------------------------------------------------------------------*/
-#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
-#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
-#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
-#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */
-#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
-#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */
+#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
+#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
+#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
+#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */
+#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
+#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */
/*-----------------------------------------------------------------------------+
| Memory Controller Options 1
+-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */
-#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
-#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
+#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */
+#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
+#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
-#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
-#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
-#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
-#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
-#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
-#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
-#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
-#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
-#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
-#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
-#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
-#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
-#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
+#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
+#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
+#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
+#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
+#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
+#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
+#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
+#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
+#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
+#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
+#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
+#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
+#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
-#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
-#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
-#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
-#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
-#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
-#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
-#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
-#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
-#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
-#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
-#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
-#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
-#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
-#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
+#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
+#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
+#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
+#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
+#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
+#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
+#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
+#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
+#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
+#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
+#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
+#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
+#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
+#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
/*-----------------------------------------------------------------------------+
| Memory Controller Options 2
+-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
-#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
-#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
-#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
-#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
-#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
-#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
-#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
+#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
+#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
+#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
+#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
+#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
+#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
+#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
+#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
-#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
+#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
-#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
+#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
-#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
-#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
-#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
+#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
+#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
+#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
/*-----------------------------------------------------------------------------+
| SDRAM Refresh Timer Register
+-----------------------------------------------------------------------------*/
-#define SDRAM_RTR_RINT_MASK 0xFFF80000
-#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
-#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
+#define SDRAM_RTR_RINT_MASK 0xFFF80000
+#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
+#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
/*-----------------------------------------------------------------------------+
| SDRAM Read DQS Delay Control Register
+-----------------------------------------------------------------------------*/
-#define SDRAM_RQDC_RQDE_MASK 0x80000000
-#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
-#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
-#define SDRAM_RQDC_RQFD_MASK 0x000001FF
-#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
+#define SDRAM_RQDC_RQDE_MASK 0x80000000
+#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
+#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
+#define SDRAM_RQDC_RQFD_MASK 0x000001FF
+#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
-#define SDRAM_RQDC_RQFD_MAX 0xFF
+#define SDRAM_RQDC_RQFD_MAX 0xFF
/*-----------------------------------------------------------------------------+
| SDRAM Read Data Capture Control Register
+-----------------------------------------------------------------------------*/
-#define SDRAM_RDCC_RDSS_MASK 0xC0000000
-#define SDRAM_RDCC_RDSS_T1 0x00000000
-#define SDRAM_RDCC_RDSS_T2 0x40000000
-#define SDRAM_RDCC_RDSS_T3 0x80000000
-#define SDRAM_RDCC_RDSS_T4 0xC0000000
-#define SDRAM_RDCC_RSAE_MASK 0x00000001
-#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
-#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
+#define SDRAM_RDCC_RDSS_MASK 0xC0000000
+#define SDRAM_RDCC_RDSS_T1 0x00000000
+#define SDRAM_RDCC_RDSS_T2 0x40000000
+#define SDRAM_RDCC_RDSS_T3 0x80000000
+#define SDRAM_RDCC_RDSS_T4 0xC0000000
+#define SDRAM_RDCC_RSAE_MASK 0x00000001
+#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
+#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
/*-----------------------------------------------------------------------------+
| SDRAM Read Feedback Delay Control Register
+-----------------------------------------------------------------------------*/
-#define SDRAM_RFDC_ARSE_MASK 0x80000000
-#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
-#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
-#define SDRAM_RFDC_RFOS_MASK 0x007F0000
-#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define SDRAM_RFDC_RFFD_MASK 0x000003FF
-#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+#define SDRAM_RFDC_ARSE_MASK 0x80000000
+#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
+#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
+#define SDRAM_RFDC_RFOS_MASK 0x007F0000
+#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define SDRAM_RFDC_RFFD_MASK 0x000003FF
+#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-#define SDRAM_RFDC_RFFD_MAX 0x4FF
+#define SDRAM_RFDC_RFFD_MAX 0x4FF
/*-----------------------------------------------------------------------------+
| SDRAM Delay Line Calibration Register
+-----------------------------------------------------------------------------*/
-#define SDRAM_DLCR_DCLM_MASK 0x80000000
-#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
-#define SDRAM_DLCR_DCLM_AUTO 0x00000000
-#define SDRAM_DLCR_DLCR_MASK 0x08000000
-#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
-#define SDRAM_DLCR_DLCR_IDLE 0x00000000
-#define SDRAM_DLCR_DLCS_MASK 0x07000000
-#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
-#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
-#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
-#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
-#define SDRAM_DLCR_DLCS_ERROR 0x04000000
-#define SDRAM_DLCR_DLCV_MASK 0x000001FF
-#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
-#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
+#define SDRAM_DLCR_DCLM_MASK 0x80000000
+#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
+#define SDRAM_DLCR_DCLM_AUTO 0x00000000
+#define SDRAM_DLCR_DLCR_MASK 0x08000000
+#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
+#define SDRAM_DLCR_DLCR_IDLE 0x00000000
+#define SDRAM_DLCR_DLCS_MASK 0x07000000
+#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
+#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
+#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
+#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
+#define SDRAM_DLCR_DLCS_ERROR 0x04000000
+#define SDRAM_DLCR_DLCV_MASK 0x000001FF
+#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
+#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
/*-----------------------------------------------------------------------------+
| SDRAM Controller On Die Termination Register
+-----------------------------------------------------------------------------*/
-#define SDRAM_CODT_ODT_ON 0x80000000
-#define SDRAM_CODT_ODT_OFF 0x00000000
-#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
-#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
-#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
-#define SDRAM_CODT_DQS_MASK 0x00000010
-#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
-#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
-#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
-#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
-#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
-#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
-#define SDRAM_CODT_IO_HIZ 0x00000000
-#define SDRAM_CODT_IO_NMODE 0x00000001
+#define SDRAM_CODT_ODT_ON 0x80000000
+#define SDRAM_CODT_ODT_OFF 0x00000000
+#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
+#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
+#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
+#define SDRAM_CODT_DQS_MASK 0x00000010
+#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
+#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
+#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
+#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
+#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
+#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
+#define SDRAM_CODT_IO_HIZ 0x00000000
+#define SDRAM_CODT_IO_NMODE 0x00000001
/*-----------------------------------------------------------------------------+
| SDRAM Mode Register
+-----------------------------------------------------------------------------*/
-#define SDRAM_MMODE_WR_MASK 0x00000E00
-#define SDRAM_MMODE_WR_DDR1 0x00000000
-#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
-#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
-#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
-#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
-#define SDRAM_MMODE_DCL_MASK 0x00000070
-#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
-#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
-#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
-#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
-#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
-#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
-#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
-#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
-#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
+#define SDRAM_MMODE_WR_MASK 0x00000E00
+#define SDRAM_MMODE_WR_DDR1 0x00000000
+#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
+#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
+#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
+#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
+#define SDRAM_MMODE_DCL_MASK 0x00000070
+#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
+#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
+#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
+#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
+#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
+#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
+#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
+#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
+#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
/*-----------------------------------------------------------------------------+
| SDRAM Extended Mode Register
+-----------------------------------------------------------------------------*/
-#define SDRAM_MEMODE_DIC_MASK 0x00000002
-#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
-#define SDRAM_MEMODE_DIC_WEAK 0x00000002
-#define SDRAM_MEMODE_DLL_MASK 0x00000001
-#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
-#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
-#define SDRAM_MEMODE_RTT_MASK 0x00000044
-#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
-#define SDRAM_MEMODE_RTT_75OHM 0x00000004
-#define SDRAM_MEMODE_RTT_150OHM 0x00000040
-#define SDRAM_MEMODE_DQS_MASK 0x00000400
-#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
-#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
+#define SDRAM_MEMODE_DIC_MASK 0x00000002
+#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
+#define SDRAM_MEMODE_DIC_WEAK 0x00000002
+#define SDRAM_MEMODE_DLL_MASK 0x00000001
+#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
+#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
+#define SDRAM_MEMODE_RTT_MASK 0x00000044
+#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
+#define SDRAM_MEMODE_RTT_75OHM 0x00000004
+#define SDRAM_MEMODE_RTT_150OHM 0x00000040
+#define SDRAM_MEMODE_DQS_MASK 0x00000400
+#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
+#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
/*-----------------------------------------------------------------------------+
| SDRAM Clock Timing Register
+-----------------------------------------------------------------------------*/
-#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
-#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
-#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
+#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
+#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
+#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
/*-----------------------------------------------------------------------------+
| SDRAM Write Timing Register
+-----------------------------------------------------------------------------*/
-#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000
-#define SDRAM_WRDTR_LLWP_MASK 0x10000000
-#define SDRAM_WRDTR_LLWP_DIS 0x10000000
-#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
-#define SDRAM_WRDTR_WTR_MASK 0x0E000000
-#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
-#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
-#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
+#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000
+#define SDRAM_WRDTR_LLWP_MASK 0x10000000
+#define SDRAM_WRDTR_LLWP_DIS 0x10000000
+#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
+#define SDRAM_WRDTR_WTR_MASK 0x0E000000
+#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
+#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
+#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
/*-----------------------------------------------------------------------------+
| SDRAM SDTR1 Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR1_LDOF_MASK 0x80000000
-#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
-#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
-#define SDRAM_SDTR1_RTW_MASK 0x00F00000
-#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
-#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
-#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
-#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
-#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
-#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
-#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000
-#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
+#define SDRAM_SDTR1_LDOF_MASK 0x80000000
+#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
+#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
+#define SDRAM_SDTR1_RTW_MASK 0x00F00000
+#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
+#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
+#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
+#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
+#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
+#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
+#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000
+#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
/*-----------------------------------------------------------------------------+
| SDRAM SDTR2 Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR2_RCD_MASK 0xF0000000
-#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
-#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
-#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
-#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
-#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
-#define SDRAM_SDTR2_WTR_MASK 0x0F000000
+#define SDRAM_SDTR2_RCD_MASK 0xF0000000
+#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
+#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
+#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
+#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
+#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
+#define SDRAM_SDTR2_WTR_MASK 0x0F000000
#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
-#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
+#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
-#define SDRAM_SDTR2_WPC_MASK 0x0000F000
+#define SDRAM_SDTR2_WPC_MASK 0x0000F000
#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
-#define SDRAM_SDTR2_RPC_MASK 0x00000F00
+#define SDRAM_SDTR2_RPC_MASK 0x00000F00
#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
-#define SDRAM_SDTR2_RP_MASK 0x000000F0
-#define SDRAM_SDTR2_RP_3_CLK 0x00000030
-#define SDRAM_SDTR2_RP_4_CLK 0x00000040
-#define SDRAM_SDTR2_RP_5_CLK 0x00000050
-#define SDRAM_SDTR2_RP_6_CLK 0x00000060
-#define SDRAM_SDTR2_RP_7_CLK 0x00000070
-#define SDRAM_SDTR2_RRD_MASK 0x0000000F
+#define SDRAM_SDTR2_RP_MASK 0x000000F0
+#define SDRAM_SDTR2_RP_3_CLK 0x00000030
+#define SDRAM_SDTR2_RP_4_CLK 0x00000040
+#define SDRAM_SDTR2_RP_5_CLK 0x00000050
+#define SDRAM_SDTR2_RP_6_CLK 0x00000060
+#define SDRAM_SDTR2_RP_7_CLK 0x00000070
+#define SDRAM_SDTR2_RRD_MASK 0x0000000F
#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
/*-----------------------------------------------------------------------------+
| SDRAM SDTR3 Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR3_RAS_MASK 0x1F000000
+#define SDRAM_SDTR3_RAS_MASK 0x1F000000
#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define SDRAM_SDTR3_RC_MASK 0x001F0000
+#define SDRAM_SDTR3_RC_MASK 0x001F0000
#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
-#define SDRAM_SDTR3_XCS_MASK 0x00001F00
-#define SDRAM_SDTR3_XCS 0x00000D00
-#define SDRAM_SDTR3_RFC_MASK 0x0000003F
+#define SDRAM_SDTR3_XCS_MASK 0x00001F00
+#define SDRAM_SDTR3_XCS 0x00000D00
+#define SDRAM_SDTR3_RFC_MASK 0x0000003F
#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
/*-----------------------------------------------------------------------------+
| Memory Bank 0-1 configuration
+-----------------------------------------------------------------------------*/
-#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
-#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
-#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
-#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
-#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
-#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
-#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
-#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
-#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
-#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
-#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
-#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
-#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
-#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
+#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
+#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
+#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
+#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
+#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
+#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
+#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
+#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
+#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
+#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
+#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
+#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
+#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
+#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
#define sdr_uart0 0x0120 /* UART0 Config */
#define sdr_uart1 0x0121 /* UART1 Config */
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
/* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE 0x80000000
-#define CPC0_EPRCSR_E1NFE 0x40000000
-#define CPC0_EPRCSR_E1RPP 0x00000080
-#define CPC0_EPRCSR_E0RPP 0x00000040
-#define CPC0_EPRCSR_E1ERP 0x00000020
-#define CPC0_EPRCSR_E0ERP 0x00000010
-#define CPC0_EPRCSR_E1PCI 0x00000002
-#define CPC0_EPRCSR_E0PCI 0x00000001
+#define CPC0_EPRCSR_E0NFE 0x80000000
+#define CPC0_EPRCSR_E1NFE 0x40000000
+#define CPC0_EPRCSR_E1RPP 0x00000080
+#define CPC0_EPRCSR_E0RPP 0x00000040
+#define CPC0_EPRCSR_E1ERP 0x00000020
+#define CPC0_EPRCSR_E0ERP 0x00000010
+#define CPC0_EPRCSR_E1PCI 0x00000002
+#define CPC0_EPRCSR_E0PCI 0x00000001
#define cpr0_clkupd 0x020
#define cpr0_pllc 0x040
@@ -1556,7 +1556,7 @@
#define SDR0_SDCS_SDD (0x80000000 >> 31)
/* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0 0x4000
+#define SDR0_CUST0 0x4000
#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
@@ -1582,9 +1582,9 @@
#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
-#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
+#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
+#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
+#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
diff --git a/include/ppc440.h b/include/ppc440.h
index 2f6ed97..54b4553 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -2163,7 +2163,7 @@
#define UIC_UIC3NC 0x00008000 /* UIC3 non-critical interrupt */
#define UIC_UIC3C 0x00004000 /* UIC3 critical interrupt */
#define UIC_EIR1 0x00002000 /* External interrupt 1 */
-#define UIC_TRNGDA 0x00001000 /* TRNG data available */
+#define UIC_TRNGDA 0x00001000 /* TRNG data available */
#define UIC_PKAR1 0x00000800 /* PKA ready (PKA[1]) */
#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 89ff26f..4c97b36 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -318,9 +318,9 @@ typedef struct emac_4xx_hw_st {
#endif
#else
#if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
-#define EMAC_BASE 0xEF600900
+#define EMAC_BASE 0xEF600900
#else
-#define EMAC_BASE 0xEF600800
+#define EMAC_BASE 0xEF600800
#endif
#endif
diff --git a/include/rtc.h b/include/rtc.h
index 2995144..df2d35f 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -35,7 +35,7 @@
* Note that there are small but significant differences to the
* common "struct time":
*
- * struct time: struct rtc_time:
+ * struct time: struct rtc_time:
* tm_mon 0 ... 11 1 ... 12
* tm_year years since 1900 years since 0
*/
diff --git a/include/s_record.h b/include/s_record.h
index 07806d5..29d40b3 100644
--- a/include/s_record.h
+++ b/include/s_record.h
@@ -97,9 +97,9 @@
#define SREC_DATA3 2 /* Data Record with 3 byte address */
#define SREC_DATA4 3 /* Data Record with 4 byte address */
#define SREC_COUNT 5 /* Count Record (previously transmitted) */
-#define SREC_END4 7 /* End Record with 4 byte start address */
-#define SREC_END3 8 /* End Record with 3 byte start address */
-#define SREC_END2 9 /* End Record with 2 byte start address */
+#define SREC_END4 7 /* End Record with 4 byte start address */
+#define SREC_END3 8 /* End Record with 3 byte start address */
+#define SREC_END2 9 /* End Record with 2 byte start address */
#define SREC_EMPTY 10 /* Empty Record without any data */
#define SREC_REC_OK SREC_EMPTY /* last code without error condition */
diff --git a/include/scsi.h b/include/scsi.h
index 2be4d40..aaafc9c 100644
--- a/include/scsi.h
+++ b/include/scsi.h
@@ -32,7 +32,7 @@ typedef struct SCSI_cmd_block{
unsigned char lun; /* Target LUN */
unsigned char cmdlen; /* command len */
unsigned long datalen; /* Total data length */
- unsigned char * pdata; /* pointer to data */
+ unsigned char * pdata; /* pointer to data */
unsigned char msgout[12]; /* Messge out buffer (NOT USED) */
unsigned char msgin[12]; /* Message in buffer */
unsigned char sensecmdlen; /* Sense command len */
@@ -77,7 +77,7 @@ typedef struct SCSI_cmd_block{
#define M_HEAD_TAG (0x21)
#define M_ORDERED_TAG (0x22)
#define M_IGN_RESIDUE (0x23)
-#define M_IDENTIFY (0x80)
+#define M_IDENTIFY (0x80)
#define M_X_MODIFY_DP (0x00)
#define M_X_SYNC_REQ (0x01)
@@ -192,7 +192,7 @@ void scsi_init(void);
/* Hardware errors */
#define SCSI_SEL_TIME_OUT 0x00000101 /* Selection time out */
#define SCSI_HNS_TIME_OUT 0x00000102 /* Handshake */
-#define SCSI_MA_TIME_OUT 0x00000103 /* Phase error */
+#define SCSI_MA_TIME_OUT 0x00000103 /* Phase error */
#define SCSI_UNEXP_DIS 0x00000104 /* unexpected disconnect */
#define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */
diff --git a/include/sed13806.h b/include/sed13806.h
index 216e788..07f4576 100644
--- a/include/sed13806.h
+++ b/include/sed13806.h
@@ -34,7 +34,7 @@
#define DEFAULT_VIDEO_MEMORY_SIZE 0x140000 /* Video Memory Size */
-#define HWCURSORSIZE 1024 /* Size of memory reserved
+#define HWCURSORSIZE 1024 /* Size of memory reserved
for HW cursor*/
/* Offset of chipset registers */
diff --git a/include/spartan2.h b/include/spartan2.h
index bd159e1..7327857 100644
--- a/include/spartan2.h
+++ b/include/spartan2.h
@@ -47,7 +47,7 @@ typedef struct {
Xilinx_busy_fn busy;
Xilinx_abort_fn abort;
Xilinx_post_fn post;
- int relocated;
+ int relocated;
} Xilinx_Spartan2_Slave_Parallel_fns;
/* Slave Serial Implementation function table */
@@ -59,18 +59,18 @@ typedef struct {
Xilinx_done_fn done;
Xilinx_wr_fn wr;
Xilinx_post_fn post;
- int relocated;
+ int relocated;
} Xilinx_Spartan2_Slave_Serial_fns;
/* Device Image Sizes
*********************************************************************/
/* Spartan-II (2.5V) */
-#define XILINX_XC2S15_SIZE 197728/8
-#define XILINX_XC2S30_SIZE 336800/8
-#define XILINX_XC2S50_SIZE 559232/8
-#define XILINX_XC2S100_SIZE 781248/8
-#define XILINX_XC2S150_SIZE 1040128/8
-#define XILINX_XC2S200_SIZE 1335872/8
+#define XILINX_XC2S15_SIZE 197728/8
+#define XILINX_XC2S30_SIZE 336800/8
+#define XILINX_XC2S50_SIZE 559232/8
+#define XILINX_XC2S100_SIZE 781248/8
+#define XILINX_XC2S150_SIZE 1040128/8
+#define XILINX_XC2S200_SIZE 1335872/8
/* Spartan-IIE (1.8V) */
#define XILINX_XC2S50E_SIZE 630048/8
diff --git a/include/spartan3.h b/include/spartan3.h
index c203eeb..9a3a5d4 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -47,7 +47,7 @@ typedef struct {
Xilinx_busy_fn busy;
Xilinx_abort_fn abort;
Xilinx_post_fn post;
- int relocated;
+ int relocated;
} Xilinx_Spartan3_Slave_Parallel_fns;
/* Slave Serial Implementation function table */
@@ -59,20 +59,20 @@ typedef struct {
Xilinx_done_fn done;
Xilinx_wr_fn wr;
Xilinx_post_fn post;
- int relocated;
+ int relocated;
} Xilinx_Spartan3_Slave_Serial_fns;
/* Device Image Sizes
*********************************************************************/
/* Spartan-III (1.2V) */
-#define XILINX_XC3S50_SIZE 439264/8
-#define XILINX_XC3S200_SIZE 1047616/8
-#define XILINX_XC3S400_SIZE 1699136/8
-#define XILINX_XC3S1000_SIZE 3223488/8
-#define XILINX_XC3S1500_SIZE 5214784/8
-#define XILINX_XC3S2000_SIZE 7673024/8
-#define XILINX_XC3S4000_SIZE 11316864/8
-#define XILINX_XC3S5000_SIZE 13271936/8
+#define XILINX_XC3S50_SIZE 439264/8
+#define XILINX_XC3S200_SIZE 1047616/8
+#define XILINX_XC3S400_SIZE 1699136/8
+#define XILINX_XC3S1000_SIZE 3223488/8
+#define XILINX_XC3S1500_SIZE 5214784/8
+#define XILINX_XC3S2000_SIZE 7673024/8
+#define XILINX_XC3S4000_SIZE 11316864/8
+#define XILINX_XC3S5000_SIZE 13271936/8
/* Spartan-3E (v3.4) */
#define XILINX_XC3S100E_SIZE 581344/8
@@ -82,7 +82,7 @@ typedef struct {
#define XILINX_XC3S1600E_SIZE 5969696/8
/* Spartan-IIIE (1.2V) */
-#define XILINX_XC3S1200E_SIZE 3841184/8
+#define XILINX_XC3S1200E_SIZE 3841184/8
/* Descriptor Macros
*********************************************************************/
diff --git a/include/spi.h b/include/spi.h
index 3a55a68..7744c2e 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -31,22 +31,87 @@
#define SPI_MODE_1 (0|SPI_CPHA)
#define SPI_MODE_2 (SPI_CPOL|0)
#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
-#define SPI_CS_HIGH 0x04 /* chipselect active high? */
+#define SPI_CS_HIGH 0x04 /* CS active high */
#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
#define SPI_3WIRE 0x10 /* SI/SO signals shared */
#define SPI_LOOP 0x20 /* loopback mode */
-/*
- * The function call pointer type used to drive the chip select.
- */
-typedef void (*spi_chipsel_type)(int cs);
+/* SPI transfer flags */
+#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
+#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
+/*-----------------------------------------------------------------------
+ * Representation of a SPI slave, i.e. what we're communicating with.
+ *
+ * Drivers are expected to extend this with controller-specific data.
+ *
+ * bus: ID of the bus that the slave is attached to.
+ * cs: ID of the chip select connected to the slave.
+ */
+struct spi_slave {
+ unsigned int bus;
+ unsigned int cs;
+};
/*-----------------------------------------------------------------------
* Initialization, must be called once on start up.
+ *
+ * TODO: I don't think we really need this.
*/
void spi_init(void);
+/*-----------------------------------------------------------------------
+ * Set up communications parameters for a SPI slave.
+ *
+ * This must be called once for each slave. Note that this function
+ * usually doesn't touch any actual hardware, it only initializes the
+ * contents of spi_slave so that the hardware can be easily
+ * initialized later.
+ *
+ * bus: Bus ID of the slave chip.
+ * cs: Chip select ID of the slave chip on the specified bus.
+ * max_hz: Maximum SCK rate in Hz.
+ * mode: Clock polarity, clock phase and other parameters.
+ *
+ * Returns: A spi_slave reference that can be used in subsequent SPI
+ * calls, or NULL if one or more of the parameters are not supported.
+ */
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode);
+
+/*-----------------------------------------------------------------------
+ * Free any memory associated with a SPI slave.
+ *
+ * slave: The SPI slave
+ */
+void spi_free_slave(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * Claim the bus and prepare it for communication with a given slave.
+ *
+ * This must be called before doing any transfers with a SPI slave. It
+ * will enable and initialize any SPI hardware as necessary, and make
+ * sure that the SCK line is in the correct idle state. It is not
+ * allowed to claim the same bus for several slaves without releasing
+ * the bus in between.
+ *
+ * slave: The SPI slave
+ *
+ * Returns: 0 if the bus was claimed successfully, or a negative value
+ * if it wasn't.
+ */
+int spi_claim_bus(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * Release the SPI bus
+ *
+ * This must be called once for every call to spi_claim_bus() after
+ * all transfers have finished. It may disable any SPI hardware as
+ * appropriate.
+ *
+ * slave: The SPI slave
+ */
+void spi_release_bus(struct spi_slave *slave);
/*-----------------------------------------------------------------------
* SPI transfer
@@ -60,28 +125,67 @@ void spi_init(void);
* input data overwrites the output data (since both are buffered by
* temporary variables, this is OK).
*
- * If the chipsel() function is not NULL, it is called with a parameter
- * of '1' (chip select active) at the start of the transfer and again with
- * a parameter of '0' at the end of the transfer.
- *
- * If the chipsel() function _is_ NULL, it the responsibility of the
- * caller to make the appropriate chip select active before calling
- * spi_xfer() and making it inactive after spi_xfer() returns.
- *
* spi_xfer() interface:
- * chipsel: Routine to call to set/clear the chip select:
- * if chipsel is NULL, it is not used.
- * if(cs), make the chip select active (typically '0').
- * if(!cs), make the chip select inactive (typically '1').
- * dout: Pointer to a string of bits to send out. The bits are
- * held in a byte array and are sent MSB first.
- * din: Pointer to a string of bits that will be filled in.
- * bitlen: How many bits to write and read.
+ * slave: The SPI slave which will be sending/receiving the data.
+ * bitlen: How many bits to write and read.
+ * dout: Pointer to a string of bits to send out. The bits are
+ * held in a byte array and are sent MSB first.
+ * din: Pointer to a string of bits that will be filled in.
+ * flags: A bitwise combination of SPI_XFER_* flags.
*
* Returns: 0 on success, not 0 on failure
*/
-int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din);
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags);
+
+/*-----------------------------------------------------------------------
+ * Determine if a SPI chipselect is valid.
+ * This function is provided by the board if the low-level SPI driver
+ * needs it to determine if a given chipselect is actually valid.
+ *
+ * Returns: 1 if bus:cs identifies a valid chip on this board, 0
+ * otherwise.
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs);
+
+/*-----------------------------------------------------------------------
+ * Activate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should activate the chip select
+ * to the device identified by "slave".
+ */
+void spi_cs_activate(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * Deactivate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should deactivate the chip
+ * select to the device identified by "slave".
+ */
+void spi_cs_deactivate(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * Write 8 bits, then read 8 bits.
+ * slave: The SPI slave we're communicating with
+ * byte: Byte to be written
+ *
+ * Returns: The value that was read, or a negative value on error.
+ *
+ * TODO: This function probably shouldn't be inlined.
+ */
+static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
+{
+ unsigned char dout[2];
+ unsigned char din[2];
+ int ret;
+
+ dout[0] = byte;
+ dout[1] = 0;
-int spi_select(unsigned int bus, unsigned int dev, unsigned long mode);
+ ret = spi_xfer(slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
+ return ret < 0 ? ret : din[1];
+}
#endif /* _SPI_H_ */
diff --git a/include/spi_flash.h b/include/spi_flash.h
new file mode 100644
index 0000000..de4f174
--- /dev/null
+++ b/include/spi_flash.h
@@ -0,0 +1,70 @@
+/*
+ * Interface to SPI flash
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SPI_FLASH_H_
+#define _SPI_FLASH_H_
+
+#include <spi.h>
+
+struct spi_flash_region {
+ unsigned int count;
+ unsigned int size;
+};
+
+struct spi_flash {
+ struct spi_slave *spi;
+
+ const char *name;
+
+ u32 size;
+
+ int (*read)(struct spi_flash *flash, u32 offset,
+ size_t len, void *buf);
+ int (*write)(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf);
+ int (*erase)(struct spi_flash *flash, u32 offset,
+ size_t len);
+};
+
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode);
+void spi_flash_free(struct spi_flash *flash);
+
+static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
+ size_t len, void *buf)
+{
+ return flash->read(flash, offset, len, buf);
+}
+
+static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf)
+{
+ return flash->write(flash, offset, len, buf);
+}
+
+static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
+ size_t len)
+{
+ return flash->erase(flash, offset, len);
+}
+
+#endif /* _SPI_FLASH_H_ */
diff --git a/include/sym53c8xx.h b/include/sym53c8xx.h
index 0734fe4..7d3ded5 100644
--- a/include/sym53c8xx.h
+++ b/include/sym53c8xx.h
@@ -33,7 +33,7 @@
#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */
#define SCNTL1 0x01 /* no reset */
- #define ISCON 0x10 /* connected to scsi */
+ #define ISCON 0x10 /* connected to scsi */
#define CRST 0x08 /* force reset */
#define IARB 0x02 /* immediate arbitration */
@@ -128,7 +128,7 @@
#define CTEST3 0x1b
#define FLF 0x08 /* cmd: flush dma fifo */
- #define CLF 0x04 /* cmd: clear dma fifo */
+ #define CLF 0x04 /* cmd: clear dma fifo */
#define FM 0x02 /* mod: fetch pin mode */
#define WRIE 0x01 /* mod: write and invalidate enable */
/* bits 4-7 rsvd for C1010 */
@@ -219,7 +219,7 @@
#define SIDL 0x50 /* Lowlevel: latched from scsi data */
#define STEST4 0x52
- #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
+ #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
#define SMODE_HVD 0x40 /* High Voltage Differential */
#define SMODE_SE 0x80 /* Single Ended */
#define SMODE_LVD 0xc0 /* Low Voltage Differential */
@@ -435,7 +435,7 @@
** LOAD_REG (reg, data) reg = <data>
** << 0 >>
**
-** LOAD_SFBR(data) SFBR = <data>
+** LOAD_SFBR(data) SFBR = <data>
** << 0 >>
**
**-----------------------------------------------------------
diff --git a/include/usbdcore_mpc8xx.h b/include/usbdcore_mpc8xx.h
index 9df62f4..039d245 100644
--- a/include/usbdcore_mpc8xx.h
+++ b/include/usbdcore_mpc8xx.h
@@ -176,7 +176,7 @@ typedef struct endpoint_parameter_block_pointer{
char rfcr; /* Rx Function code */
char tfcr; /* Tx Function code */
ushort mrblr; /* Maximum Receive Buffer Length */
- ushort rbptr; /* RxBD pointer Next Buffer Descriptor */
+ ushort rbptr; /* RxBD pointer Next Buffer Descriptor */
ushort tbptr; /* TxBD pointer Next Buffer Descriptor */
ulong tstate; /* Transmit internal state */
ulong tptr; /* Transmit internal data pointer */
diff --git a/include/video_easylogo.h b/include/video_easylogo.h
index 1e00818..ce93868 100644
--- a/include/video_easylogo.h
+++ b/include/video_easylogo.h
@@ -15,7 +15,7 @@
#endif
typedef struct {
- unsigned char *data;
+ unsigned char *data;
int width;
int height;
int bpp;
diff --git a/include/video_logo.h b/include/video_logo.h
index c12e8f8..a0d2da4 100644
--- a/include/video_logo.h
+++ b/include/video_logo.h
@@ -4,9 +4,9 @@
/* To use this, include it and call: easylogo_plot(screen,&u_boot_logo, width,x,y) */
/* */
/* Where: 'screen' is the pointer to the frame buffer */
-/* 'width' is the screen width */
-/* 'x' is the horizontal position */
-/* 'y' is the vertical position */
+/* 'width' is the screen width */
+/* 'x' is the horizontal position */
+/* 'y' is the vertical position */
/* */
#include <video_easylogo.h>
diff --git a/include/virtex2.h b/include/virtex2.h
index f59227b..d116647 100644
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -50,7 +50,7 @@ typedef struct {
Xilinx_busy_fn busy;
Xilinx_abort_fn abort;
Xilinx_post_fn post;
- int relocated;
+ int relocated;
} Xilinx_Virtex2_Slave_SelectMap_fns;
/* Slave Serial Implementation function table */
@@ -59,7 +59,7 @@ typedef struct {
Xilinx_clk_fn clk;
Xilinx_rdata_fn rdata;
Xilinx_wdata_fn wdata;
- int relocated;
+ int relocated;
} Xilinx_Virtex2_Slave_Serial_fns;
/* Device Image Sizes (in bytes)
@@ -116,5 +116,3 @@ typedef struct {
{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
#endif /* _VIRTEX2_H_ */
-
-/* vim: set ts=4 tw=78: */
diff --git a/include/xilinx.h b/include/xilinx.h
index 95ebe3d..ad33e1f 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -29,55 +29,55 @@
/* Xilinx Model definitions
*********************************************************************/
-#define CFG_SPARTAN2 CFG_FPGA_DEV( 0x1 )
-#define CFG_VIRTEX_E CFG_FPGA_DEV( 0x2 )
+#define CFG_SPARTAN2 CFG_FPGA_DEV( 0x1 )
+#define CFG_VIRTEX_E CFG_FPGA_DEV( 0x2 )
#define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 )
-#define CFG_SPARTAN3 CFG_FPGA_DEV( 0x8 )
-#define CFG_XILINX_SPARTAN2 (CFG_FPGA_XILINX | CFG_SPARTAN2)
-#define CFG_XILINX_VIRTEX_E (CFG_FPGA_XILINX | CFG_VIRTEX_E)
+#define CFG_SPARTAN3 CFG_FPGA_DEV( 0x8 )
+#define CFG_XILINX_SPARTAN2 (CFG_FPGA_XILINX | CFG_SPARTAN2)
+#define CFG_XILINX_VIRTEX_E (CFG_FPGA_XILINX | CFG_VIRTEX_E)
#define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2)
-#define CFG_XILINX_SPARTAN3 (CFG_FPGA_XILINX | CFG_SPARTAN3)
+#define CFG_XILINX_SPARTAN3 (CFG_FPGA_XILINX | CFG_SPARTAN3)
/* XXX - Add new models here */
/* Xilinx Interface definitions
*********************************************************************/
-#define CFG_XILINX_IF_SS CFG_FPGA_IF( 0x1 ) /* slave serial */
+#define CFG_XILINX_IF_SS CFG_FPGA_IF( 0x1 ) /* slave serial */
#define CFG_XILINX_IF_MS CFG_FPGA_IF( 0x2 ) /* master serial */
-#define CFG_XILINX_IF_SP CFG_FPGA_IF( 0x4 ) /* slave parallel */
-#define CFG_XILINX_IF_JTAG CFG_FPGA_IF( 0x8 ) /* jtag */
+#define CFG_XILINX_IF_SP CFG_FPGA_IF( 0x4 ) /* slave parallel */
+#define CFG_XILINX_IF_JTAG CFG_FPGA_IF( 0x8 ) /* jtag */
#define CFG_XILINX_IF_MSM CFG_FPGA_IF( 0x10 ) /* master selectmap */
#define CFG_XILINX_IF_SSM CFG_FPGA_IF( 0x20 ) /* slave selectmap */
/* Xilinx types
*********************************************************************/
-typedef enum { /* typedef Xilinx_iface */
- min_xilinx_iface_type, /* low range check value */
- slave_serial, /* serial data and external clock */
- master_serial, /* serial data w/ internal clock (not used) */
- slave_parallel, /* parallel data w/ external latch */
- jtag_mode, /* jtag/tap serial (not used ) */
- master_selectmap, /* master SelectMap (virtex2) */
- slave_selectmap, /* slave SelectMap (virtex2) */
- max_xilinx_iface_type /* insert all new types before this */
-} Xilinx_iface; /* end, typedef Xilinx_iface */
+typedef enum { /* typedef Xilinx_iface */
+ min_xilinx_iface_type, /* low range check value */
+ slave_serial, /* serial data and external clock */
+ master_serial, /* serial data w/ internal clock (not used) */
+ slave_parallel, /* parallel data w/ external latch */
+ jtag_mode, /* jtag/tap serial (not used ) */
+ master_selectmap, /* master SelectMap (virtex2) */
+ slave_selectmap, /* slave SelectMap (virtex2) */
+ max_xilinx_iface_type /* insert all new types before this */
+} Xilinx_iface; /* end, typedef Xilinx_iface */
-typedef enum { /* typedef Xilinx_Family */
- min_xilinx_type, /* low range check value */
- Xilinx_Spartan2, /* Spartan-II Family */
- Xilinx_VirtexE, /* Virtex-E Family */
- Xilinx_Virtex2, /* Virtex2 Family */
- Xilinx_Spartan3, /* Spartan-III Family */
- max_xilinx_type /* insert all new types before this */
-} Xilinx_Family; /* end, typedef Xilinx_Family */
+typedef enum { /* typedef Xilinx_Family */
+ min_xilinx_type, /* low range check value */
+ Xilinx_Spartan2, /* Spartan-II Family */
+ Xilinx_VirtexE, /* Virtex-E Family */
+ Xilinx_Virtex2, /* Virtex2 Family */
+ Xilinx_Spartan3, /* Spartan-III Family */
+ max_xilinx_type /* insert all new types before this */
+} Xilinx_Family; /* end, typedef Xilinx_Family */
-typedef struct { /* typedef Xilinx_desc */
- Xilinx_Family family; /* part type */
- Xilinx_iface iface; /* interface type */
- size_t size; /* bytes of data part can accept */
- void * iface_fns; /* interface function table */
- int cookie; /* implementation specific cookie */
-} Xilinx_desc; /* end, typedef Xilinx_desc */
+typedef struct { /* typedef Xilinx_desc */
+ Xilinx_Family family; /* part type */
+ Xilinx_iface iface; /* interface type */
+ size_t size; /* bytes of data part can accept */
+ void *iface_fns; /* interface function table */
+ int cookie; /* implementation specific cookie */
+} Xilinx_desc; /* end, typedef Xilinx_desc */
/* Generic Xilinx Functions
*********************************************************************/