diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/ELPPC.h | 337 | ||||
| -rw-r--r-- | include/configs/P3G4.h | 407 | ||||
| -rw-r--r-- | include/configs/ZUMA.h | 370 | ||||
| -rw-r--r-- | include/configs/mpc7448hpc2.h | 386 | ||||
| -rw-r--r-- | include/configs/ppmc7xx.h | 416 |
5 files changed, 0 insertions, 1916 deletions
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h deleted file mode 100644 index debfc36..0000000 --- a/include/configs/ELPPC.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling <fgottschling@eltec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define GTREGREAD(x) 0xffffffff /* needed for debug */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* these hardware addresses are pretty bogus, please change them to - suit your needs */ - -/* first ethernet */ -#define CONFIG_ETHADDR 00:00:5b:ee:de:ad - -#define CONFIG_IPADDR 192.168.0.105 -#define CONFIG_SERVERIP 192.168.0.100 - -#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */ - -#define CONFIG_BAUDRATE 9600 /* console baudrate */ - -#undef CONFIG_WATCHDOG - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp 1000000; " \ - "setenv bootargs root=ramfs console=ttyS00,9600 " \ - "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \ - "${netmask}:${hostname}:eth0:none; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_JFFS2 - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -/* - * choose between COM1 and COM2 as serial console - */ -#define CONFIG_CONS_INDEX 1 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -#define CONFIG_SYS_BOARD_ASM_INIT -#define CONFIG_MISC_INIT_R - -/* - * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP) - */ -#undef CONFIG_SYS_ADDRESS_MAP_A - -#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000 - -#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000 - -#define CONFIG_SYS_ISA_MEM_BUS 0x00000000 -#define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000 -#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000 - -#define CONFIG_SYS_PCI_IO_BUS 0x00800000 -#define CONFIG_SYS_PCI_IO_PHYS 0xfe800000 -#define CONFIG_SYS_PCI_IO_SIZE 0x00400000 - -#define CONFIG_SYS_ISA_IO_BUS 0x00000000 -#define CONFIG_SYS_ISA_IO_PHYS 0xfe000000 -#define CONFIG_SYS_ISA_IO_SIZE 0x00800000 - -/* driver defines FDC,IDE,... */ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS -#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS -#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_USR_LED_BASE 0x78000000 -#define CONFIG_SYS_NVRAM_BASE 0xff000000 -#define CONFIG_SYS_UART_BASE 0xff400000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 - -#define MPC107_EUMB_ADDR 0xfce00000 -#define MPC107_EUMB_PI 0xfce41090 -#define MPC107_EUMB_GCR 0xfce41020 -#define MPC107_EUMB_IACKR 0xfce600a0 -#define MPC107_I2C_ADDR 0xfce03000 - -/* - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Flash mapping/organization on the MPC10x. - */ -#define FLASH_BASE0_PRELIM 0xff800000 -#define FLASH_BASE1_PRELIM 0xffc00000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1" -#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)" -*/ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */ -#undef CONFIG_SYS_MEMTEST - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_SYS_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */ -#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */ -#define CONFIG_ENV_ADDR 0x0 -#define CONFIG_ENV_MAP_ADRS 0xff000000 -#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */ -#define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */ - -/* - * Serial devices - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 24000000 -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_UART_BASE + 8) - -/* - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO -#undef CONFIG_PCI_SCAN_SHOW - -/* - * Optional Video console (graphic: SMI LynxEM) - */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10)) -#define VIDEO_TSTC_FCT serial_stub_tstc -#define VIDEO_GETC_FCT serial_stub_getc - -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_VIDEO_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO - -/* - * Initial BATs - */ -#if 1 - -#define CONFIG_SYS_IBAT0L 0 -#define CONFIG_SYS_IBAT0U 0 -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U - -#define CONFIG_SYS_IBAT1L 0 -#define CONFIG_SYS_IBAT1U 0 -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -#define CONFIG_SYS_IBAT2L 0 -#define CONFIG_SYS_IBAT2U 0 -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -#define CONFIG_SYS_IBAT3L 0 -#define CONFIG_SYS_IBAT3U 0 -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#else - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U - -/* address range for flashes */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* ISA IO space */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* ISA memory space */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#endif - -/* - * Speed settings are board specific - */ -#define CONFIG_SYS_BUS_CLK 100000000 -#define CONFIG_SYS_CPU_CLK 400000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - -#if 1 -#define L2_INIT 0 /* cpu 750 CXe*/ -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_EEPRO100_SROM_WRITE - -#endif /* __CONFIG_H */ diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h deleted file mode 100644 index ac75d3e..0000000 --- a/include/configs/P3G4.h +++ /dev/null @@ -1,407 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -#include "../board/evb64260/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_P3G4 1 /* this is a P3G4 board */ -#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ - -#undef CONFIG_ECC /* enable ECC support */ -/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#define CONFIG_SYS_BOARD_NAME "P3G4" - -#undef CONFIG_SYS_HUSH_PARSER - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=p3g4\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_74xx\0" \ - "bootfile=/tftpboot/p3g4/uImage\0" \ - "kernel_addr=ff000000\0" \ - "ramdisk_addr=ff010000\0" \ - "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \ - "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ - "cp.b 100000 fff00000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_UNIVERSE -#define CONFIG_CMD_BSP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 1 -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CONFIG_SYS_GT_REGS 0xf8000000 -#define CONFIG_SYS_DEV_BASE 0xff000000 - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) - -#define CONFIG_SYS_DEV0_SIZE _8M /* Flash bank */ -#define CONFIG_SYS_DEV1_SIZE 0 /* unused */ -#define CONFIG_SYS_DEV2_SIZE 0 /* unused */ -#define CONFIG_SYS_DEV3_SIZE 0 /* unused */ - -#define CONFIG_SYS_16BIT_BOOT_PAR 0xc01b5e7c -#define CONFIG_SYS_DEV0_PAR CONFIG_SYS_16BIT_BOOT_PAR - -#if 0 /* Wrong?? NTL */ -#define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ - /* DMAAck[1:0] GNT0[1:0] */ -#else -#define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ - /* REQ0[1:0] GNT0[1:0] */ -#endif -#define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ - /* DMAReq[4] DMAAck[4] WDNMI WDE */ -#if 0 /* Wrong?? NTL */ -#define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ - /* DMAAck[1:0] GNT1[1:0] */ -#else -#define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ - /* GPP[22] (RS232IntB or PCI1Int) */ - /* GPP[21] (RS323IntA) */ - /* BClkIn */ - /* REQ1[1:0] GNT1[1:0] */ -#endif - -#if 0 /* Wrong?? NTL */ -# define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ - /* GPP[27:26] Int[1:0] */ -#else -# define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ - /* GPP[29] (PCI1Int) */ - /* BClkOut0 */ - /* GPP[27] (PCI0Int) */ - /* GPP[26] (RtcInt or PCI1Int) */ - /* CPUInt[25:24] */ -#endif - -#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */ - -#if 0 /* Wrong?? - NTL */ -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6 -#else -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ - /* gpp[29] */ - /* gpp[27:26] */ - /* gpp[22:21] */ - -# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 0 - pci use buffer 1,1 - cpu use buffer 0 - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 110110 00 111 0 0 00 1 */ - /* refresh_count=0x200 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ -#endif - -#if 0 -#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE -#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ -#endif -#undef CONFIG_SYS_INIT_CHAN1 -#undef CONFIG_SYS_INIT_CHAN2 -#if 0 -#define SRAM_BASE CONFIG_SYS_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ -#endif - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) - -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 - -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* I2C speed and slave address (for compatability) defaults */ -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* I2C addresses for the two DIMM SPD chips */ -#ifndef CONFIG_EVB64260_750CX -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 -#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ -#define DIMM0_I2C_ADDR 0x54 -#define DIMM1_I2C_ADDR 0x54 -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE BOOT_DEVICE -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */ -#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR 0xFFFE0000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h deleted file mode 100644 index cac6a67..0000000 --- a/include/configs/ZUMA.h +++ /dev/null @@ -1,370 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */ -#define CONFIG_ETHER_PORT_MII /* use two MII ports */ -#define CONFIG_INTEL_LXT97X /* Intel LXT97X phy */ - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -#include "../board/evb64260/local.h" - -#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ -#define CONFIG_ZUMA_V2 1 /* always define this for ZUMA v2 */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -/* #define CONFIG_ZUMA_V2_OLD 1 */ /* backwards compat for old V2 board */ - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ - -#define CONFIG_ECC /* enable ECC support */ - -#define CONFIG_750CX /* we have a 750CX/CXe (override local.h) */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SYS_BOARD_ASM_INIT - -#define CONFIG_SYS_BOARD_NAME "Zuma APv2" - -#define CONFIG_SYS_HUSH_PARSER - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC - -#define CONFIG_MPSC_PORT 0 - - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND \ - "tftpboot && " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:" \ - "$netmask:$hostname:eth0:none panic=5 && bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MII /* enable MII commands */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_DATE - - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" -#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" -*/ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ - -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CONFIG_SYS_GT_REGS 0xf8000000 /* later mapped GT_REGS */ -#define CONFIG_SYS_DEV_BASE 0xf0000000 -#define CONFIG_SYS_DEV0_SIZE _64M /* zuma flash @ 0xf000.0000*/ -#define CONFIG_SYS_DEV1_SIZE _8M /* zuma IDE @ 0xf400.0000 */ -#define CONFIG_SYS_DEV2_SIZE _8M /* unused */ -#define CONFIG_SYS_DEV3_SIZE _8M /* unused */ - -#define CONFIG_SYS_DEV0_PAR 0xc498243c - /* c 4 9 8 2 4 3 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */ - /* 3| 0|.... ..| 1| 4 | 0 | 4 | 8 | 7 | 4 */ - -#define CONFIG_SYS_DEV1_PAR 0xc01b6ac5 - /* c 0 1 b 6 a c 5 */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */ - /* 3| 0|.... ..| 1| 5 | 5 | 5 | 5 | 8 | 5 */ - - -#define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c - -#define CONFIG_SYS_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */ -#define CONFIG_SYS_MPP_CONTROL_1 0x00000000 /* GPP[15:12] : GPP[11:8] */ -#define CONFIG_SYS_MPP_CONTROL_2 0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */ -#define CONFIG_SYS_MPP_CONTROL_3 0x00000000 /* GPP[31:28] (int[3:0]) */ - /* GPP[27:24] (27 is int4, rest are GPP) */ - -#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001101 /* 11=MPSC1/MPSC0 01=ETH, 0=only MII */ -#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xf8000000 /* interrupt inputs: GPP[31:27] */ - -#define CONFIG_SYS_SDRAM_CONFIG 0xe4e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 1 - pci use buffer 0,0 (pci1->0 pci0->0) - cpu use buffer 1 (R*18) - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 111001 00 111 0 0 00 1 */ - - /* refresh count=0x200 - phy interleave disable (by default, - set later by dram config..) - virt interleave enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) - -/*----------------------------------------------------------------------- - * PCI stuff - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 130 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */ -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -#define CONFIG_ENV_ADDR (0xfff80000 - CONFIG_ENV_SECT_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - -#ifdef CONFIG_750CX -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/*------------------------------------------------------------------------ - * Real time clock - */ -#define CONFIG_RTC_DS1302 - - -/*------------------------------------------------------------------------ - * Galileo I2C driver - */ -#define CONFIG_GT_I2C - -#endif /* __CONFIG_H */ diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h deleted file mode 100644 index 0308c52..0000000 --- a/include/configs/mpc7448hpc2.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright (c) 2005 Freescale Semiconductor, Inc. - * - * (C) Copyright 2006 - * Alex Bounine , Tundra Semiconductor Corp. - * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board specific configuration options for Freescale - * MPC7448HPC2 (High-Performance Computing II) (Taiga) board - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Board Configuration Definitions */ -/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */ - -#define CONFIG_MPC7448HPC2 - -#define CONFIG_74xx -#define CONFIG_HIGH_BATS /* High BATs supported */ -#define CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_SYS_TEXT_BASE 0xFF000000 - -#define CONFIG_SYS_BOARD_NAME "MPC7448 HPC II" -#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" - -#define CONFIG_SYS_OCN_CLK 133000000 /* 133 MHz */ -#define CONFIG_SYS_BUS_CLK 133000000 - -#define CONFIG_SYS_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ - -#undef CONFIG_ECC /* disable ECC support */ - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -/* Board-specific Initialization Functions to be called */ -#define CONFIG_SYS_BOARD_ASM_INIT -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_EARLY_INIT_R -#define CONFIG_MISC_INIT_R - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 - -#define CONFIG_ENV_OVERWRITE - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ - -/*#define CONFIG_SYS_HUSH_PARSER */ -#undef CONFIG_SYS_HUSH_PARSER - - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_TSI "tsi108@c0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808" - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * If you have hacked a serial cable onto the second DUART channel, - * change the CONFIG_SYS_DUART port from 1 to 0 below. - * - */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_OCN_CLK * 8 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08) - -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS -/* #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ - -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ - setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ - ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" -#endif - -#undef CONFIG_EXTRA_ENV_SETTINGS - -#define CONFIG_SERIAL "No. 1" - -/* Networking Configuration */ - -#define CONFIG_TSI108_ETH -#define CONFIG_TSI108_ETH_NUM_PORTS 2 - - -#define CONFIG_BOOTFILE "zImage.initrd.elf" -#define CONFIG_LOADADDR 0x400000 - -/*-------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_DATE - - -/*set date in u-boot*/ -#define CONFIG_RTC_M48T35A -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 -#define CONFIG_SYS_NVRAM_SIZE 0x8000 -/* - * Miscellaneous configurable options - */ -#define CONFIG_VERSION_VARIABLE 1 -#define CONFIG_TSI108_I2C -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized - */ -#undef CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000/* larger space - we have SDRAM initialized */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ - -#define CONFIG_SYS_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ -#define CONFIG_SYS_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ - -#define CONFIG_SYS_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ - -#define CONFIG_SYS_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ - -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* Base Address of Flash device */ -#define CONFIG_SYS_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ - -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */ - -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CONFIG_SYS_RESET_ADDRESS 0x3fffff00 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* u-boot code base */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* Peripheral Device section */ - -/* - * Resources on the Tsi108 - */ - -#define CONFIG_SYS_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ -#define CONFIG_SYS_TSI108_CSR_BASE CONFIG_SYS_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ - -#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */ - -#undef DISABLE_PBM - -/* - * PCI stuff - * - */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_TSI108_PCI /* include tsi108 pci support */ - -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ - -/* PCI view of System Memory */ -#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000 - -/* PCI Memory Space */ -#define CONFIG_SYS_PCI_MEM_BUS (CONFIG_SYS_PCI_MEM_PHYS) -#define CONFIG_SYS_PCI_MEM_PHYS (CONFIG_SYS_PCI_MEM32_BASE) /* 0xE0000000 */ -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ - -/* PCI I/O Space */ -#define CONFIG_SYS_PCI_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ - -#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */ - -/* PCI Config Space mapping */ -#define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ -#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */ - -#define CONFIG_SYS_IBAT0U 0xFE0003FF -#define CONFIG_SYS_IBAT0L 0xFE000002 - -#define CONFIG_SYS_IBAT1U 0x00007FFF -#define CONFIG_SYS_IBAT1L 0x00000012 - -#define CONFIG_SYS_IBAT2U 0x80007FFF -#define CONFIG_SYS_IBAT2L 0x80000022 - -#define CONFIG_SYS_IBAT3U 0x00000000 -#define CONFIG_SYS_IBAT3L 0x00000000 - -#define CONFIG_SYS_IBAT4U 0x00000000 -#define CONFIG_SYS_IBAT4L 0x00000000 - -#define CONFIG_SYS_IBAT5U 0x00000000 -#define CONFIG_SYS_IBAT5L 0x00000000 - -#define CONFIG_SYS_IBAT6U 0x00000000 -#define CONFIG_SYS_IBAT6L 0x00000000 - -#define CONFIG_SYS_IBAT7U 0x00000000 -#define CONFIG_SYS_IBAT7L 0x00000000 - -#define CONFIG_SYS_DBAT0U 0xE0003FFF -#define CONFIG_SYS_DBAT0L 0xE000002A - -#define CONFIG_SYS_DBAT1U 0x00007FFF -#define CONFIG_SYS_DBAT1L 0x00000012 - -#define CONFIG_SYS_DBAT2U 0x00000000 -#define CONFIG_SYS_DBAT2L 0x00000000 - -#define CONFIG_SYS_DBAT3U 0xC0000003 -#define CONFIG_SYS_DBAT3L 0xC000002A - -#define CONFIG_SYS_DBAT4U 0x00000000 -#define CONFIG_SYS_DBAT4L 0x00000000 - -#define CONFIG_SYS_DBAT5U 0x00000000 -#define CONFIG_SYS_DBAT5L 0x00000000 - -#define CONFIG_SYS_DBAT6U 0x00000000 -#define CONFIG_SYS_DBAT6L 0x00000000 - -#define CONFIG_SYS_DBAT7U 0x00000000 -#define CONFIG_SYS_DBAT7L 0x00000000 - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x51 -#define DIMM1_I2C_ADDR 0x52 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */ -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ } - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_WRITE_SWAPPED_DATA - -#define PHYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MAX_FLASH_SECT (128) - -#define CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_ADDR 0xFC000000 - -#define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ -#undef CONFIG_SYS_L2 - -#define L2_INIT 0 -#define L2_ENABLE (L2_INIT | L2CR_L2E) -#define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION -#endif /* __CONFIG_H */ diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h deleted file mode 100644 index 18f9a6c..0000000 --- a/include/configs/ppmc7xx.h +++ /dev/null @@ -1,416 +0,0 @@ -/* - * ppmc7xx.h - * --------- - * - * Wind River PPMC 7xx/74xx board configuration file. - * - * By Richard Danter (richard.danter@windriver.com) - * Copyright (C) 2005 Wind River Systems - */ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PPMC7XX - - -/*=================================================================== - * - * User configurable settings - Modify to your preference - * - *=================================================================== - */ - -/* - * Debug - * - * DEBUG - Define this is you want extra debug info - * GTREGREAD - Required to build with debug - * do_bdinfo - Required to build with debug - */ - -#ifdef DEBUG -#define GTREGREAD(x) 0xFFFFFFFF -#define do_bdinfo(a,b,c,d) -#endif - -/* - * CPU type - * - * CONFIG_7xx - We have a 750 or 755 CPU - * CONFIG_74xx - We have a 7400 CPU - * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400) - * CONFIG_BUS_CLK - System bus clock in Hz - */ - -#define CONFIG_7xx -#undef CONFIG_74xx -#undef CONFIG_ALTIVEC -#define CONFIG_BUS_CLK 66000000 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -/* - * Monitor configuration - * - * List of command sets to include in shell - * - * The following command sets have been tested and known to work: - * - * CMD_CACHE - Cache control commands - * CMD_MEMORY - Memory display, change and test commands - * CMD_FLASH - Erase and program flash - * CMD_ENV - Environment commands - * CMD_RUN - Run commands stored in env vars - * CMD_ELF - Load ELF files - * CMD_NET - Networking/file download commands - * CMD_PIN - ICMP Echo Request command - * CMD_PCI - PCI Bus scanning command - */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_RUN -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_PCI - -#undef CONFIG_CMD_KGDB - - -/* - * Serial configuration - * - * CONFIG_CONS_INDEX - Serial console port number (COM1) - * CONFIG_BAUDRATE - Serial speed - */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - - -/* - * PCI config - * - * CONFIG_PCI - Enable PCI bus - * CONFIG_PCI_PNP - Enable Plug & Play support - * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup - */ - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_PNP -#undef CONFIG_PCI_SCAN_SHOW - - -/* - * Network config - * - * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller - * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM - */ - -#define CONFIG_EEPRO100 -#define CONFIG_EEPRO100_SROM_WRITE - - -/* - * Enable extra init functions - * - * CONFIG_MISC_INIT_F - Call pre-relocation init functions - * CONFIG_MISC_INIT_R - Call post relocation init functions - */ - -#undef CONFIG_MISC_INIT_F -#define CONFIG_MISC_INIT_R - - -/* - * Boot config - * - * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot - * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec) - */ - -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ - "bootm" -#define CONFIG_BOOTDELAY 5 - - -/*=================================================================== - * - * Board configuration settings - You should not need to modify these - * - *=================================================================== - */ - - -/* - * Memory map - * - * This board runs in a standard CHRP (Map-B) configuration. - * - * Type Start End Size Width Chip Sel - * ----------- ----------- ----------- ------- ------- -------- - * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0 - * User LED's 0x78000000 RCS3 - * UART 0x7C000000 RCS2 - * Mailbox 0xFF000000 RCS1 - * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0 - * - * Flash sectors are laid out as follows. - * - * Sector Start End Size Comments - * ------- ----------- ----------- ------- ----------- - * 0 0xFFC00000 0xFFC3FFFF 256KB - * 1 0xFFC40000 0xFFC7FFFF 256KB - * 2 0xFFC80000 0xFFCBFFFF 256KB - * 3 0xFFCC0000 0xFFCFFFFF 256KB - * 4 0xFFD00000 0xFFD3FFFF 256KB - * 5 0xFFD40000 0xFFD7FFFF 256KB - * 6 0xFFD80000 0xFFDBFFFF 256KB - * 7 0xFFDC0000 0xFFDFFFFF 256KB - * 8 0xFFE00000 0xFFE3FFFF 256KB - * 9 0xFFE40000 0xFFE7FFFF 256KB - * 10 0xFFE80000 0xFFEBFFFF 256KB - * 11 0xFFEC0000 0xFFEFFFFF 256KB - * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here - * 13 0xFFF40000 0xFFF7FFFF 256KB - * 14 0xFFF80000 0xFFFBFFFF 256KB - * 15 0xFFFC0000 0xFFFDFFFF 128KB - * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here - * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here - * 18 0xFFFF0000 0xFFFFFFFF 64KB - */ - - -/* - * SDRAM config - see memory map details above. - * - * CONFIG_SYS_SDRAM_BASE - Start address of SDRAM, this _must_ be zero! - * CONFIG_SYS_SDRAM_SIZE - Total size of contiguous SDRAM bank(s) - */ - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - - -/* - * Flash config - see memory map details above. - * - * CONFIG_SYS_FLASH_BASE - Start address of flash memory - * CONFIG_SYS_FLASH_SIZE - Total size of contiguous flash mem - * CONFIG_SYS_FLASH_ERASE_TOUT - Erase timeout in ms - * CONFIG_SYS_FLASH_WRITE_TOUT - Write timeout in ms - * CONFIG_SYS_MAX_FLASH_BANKS - Number of banks of flash on board - * CONFIG_SYS_MAX_FLASH_SECT - Number of sectors in a bank - */ - -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_FLASH_SIZE 0x00400000 -#define CONFIG_SYS_FLASH_ERASE_TOUT 250000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 5000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - - -/* - * Monitor config - see memory map details above - * - * CONFIG_SYS_MONITOR_BASE - Base address of monitor code - * CONFIG_SYS_MALLOC_LEN - Size of malloc pool (128KB) - */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x20000 - - -/* - * Command shell settings - * - * CONFIG_SYS_BARGSIZE - Boot Argument buffer size - * CONFIG_SYS_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB) - * CONFIG_SYS_CBSIZE - Console Buffer (input) size - * CONFIG_SYS_LOAD_ADDR - Default load address - * CONFIG_SYS_LONGHELP - Provide more detailed help - * CONFIG_SYS_MAXARGS - Number of args accepted by monitor commands - * CONFIG_SYS_MEMTEST_START - Start address of test to run on RAM - * CONFIG_SYS_MEMTEST_END - End address of RAM test - * CONFIG_SYS_PBSIZE - Print Buffer (output) size - * CONFIG_SYS_PROMPT - Prompt string - */ - -#define CONFIG_SYS_BARGSIZE 1024 -#define CONFIG_SYS_BOOTMAPSZ 0x800000 -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_LOAD_ADDR 0x100000 -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_MEMTEST_START 0x00040000 -#define CONFIG_SYS_MEMTEST_END 0x00040100 -#define CONFIG_SYS_PBSIZE 1024 - - -/* - * Environment config - see memory map details above - * - * CONFIG_ENV_IS_IN_FLASH - The env variables are stored in flash - * CONFIG_ENV_ADDR - Address of the sector containing env vars - * CONFIG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB) - * CONFIG_ENV_SECT_SIZE - Size of sector containing env vars (32KB) - */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFFE0000 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_ADDR_REDUND 0xFFFE8000 -#define CONFIG_ENV_SIZE_REDUND 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x8000 - - -/* - * Initial RAM config - * - * Since the main system RAM is initialised very early, we place the INIT_RAM - * in the main system RAM just above the exception vectors. The contents are - * copied to top of RAM by the init code. - * - * CONFIG_SYS_INIT_RAM_ADDR - Address of Init RAM, above exception vect - * CONFIG_SYS_INIT_RAM_SIZE - Size of Init RAM - * GENERATED_GBL_DATA_SIZE - Ammount of RAM to reserve for global data - * CONFIG_SYS_GBL_DATA_OFFSET - Start of global data, top of stack - */ - -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000) -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -/* - * Initial BAT config - * - * BAT0 - System SDRAM - * BAT1 - LED's and Serial Port - * BAT2 - PCI Memory - * BAT3 - PCI I/O including Flash Memory - */ - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - - -/* - * Cache config - * - * CONFIG_SYS_CACHELINE_SIZE - Size of a cache line (CPU specific) - * CONFIG_SYS_L2 - L2 cache enabled if defined - * L2_INIT - L2 cache init flags - * L2_ENABLE - L2 cache enable flags - */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 -#undef CONFIG_SYS_L2 -#define L2_INIT 0 -#define L2_ENABLE 0 - - -/* - * Clocks config - * - * CONFIG_SYS_BUS_CLK - Bus clock frequency in Hz - * CONFIG_SYS_HZ - Decrementer freq in Hz - */ - -#define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK - - -/* - * Serial port config - * - * CONFIG_SYS_NS16550 - Include the NS16550 driver - * CONFIG_SYS_NS16550_SERIAL - Include the serial (wrapper) driver - * CONFIG_SYS_NS16550_CLK - Frequency of reference clock - * CONFIG_SYS_NS16550_REG_SIZE - 64-bit accesses to 8-bit port - * CONFIG_SYS_NS16550_COM1 - Base address of 1st serial port - */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 3686400 -#define CONFIG_SYS_NS16550_REG_SIZE -8 -#define CONFIG_SYS_NS16550_COM1 0x7C000000 - - -/* - * PCI Config - Address Map B (CHRP) - */ - -#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 -#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000 -#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI_MEM_SIZE 0x7D000000 -#define CONFIG_SYS_ISA_MEM_BUS 0x00000000 -#define CONFIG_SYS_ISA_MEM_PHYS 0xFD000000 -#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000 -#define CONFIG_SYS_PCI_IO_BUS 0x00800000 -#define CONFIG_SYS_PCI_IO_PHYS 0xFE800000 -#define CONFIG_SYS_PCI_IO_SIZE 0x00400000 -#define CONFIG_SYS_ISA_IO_BUS 0x00000000 -#define CONFIG_SYS_ISA_IO_PHYS 0xFE000000 -#define CONFIG_SYS_ISA_IO_SIZE 0x00800000 -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS -#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS -#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS - - -/* - * Extra init functions - * - * CONFIG_SYS_BOARD_ASM_INIT - Call assembly init code - */ - -#define CONFIG_SYS_BOARD_ASM_INIT - -#endif /* __CONFIG_H */ |