diff options
Diffstat (limited to 'include/configs')
27 files changed, 1035 insertions, 121 deletions
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h new file mode 100644 index 0000000..f7020b4 --- /dev/null +++ b/include/configs/ATUM8548.h @@ -0,0 +1,458 @@ +/* + * Copyright 2007 + * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com + * + * Copyright 2004, 2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * atum8548 board configuration file + * + * Please refer to doc/README.atum8548 for more info. + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Debug Options, Disable in production +#define ET_DEBUG 1 +#define CONFIG_PANIC_HANG 1 +#define DEBUG 1 +*/ + +/* CPLD Configuration Options */ +#define MPC85xx_ATUM_CLKOCR 0x80000002 + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 1 /* MPC8548 specific */ + +#define CONFIG_PCI 1 /* enable any pci type devices */ +#define CONFIG_PCI1 1 /* PCI controller 1 */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCI2 1 /* PCI controller 2 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/ +#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#define CONFIG_SYS_CLK_FREQ 33000000 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */ +#define CONFIG_ENABLE_36BIT_PHYS 1 +#undef CFG_DRAM_TEST +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */ +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +#else + /* + * Manually set up DDR parameters + */ + #define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */ + #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */ + #define CFG_DDR_CS0_CONFIG 0x80000102 + #define CFG_DDR_TIMING_0 0x00260802 + #define CFG_DDR_TIMING_1 0x38355322 + #define CFG_DDR_TIMING_2 0x039048c7 + #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ + #define CFG_DDR_MODE 0x00000432 + #define CFG_DDR_INTERVAL 0x05150100 + #define DDR_SDRAM_CFG 0x43000000 +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * based on flash chip S29GL01GP + * One bank, 128M, using the CFI driver. + * Boot from BR0 bank at 0xf800_0000 + * + * BR0: + * Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0 + * Port Size = 16 bits = BRx[19:20] = 10 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0 + * + * OR0: + * Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0 + * Reserved ORx[17:18] = 00 + * CSNT = ORx[20] = 1 + * ACS = half cycle delay = ORx[21:22] = 11 + * SCY = 6 = ORx[24:27] = 0110 + * TRLX = use relaxed timing = ORx[29] = 1 + * EAD = use external address latch delay = OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx + */ + +#define CFG_BOOT_BLOCK 0xf8000000 /* boot TLB block */ +#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 128M */ + +#define CFG_BR0_PRELIM 0xf8001001 + +#define CFG_OR0_PRELIM 0xf8000E65 + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */ + + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_EMPTY_INFO + +/* + * Flash on the LocalBus + */ +#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ + +/* Memory */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ + +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#ifdef CONFIG_PCI2 +#define CFG_PCI2_MEM_BASE 0xC0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2800000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#endif + +#ifdef CONFIG_PCIE1 +#define CFG_PCIE1_MEM_BASE 0xa0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe3000000 +#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#endif + + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC2" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC3" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 +#define TSEC4_PHY_ADDR 3 + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS TSEC_GIGABIT +#define TSEC4_FLAGS TSEC_GIGABIT + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC2" +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD +#endif + +#define CONFIG_IPADDR 10.101.43.142 + +#define CONFIG_HOSTNAME atum +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE /tftpboot/uImage.atum +#define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */ + +#define CONFIG_SERVERIP 10.101.43.10 +#define CONFIG_GATEWAYIP 10.101.45.1 +#define CONFIG_NETMASK 255.255.248.0 + +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" + + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 0321650..1603c9c 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -473,7 +473,7 @@ #define CONFIG_VGA_AS_SINGLE_DEVICE /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ #define CFG_ISA_IO 0xE8000000 -/* see also drivers/videomodes.c */ +/* see also drivers/video/videomodes.c */ #define CFG_DEFAULT_VIDEO_MODE 0x303 #endif diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 35637f9..211f11d 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -294,7 +294,6 @@ #endif /* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system -/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system keep reset. */ #undef CFG_FLASH_CFI #ifdef CFG_FLASH_CFI diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index c9a9c83..7bc4e27 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -192,7 +192,7 @@ #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ -/* drivers/nand/nand.c */ +/* drivers/mtd/nand/nand.c */ #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 35e1d63..afce7fb 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -460,13 +460,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions * diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index e376c11..2868dcb 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -319,13 +319,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index d2e7237..c83382f 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -450,13 +450,6 @@ extern unsigned long get_clock_freq(void); */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions * diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 545a76c..5a96db5 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -444,13 +444,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions * diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 3f382e5..90beb25 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -512,13 +512,6 @@ extern unsigned long get_clock_freq(void); */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions * diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 90ef3d6..76d673c 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -450,13 +450,6 @@ extern unsigned long get_clock_freq(void); */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions * diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index d4e0de0..5f10555 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -490,13 +490,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions * diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 59f490e..2b089d9 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -480,13 +480,6 @@ extern unsigned long get_clock_freq(void); */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions * diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 575bbae..7f485c6 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -573,13 +573,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) - #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions * diff --git a/include/configs/PM854.h b/include/configs/PM854.h index a6a1e73..f0d0399 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -366,13 +366,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions * diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 9a17e3d..ae2645c 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -365,13 +365,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions * diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index c2aa2cc..cf98324 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -496,7 +496,7 @@ #define CONFIG_VGA_AS_SINGLE_DEVICE /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ #define CFG_ISA_IO 0xE8000000 -/* see also drivers/videomodes.c */ +/* see also drivers/video/videomodes.c */ #define CFG_DEFAULT_VIDEO_MODE 0x303 #endif diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index f2c3699..3ca85b8 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -395,13 +395,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) - #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/SX1.h b/include/configs/SX1.h index 05cef87..50ad7dd 100644 --- a/include/configs/SX1.h +++ b/include/configs/SX1.h @@ -181,7 +181,7 @@ * FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 6dbd392..f3b1a53 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -417,13 +417,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 69310d4..e1d1483 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -168,7 +168,7 @@ SIB at Block62 End Block62 address 0x24f80000 /* * Move up the U-Boot & monitor area if more flash is fitted. * If this U-Boot is to be run on Integrators with varying flash sizes, - * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG + * drivers/mtd/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG * register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE * - CFG_MONITOR_BASE is set to indicate that the environment is not * embedded in the boot monitor(s) area diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h index 8623ed3..0be46ea 100644 --- a/include/configs/omap1510inn.h +++ b/include/configs/omap1510inn.h @@ -179,7 +179,7 @@ * FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 8ae8efe..88a3f6e 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -283,7 +283,7 @@ * CFI FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h index 16ce2f6..e3bde4f 100644 --- a/include/configs/omap5912osk.h +++ b/include/configs/omap5912osk.h @@ -174,7 +174,7 @@ * FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ #define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h new file mode 100644 index 0000000..c050a06 --- /dev/null +++ b/include/configs/sbc8548.h @@ -0,0 +1,569 @@ +/* + * Copyright 2007 Wind River Systems <www.windriver.com> + * Copyright 2007 Embedded Specialties, Inc. + * Copyright 2004, 2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * sbc8548 board configuration file + * + * Please refer to doc/README.sbc85xx for more info. + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 1 /* MPC8548 specific */ +#define CONFIG_SBC8548 1 /* SBC8548 board specific */ + +#undef CONFIG_PCI /* enable any pci type devices */ +#undef CONFIG_PCI1 /* PCI controller 1 */ +#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#undef CONFIG_RIO +#undef CONFIG_PCI2 +#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ + + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM + #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * FLASH on the Local Bus + * Two banks, one 8MB the other 64MB, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff80_0000 + * Alternate BR6/OR6 bank at 0xfb80_0000 + * + * BR0: + * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 + * Port Size = 8 bits = BRx[19:20] = 01 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 + * + * BR6: + * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 + * Port Size = 32 bits = BRx[19:20] = 11 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 + * + * OR0: + * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 + * XAM = OR0[17:18] = 11 + * CSNT = OR0[20] = 1 + * ACS = half cycle delay = OR0[21:22] = 11 + * SCY = 6 = OR0[24:27] = 0110 + * TRLX = use relaxed timing = OR0[29] = 1 + * EAD = use external address latch delay = OR0[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 + * + * OR6: + * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 + * XAM = OR6[17:18] = 11 + * CSNT = OR6[20] = 1 + * ACS = half cycle delay = OR6[21:22] = 11 + * SCY = 6 = OR6[24:27] = 0110 + * TRLX = use relaxed timing = OR6[29] = 1 + * EAD = use external address latch delay = OR6[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6 + */ + +#define CFG_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ +#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ + +#define CFG_BR0_PRELIM 0xff800801 +#define CFG_BR6_PRELIM 0xfb801801 + +#define CFG_OR0_PRELIM 0xff806e65 +#define CFG_OR6_PRELIM 0xfc006e65 + +#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +/* CS5 = Local bus peripherals controlled by the EPLD */ + +#define CFG_BR5_PRELIM 0xf8000801 +#define CFG_OR5_PRELIM 0xff006e65 +#define CFG_EPLD_BASE 0xf8000000 +#define CFG_LED_DISP_BASE 0xf8000000 +#define CFG_USER_SWITCHES_BASE 0xf8100000 +#define CFG_BD_REV 0xf8300000 +#define CFG_EEPROM_BASE 0xf8b00000 + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * Base Register 3 and Option Register 3 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR3, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + */ + +#define CFG_BR3_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR3, need: + * 64MB mask for AM, OR3[0:7] = 1111 1100 + * XAM, OR3[17:18] = 11 + * 10 columns OR3[19-21] = 011 + * 12 rows OR3[23-25] = 011 + * EAD set for extra time OR[31] = 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 + */ + +#define CFG_OR3_PRELIM 0xfc006cc0 + +#define CFG_LBC_LCRR 0x00000002 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ + | CFG_LBC_LSDMR_PRETOACT7 \ + | CFG_LBC_LSDMR_ACTTORW7 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC4 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 400000000 /* get_bus_freq(0) */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x3000 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ + +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#ifdef CONFIG_PCI2 +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2800000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#endif + +#ifdef CONFIG_PCIE1 +#define CFG_PCIE1_MEM_BASE 0xa0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe3000000 +#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#endif + +#ifdef CONFIG_RIO +/* + * RapidIO MMU + */ +#define CFG_RIO_MEM_BASE 0xC0000000 +#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif + +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC2" +#define CONFIG_TSEC4 +#define CONFIG_TSEC4_NAME "eTSEC3" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 +#define TSEC4_PHY_ADDR 3 + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC0" +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 02:E0:0C:00:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD +#endif + +#define CONFIG_IPADDR 192.168.0.55 + +#define CONFIG_HOSTNAME sbc8548 +#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx +#define CONFIG_BOOTFILE /uImage +#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ + +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=uRamdisk\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=sbc8548.dtb\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index defc428..b71ba78 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -377,13 +377,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) - #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index c5ae0cd..3baa32c 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -357,13 +357,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index c6e7953..9457bce 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -391,13 +391,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * |