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-rw-r--r--include/configs/tegra-common.h2
-rw-r--r--include/configs/tegra114-common.h3
-rw-r--r--include/configs/tegra20-common.h3
-rw-r--r--include/configs/tegra30-common.h3
4 files changed, 9 insertions, 2 deletions
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index ccd68a1..0aac14e 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -17,8 +17,6 @@
#define CONFIG_TEGRA /* which is a Tegra generic machine */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#include <asm/arch/tegra.h> /* get chip and board defs */
/*
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 44e98e5..c3de9a9 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -18,6 +18,9 @@
#define _TEGRA114_COMMON_H_
#include "tegra-common.h"
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/*
* NS16550 Configuration
*/
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index d5e9ee4..b009a31 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -9,6 +9,9 @@
#define _TEGRA20_COMMON_H_
#include "tegra-common.h"
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
/*
* Errata configuration
*/
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 5ac8816..99acbfd 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -9,6 +9,9 @@
#define _TEGRA30_COMMON_H_
#include "tegra-common.h"
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
/*
* Errata configuration
*/