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-rw-r--r--drivers/block/mvsata_ide.c4
-rw-r--r--drivers/gpio/mxc_gpio.c5
-rw-r--r--drivers/i2c/Makefile1
-rw-r--r--drivers/i2c/mv_i2c.c481
-rw-r--r--drivers/i2c/mv_i2c.h83
-rw-r--r--drivers/i2c/mvtwsi.c2
-rw-r--r--drivers/i2c/mxc_i2c.c7
-rw-r--r--drivers/mtd/Makefile1
-rw-r--r--drivers/mtd/ftsmc020.c51
-rw-r--r--drivers/power/ftpmu010.c41
-rw-r--r--drivers/power/ftpmu010.h146
-rw-r--r--drivers/serial/serial_mxc.c4
-rw-r--r--drivers/spi/mxc_spi.c9
-rw-r--r--drivers/usb/host/ehci-mxc.c2
-rw-r--r--drivers/video/mx3fb.c6
15 files changed, 665 insertions, 178 deletions
diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index 3d6993a..e0e4097 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -1,7 +1,7 @@
/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
- * Written-by: Albert ARIBAUD <albert.aribaud@free.fr>
+ * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* See file CREDITS for list of people who contributed to this
* project.
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 53a0673..1037862 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -21,12 +21,7 @@
* MA 02111-1307 USA
*/
#include <common.h>
-#ifdef CONFIG_MX31
-#include <asm/arch/mx31-regs.h>
-#endif
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
-#endif
#include <asm/io.h>
#include <mxc_gpio.h>
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 052fe36..00a12cc 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -29,6 +29,7 @@ COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
+COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
new file mode 100644
index 0000000..dcbe1ae
--- /dev/null
+++ b/drivers/i2c/mv_i2c.c
@@ -0,0 +1,481 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2003 Pengutronix e.K.
+ * Robert Schwebel <r.schwebel@pengutronix.de>
+ *
+ * (C) Copyright 2011 Marvell Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Back ported to the 8xx platform (from the 8260 platform) by
+ * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_HARD_I2C
+#include <i2c.h>
+#include "mv_i2c.h"
+
+#ifdef DEBUG_I2C
+#define PRINTD(x) printf x
+#else
+#define PRINTD(x)
+#endif
+
+/* All transfers are described by this data structure */
+struct i2c_msg {
+ u8 condition;
+ u8 acknack;
+ u8 direction;
+ u8 data;
+};
+
+struct mv_i2c {
+ u32 ibmr;
+ u32 pad0;
+ u32 idbr;
+ u32 pad1;
+ u32 icr;
+ u32 pad2;
+ u32 isr;
+ u32 pad3;
+ u32 isar;
+};
+
+static struct mv_i2c *base;
+#ifdef CONFIG_I2C_MULTI_BUS
+static u32 i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
+static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
+static unsigned int current_bus;
+
+int i2c_set_bus_num(unsigned int bus)
+{
+ if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) {
+ printf("Bad bus: %d\n", bus);
+ return -1;
+ }
+
+ base = (struct mv_i2c *)i2c_regs[bus];
+ current_bus = bus;
+
+ if (!bus_initialized[current_bus]) {
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ bus_initialized[current_bus] = 1;
+ }
+
+ return 0;
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+ return current_bus;
+}
+#endif
+
+/*
+ * i2c_reset: - reset the host controller
+ *
+ */
+static void i2c_reset(void)
+{
+ writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
+ writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
+ udelay(100);
+ writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
+
+ i2c_clk_enable();
+
+ writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
+ writel(I2C_ICR_INIT, &base->icr); /* set control reg values */
+ writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
+ writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
+ udelay(100);
+}
+
+/*
+ * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
+ * are set and cleared
+ *
+ * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
+ */
+static int i2c_isr_set_cleared(unsigned long set_mask,
+ unsigned long cleared_mask)
+{
+ int timeout = 1000, isr;
+
+ do {
+ isr = readl(&base->isr);
+ udelay(10);
+ if (timeout-- < 0)
+ return 0;
+ } while (((isr & set_mask) != set_mask)
+ || ((isr & cleared_mask) != 0));
+
+ return 1;
+}
+
+/*
+ * i2c_transfer: - Transfer one byte over the i2c bus
+ *
+ * This function can tranfer a byte over the i2c bus in both directions.
+ * It is used by the public API functions.
+ *
+ * @return: 0: transfer successful
+ * -1: message is empty
+ * -2: transmit timeout
+ * -3: ACK missing
+ * -4: receive timeout
+ * -5: illegal parameters
+ * -6: bus is busy and couldn't be aquired
+ */
+int i2c_transfer(struct i2c_msg *msg)
+{
+ int ret;
+
+ if (!msg)
+ goto transfer_error_msg_empty;
+
+ switch (msg->direction) {
+ case I2C_WRITE:
+ /* check if bus is not busy */
+ if (!i2c_isr_set_cleared(0, ISR_IBB))
+ goto transfer_error_bus_busy;
+
+ /* start transmission */
+ writel(readl(&base->icr) & ~ICR_START, &base->icr);
+ writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
+ writel(msg->data, &base->idbr);
+ if (msg->condition == I2C_COND_START)
+ writel(readl(&base->icr) | ICR_START, &base->icr);
+ if (msg->condition == I2C_COND_STOP)
+ writel(readl(&base->icr) | ICR_STOP, &base->icr);
+ if (msg->acknack == I2C_ACKNAK_SENDNAK)
+ writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
+ if (msg->acknack == I2C_ACKNAK_SENDACK)
+ writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
+ writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
+ writel(readl(&base->icr) | ICR_TB, &base->icr);
+
+ /* transmit register empty? */
+ if (!i2c_isr_set_cleared(ISR_ITE, 0))
+ goto transfer_error_transmit_timeout;
+
+ /* clear 'transmit empty' state */
+ writel(readl(&base->isr) | ISR_ITE, &base->isr);
+
+ /* wait for ACK from slave */
+ if (msg->acknack == I2C_ACKNAK_WAITACK)
+ if (!i2c_isr_set_cleared(0, ISR_ACKNAK))
+ goto transfer_error_ack_missing;
+ break;
+
+ case I2C_READ:
+
+ /* check if bus is not busy */
+ if (!i2c_isr_set_cleared(0, ISR_IBB))
+ goto transfer_error_bus_busy;
+
+ /* start receive */
+ writel(readl(&base->icr) & ~ICR_START, &base->icr);
+ writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
+ if (msg->condition == I2C_COND_START)
+ writel(readl(&base->icr) | ICR_START, &base->icr);
+ if (msg->condition == I2C_COND_STOP)
+ writel(readl(&base->icr) | ICR_STOP, &base->icr);
+ if (msg->acknack == I2C_ACKNAK_SENDNAK)
+ writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
+ if (msg->acknack == I2C_ACKNAK_SENDACK)
+ writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
+ writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
+ writel(readl(&base->icr) | ICR_TB, &base->icr);
+
+ /* receive register full? */
+ if (!i2c_isr_set_cleared(ISR_IRF, 0))
+ goto transfer_error_receive_timeout;
+
+ msg->data = readl(&base->idbr);
+
+ /* clear 'receive empty' state */
+ writel(readl(&base->isr) | ISR_IRF, &base->isr);
+ break;
+ default:
+ goto transfer_error_illegal_param;
+ }
+
+ return 0;
+
+transfer_error_msg_empty:
+ PRINTD(("i2c_transfer: error: 'msg' is empty\n"));
+ ret = -1; goto i2c_transfer_finish;
+
+transfer_error_transmit_timeout:
+ PRINTD(("i2c_transfer: error: transmit timeout\n"));
+ ret = -2; goto i2c_transfer_finish;
+
+transfer_error_ack_missing:
+ PRINTD(("i2c_transfer: error: ACK missing\n"));
+ ret = -3; goto i2c_transfer_finish;
+
+transfer_error_receive_timeout:
+ PRINTD(("i2c_transfer: error: receive timeout\n"));
+ ret = -4; goto i2c_transfer_finish;
+
+transfer_error_illegal_param:
+ PRINTD(("i2c_transfer: error: illegal parameters\n"));
+ ret = -5; goto i2c_transfer_finish;
+
+transfer_error_bus_busy:
+ PRINTD(("i2c_transfer: error: bus is busy\n"));
+ ret = -6; goto i2c_transfer_finish;
+
+i2c_transfer_finish:
+ PRINTD(("i2c_transfer: ISR: 0x%04x\n", ISR));
+ i2c_reset();
+ return ret;
+}
+
+/* ------------------------------------------------------------------------ */
+/* API Functions */
+/* ------------------------------------------------------------------------ */
+void i2c_init(int speed, int slaveaddr)
+{
+#ifdef CONFIG_I2C_MULTI_BUS
+ base = (struct mv_i2c *)i2c_regs[current_bus];
+#else
+ base = (struct mv_i2c *)CONFIG_MV_I2C_REG;
+#endif
+
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+ u32 icr;
+ /*
+ * call board specific i2c bus reset routine before accessing the
+ * environment, which might be in a chip on that bus. For details
+ * about this problem see doc/I2C_Edge_Conditions.
+ *
+ * disable I2C controller first, otherwhise it thinks we want to
+ * talk to the slave port...
+ */
+ icr = readl(&base->icr);
+ writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr);
+
+ i2c_init_board();
+
+ writel(icr, &base->icr);
+#endif
+}
+
+/*
+ * i2c_probe: - Test if a chip answers for a given i2c address
+ *
+ * @chip: address of the chip which is searched for
+ * @return: 0 if a chip was found, -1 otherwhise
+ */
+int i2c_probe(uchar chip)
+{
+ struct i2c_msg msg;
+
+ i2c_reset();
+
+ msg.condition = I2C_COND_START;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = (chip << 1) + 1;
+ if (i2c_transfer(&msg))
+ return -1;
+
+ msg.condition = I2C_COND_STOP;
+ msg.acknack = I2C_ACKNAK_SENDNAK;
+ msg.direction = I2C_READ;
+ msg.data = 0x00;
+ if (i2c_transfer(&msg))
+ return -1;
+
+ return 0;
+}
+
+/*
+ * i2c_read: - Read multiple bytes from an i2c device
+ *
+ * The higher level routines take into account that this function is only
+ * called with len < page length of the device (see configuration file)
+ *
+ * @chip: address of the chip which is to be read
+ * @addr: i2c data address within the chip
+ * @alen: length of the i2c data address (1..2 bytes)
+ * @buffer: where to write the data
+ * @len: how much byte do we want to read
+ * @return: 0 in case of success
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ struct i2c_msg msg;
+ u8 addr_bytes[3]; /* lowest...highest byte of data address */
+
+ PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
+ "len=0x%02x)\n", chip, addr, alen, len));
+
+ i2c_reset();
+
+ /* dummy chip address write */
+ PRINTD(("i2c_read: dummy chip address write\n"));
+ msg.condition = I2C_COND_START;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = (chip << 1);
+ msg.data &= 0xFE;
+ if (i2c_transfer(&msg))
+ return -1;
+
+ /*
+ * send memory address bytes;
+ * alen defines how much bytes we have to send.
+ */
+ /*addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); */
+ addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
+ addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
+ addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
+
+ while (--alen >= 0) {
+ PRINTD(("i2c_read: send memory word address byte %1d\n", alen));
+ msg.condition = I2C_COND_NORMAL;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = addr_bytes[alen];
+ if (i2c_transfer(&msg))
+ return -1;
+ }
+
+ /* start read sequence */
+ PRINTD(("i2c_read: start read sequence\n"));
+ msg.condition = I2C_COND_START;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = (chip << 1);
+ msg.data |= 0x01;
+ if (i2c_transfer(&msg))
+ return -1;
+
+ /* read bytes; send NACK at last byte */
+ while (len--) {
+ if (len == 0) {
+ msg.condition = I2C_COND_STOP;
+ msg.acknack = I2C_ACKNAK_SENDNAK;
+ } else {
+ msg.condition = I2C_COND_NORMAL;
+ msg.acknack = I2C_ACKNAK_SENDACK;
+ }
+
+ msg.direction = I2C_READ;
+ msg.data = 0x00;
+ if (i2c_transfer(&msg))
+ return -1;
+
+ *buffer = msg.data;
+ PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",
+ (unsigned int)buffer, *buffer));
+ buffer++;
+ }
+
+ i2c_reset();
+
+ return 0;
+}
+
+/*
+ * i2c_write: - Write multiple bytes to an i2c device
+ *
+ * The higher level routines take into account that this function is only
+ * called with len < page length of the device (see configuration file)
+ *
+ * @chip: address of the chip which is to be written
+ * @addr: i2c data address within the chip
+ * @alen: length of the i2c data address (1..2 bytes)
+ * @buffer: where to find the data to be written
+ * @len: how much byte do we want to read
+ * @return: 0 in case of success
+ */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ struct i2c_msg msg;
+ u8 addr_bytes[3]; /* lowest...highest byte of data address */
+
+ PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
+ "len=0x%02x)\n", chip, addr, alen, len));
+
+ i2c_reset();
+
+ /* chip address write */
+ PRINTD(("i2c_write: chip address write\n"));
+ msg.condition = I2C_COND_START;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = (chip << 1);
+ msg.data &= 0xFE;
+ if (i2c_transfer(&msg))
+ return -1;
+
+ /*
+ * send memory address bytes;
+ * alen defines how much bytes we have to send.
+ */
+ addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
+ addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
+ addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
+
+ while (--alen >= 0) {
+ PRINTD(("i2c_write: send memory word address\n"));
+ msg.condition = I2C_COND_NORMAL;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = addr_bytes[alen];
+ if (i2c_transfer(&msg))
+ return -1;
+ }
+
+ /* write bytes; send NACK at last byte */
+ while (len--) {
+ PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",
+ (unsigned int)buffer, *buffer));
+
+ if (len == 0)
+ msg.condition = I2C_COND_STOP;
+ else
+ msg.condition = I2C_COND_NORMAL;
+
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = *(buffer++);
+
+ if (i2c_transfer(&msg))
+ return -1;
+ }
+
+ i2c_reset();
+
+ return 0;
+}
+#endif /* CONFIG_HARD_I2C */
diff --git a/drivers/i2c/mv_i2c.h b/drivers/i2c/mv_i2c.h
new file mode 100644
index 0000000..41af0d9
--- /dev/null
+++ b/drivers/i2c/mv_i2c.h
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Inc, <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MV_I2C_H_
+#define _MV_I2C_H_
+extern void i2c_clk_enable(void);
+
+/* Shall the current transfer have a start/stop condition? */
+#define I2C_COND_NORMAL 0
+#define I2C_COND_START 1
+#define I2C_COND_STOP 2
+
+/* Shall the current transfer be ack/nacked or being waited for it? */
+#define I2C_ACKNAK_WAITACK 1
+#define I2C_ACKNAK_SENDACK 2
+#define I2C_ACKNAK_SENDNAK 4
+
+/* Specify who shall transfer the data (master or slave) */
+#define I2C_READ 0
+#define I2C_WRITE 1
+
+#if (CONFIG_SYS_I2C_SPEED == 400000)
+#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \
+ | ICR_SCLE)
+#else
+#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+#endif
+
+#define I2C_ISR_INIT 0x7FF
+/* ----- Control register bits ---------------------------------------- */
+
+#define ICR_START 0x1 /* start bit */
+#define ICR_STOP 0x2 /* stop bit */
+#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
+#define ICR_TB 0x8 /* transfer byte bit */
+#define ICR_MA 0x10 /* master abort */
+#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */
+#define ICR_IUE 0x40 /* unit enable */
+#define ICR_GCD 0x80 /* general call disable */
+#define ICR_ITEIE 0x100 /* enable tx interrupts */
+#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */
+#define ICR_BEIE 0x400 /* enable bus error ints */
+#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
+#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
+#define ICR_SADIE 0x2000 /* slave address detected int enable */
+#define ICR_UR 0x4000 /* unit reset */
+#define ICR_FM 0x8000 /* Fast Mode */
+
+/* ----- Status register bits ----------------------------------------- */
+
+#define ISR_RWM 0x1 /* read/write mode */
+#define ISR_ACKNAK 0x2 /* ack/nak status */
+#define ISR_UB 0x4 /* unit busy */
+#define ISR_IBB 0x8 /* bus busy */
+#define ISR_SSD 0x10 /* slave stop detected */
+#define ISR_ALD 0x20 /* arbitration loss detected */
+#define ISR_ITE 0x40 /* tx buffer empty */
+#define ISR_IRF 0x80 /* rx buffer full */
+#define ISR_GCAD 0x100 /* general call address detected */
+#define ISR_SAD 0x200 /* slave address detected */
+#define ISR_BED 0x400 /* bus error no ACK/NAK */
+
+#endif
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 16a536f..5be6dbb 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -2,7 +2,7 @@
* Driver for the TWSI (i2c) controller found on the Marvell
* orion5x and kirkwood SoC families.
*
- * Author: Albert Aribaud <albert.aribaud@free.fr>
+ * Author: Albert Aribaud <albert.u.boot@aribaud.net>
* Copyright (c) 2010 Albert Aribaud.
*
* See file CREDITS for list of people who contributed to this
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index c5ec486..89d1973 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -27,13 +27,8 @@
#if defined(CONFIG_HARD_I2C)
-#if defined(CONFIG_MX31)
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
-#else
-#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#endif
+#include <asm/arch/imx-regs.h>
#define IADR 0x00
#define IFDR 0x04
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 999431c..5a5ecdf 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -32,6 +32,7 @@ COBJS-$(CONFIG_HAS_DATAFLASH) += at45.o
COBJS-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o
+COBJS-$(CONFIG_FTSMC020) += ftsmc020.o
COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o
COBJS-$(CONFIG_SPEARSMI) += spr_smi.o
diff --git a/drivers/mtd/ftsmc020.c b/drivers/mtd/ftsmc020.c
new file mode 100644
index 0000000..b027685
--- /dev/null
+++ b/drivers/mtd/ftsmc020.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/ftsmc020.h>
+
+struct ftsmc020_config {
+ unsigned int config;
+ unsigned int timing;
+};
+
+static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS;
+
+static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE;
+
+static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg)
+{
+ if (bank > 3) {
+ printf("bank # %u invalid\n", bank);
+ return;
+ }
+
+ writel(cfg->config, &smc->bank[bank].cr);
+ writel(cfg->timing, &smc->bank[bank].tpr);
+}
+
+void ftsmc020_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(config); i++)
+ ftsmc020_setup_bank(i, &config[i]);
+}
diff --git a/drivers/power/ftpmu010.c b/drivers/power/ftpmu010.c
index 7924ac1..df99dfa 100644
--- a/drivers/power/ftpmu010.c
+++ b/drivers/power/ftpmu010.c
@@ -23,12 +23,12 @@
#include <common.h>
#include <asm/io.h>
-#include "ftpmu010.h"
-
-static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+#include <faraday/ftpmu010.h>
+/* OSCC: OSC Control Register */
void ftpmu010_32768osc_enable(void)
{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int oscc;
/* enable the 32768Hz oscillator */
@@ -46,8 +46,31 @@ void ftpmu010_32768osc_enable(void)
writel(oscc, &pmu->OSCC);
}
+/* MFPSR: Multi-Function Port Setting Register */
+void ftpmu010_mfpsr_select_dev(unsigned int dev)
+{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+ unsigned int mfpsr;
+
+ mfpsr = readl(&pmu->MFPSR);
+ mfpsr |= dev;
+ writel(mfpsr, &pmu->MFPSR);
+}
+
+void ftpmu010_mfpsr_diselect_dev(unsigned int dev)
+{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+ unsigned int mfpsr;
+
+ mfpsr = readl(&pmu->MFPSR);
+ mfpsr &= ~dev;
+ writel(mfpsr, &pmu->MFPSR);
+}
+
+/* PDLLCR0: PLL/DLL Control Register 0 */
void ftpmu010_dlldis_disable(void)
{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int pdllcr0;
pdllcr0 = readl(&pmu->PDLLCR0);
@@ -57,9 +80,21 @@ void ftpmu010_dlldis_disable(void)
void ftpmu010_sdram_clk_disable(unsigned int cr0)
{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int pdllcr0;
pdllcr0 = readl(&pmu->PDLLCR0);
pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0);
writel(pdllcr0, &pmu->PDLLCR0);
}
+
+/* SDRAMHTC: SDRAM Signal Hold Time Control */
+void ftpmu010_sdramhtc_set(unsigned int val)
+{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+ unsigned int sdramhtc;
+
+ sdramhtc = readl(&pmu->SDRAMHTC);
+ sdramhtc |= val;
+ writel(sdramhtc, &pmu->SDRAMHTC);
+}
diff --git a/drivers/power/ftpmu010.h b/drivers/power/ftpmu010.h
deleted file mode 100644
index 8ef7a37..0000000
--- a/drivers/power/ftpmu010.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Power Management Unit
- */
-#ifndef __FTPMU010_H
-#define __FTPMU010_H
-
-struct ftpmu010 {
- unsigned int IDNMBR0; /* 0x00 */
- unsigned int reserved0; /* 0x04 */
- unsigned int OSCC; /* 0x08 */
- unsigned int PMODE; /* 0x0C */
- unsigned int PMCR; /* 0x10 */
- unsigned int PED; /* 0x14 */
- unsigned int PEDSR; /* 0x18 */
- unsigned int reserved1; /* 0x1C */
- unsigned int PMSR; /* 0x20 */
- unsigned int PGSR; /* 0x24 */
- unsigned int MFPSR; /* 0x28 */
- unsigned int MISC; /* 0x2C */
- unsigned int PDLLCR0; /* 0x30 */
- unsigned int PDLLCR1; /* 0x34 */
- unsigned int AHBMCLKOFF; /* 0x38 */
- unsigned int APBMCLKOFF; /* 0x3C */
- unsigned int DCSRCR0; /* 0x40 */
- unsigned int DCSRCR1; /* 0x44 */
- unsigned int DCSRCR2; /* 0x48 */
- unsigned int SDRAMHTC; /* 0x4C */
- unsigned int PSPR0; /* 0x50 */
- unsigned int PSPR1; /* 0x54 */
- unsigned int PSPR2; /* 0x58 */
- unsigned int PSPR3; /* 0x5C */
- unsigned int PSPR4; /* 0x60 */
- unsigned int PSPR5; /* 0x64 */
- unsigned int PSPR6; /* 0x68 */
- unsigned int PSPR7; /* 0x6C */
- unsigned int PSPR8; /* 0x70 */
- unsigned int PSPR9; /* 0x74 */
- unsigned int PSPR10; /* 0x78 */
- unsigned int PSPR11; /* 0x7C */
- unsigned int PSPR12; /* 0x80 */
- unsigned int PSPR13; /* 0x84 */
- unsigned int PSPR14; /* 0x88 */
- unsigned int PSPR15; /* 0x8C */
- unsigned int AHBDMA_RACCS; /* 0x90 */
- unsigned int reserved2; /* 0x94 */
- unsigned int reserved3; /* 0x98 */
- unsigned int JSS; /* 0x9C */
- unsigned int CFC_RACC; /* 0xA0 */
- unsigned int SSP1_RACC; /* 0xA4 */
- unsigned int UART1TX_RACC; /* 0xA8 */
- unsigned int UART1RX_RACC; /* 0xAC */
- unsigned int UART2TX_RACC; /* 0xB0 */
- unsigned int UART2RX_RACC; /* 0xB4 */
- unsigned int SDC_RACC; /* 0xB8 */
- unsigned int I2SAC97_RACC; /* 0xBC */
- unsigned int IRDATX_RACC; /* 0xC0 */
- unsigned int reserved4; /* 0xC4 */
- unsigned int USBD_RACC; /* 0xC8 */
- unsigned int IRDARX_RACC; /* 0xCC */
- unsigned int IRDA_RACC; /* 0xD0 */
- unsigned int ED0_RACC; /* 0xD4 */
- unsigned int ED1_RACC; /* 0xD8 */
-};
-
-/*
- * ID Number 0 Register
- */
-#define FTPMU010_ID_A320A 0x03200000
-#define FTPMU010_ID_A320C 0x03200010
-#define FTPMU010_ID_A320D 0x03200030
-
-/*
- * OSC Control Register
- */
-#define FTPMU010_OSCC_OSCH_TRI (1 << 11)
-#define FTPMU010_OSCC_OSCH_STABLE (1 << 9)
-#define FTPMU010_OSCC_OSCH_OFF (1 << 8)
-
-#define FTPMU010_OSCC_OSCL_TRI (1 << 3)
-#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2)
-#define FTPMU010_OSCC_OSCL_STABLE (1 << 1)
-#define FTPMU010_OSCC_OSCL_OFF (1 << 0)
-
-/*
- * Power Mode Register
- */
-#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4)
-#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4)
-#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4)
-#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4)
-#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4)
-#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4)
-#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7)
-#define FTPMU010_PMODE_FCS (1 << 2)
-#define FTPMU010_PMODE_TURBO (1 << 1)
-#define FTPMU010_PMODE_SLEEP (1 << 0)
-
-/*
- * Power Manager Status Register
- */
-#define FTPMU010_PMSR_SMR (1 << 10)
-
-#define FTPMU010_PMSR_RDH (1 << 2)
-#define FTPMU010_PMSR_PH (1 << 1)
-#define FTPMU010_PMSR_CKEHLOW (1 << 0)
-
-/*
- * Multi-Function Port Setting Register
- */
-#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14)
-#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13)
-#define FTPMU010_MFPSR_AC97PINSEL (1 << 3)
-
-/*
- * PLL/DLL Control Register 0
- */
-#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf)
-#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19)
-#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18)
-#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17)
-#define FTPMU010_PDLLCR0_DLLDIS (1 << 16)
-#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff)
-#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2)
-#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1)
-#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0)
-
-#endif /* __FTPMU010_H */
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index b9cf9de..dcb4bd1 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -19,12 +19,8 @@
#include <common.h>
#include <watchdog.h>
-#ifdef CONFIG_MX31
-#include <asm/arch/mx31.h>
-#else
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#endif
#define __REG(x) (*((volatile u32 *)(x)))
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 6474eb8..f909e07 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -24,6 +24,8 @@
#include <asm/errno.h>
#include <asm/io.h>
#include <mxc_gpio.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
@@ -34,8 +36,6 @@
#elif defined(CONFIG_MX31)
-#include <asm/arch/mx31.h>
-
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2)
@@ -63,8 +63,6 @@ static unsigned long spi_bases[] = {
#define mxc_get_clock(x) mx31_get_ipg_clk()
#elif defined(CONFIG_MX51)
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
@@ -97,9 +95,6 @@ static unsigned long spi_bases[] = {
#elif defined(CONFIG_MX35)
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index 8d7b380..6af35ab 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -20,7 +20,7 @@
#include <common.h>
#include <usb.h>
#include <asm/io.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
#include <usb/ehci-fsl.h>
#include <errno.h>
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
index 6dd952c..0c925a0 100644
--- a/drivers/video/mx3fb.c
+++ b/drivers/video/mx3fb.c
@@ -22,8 +22,8 @@
*/
#include <common.h>
#include <lcd.h>
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
#include <asm/errno.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -192,7 +192,7 @@ enum ipu_panel {
};
/* IPU Common registers */
-/* IPU_CONF and its bits already defined in mx31-regs.h */
+/* IPU_CONF and its bits already defined in imx-regs.h */
#define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE)
#define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE)
#define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE)