diff options
Diffstat (limited to 'drivers/video/ipu_regs.h')
| -rw-r--r-- | drivers/video/ipu_regs.h | 89 |
1 files changed, 59 insertions, 30 deletions
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index bfa10f5..a60c2b8 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -30,31 +30,60 @@ #ifndef __IPU_REGS_INCLUDED__ #define __IPU_REGS_INCLUDED__ +/* + * hw_rev 2: IPUV3DEX + * hw_rev 3: IPUV3M + * hw_rev 4: IPUV3H + */ +extern int g_ipu_hw_rev; + #define IPU_DISP0_BASE 0x00000000 #define IPU_MCU_T_DEFAULT 8 -#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25) -#define IPU_CM_REG_BASE 0x1E000000 -#define IPU_STAT_REG_BASE 0x1E000200 -#define IPU_IDMAC_REG_BASE 0x1E008000 -#define IPU_ISP_REG_BASE 0x1E010000 -#define IPU_DP_REG_BASE 0x1E018000 -#define IPU_IC_REG_BASE 0x1E020000 -#define IPU_IRT_REG_BASE 0x1E028000 -#define IPU_CSI0_REG_BASE 0x1E030000 -#define IPU_CSI1_REG_BASE 0x1E038000 -#define IPU_DI0_REG_BASE 0x1E040000 -#define IPU_DI1_REG_BASE 0x1E048000 -#define IPU_SMFC_REG_BASE 0x1E050000 -#define IPU_DC_REG_BASE 0x1E058000 -#define IPU_DMFC_REG_BASE 0x1E060000 -#define IPU_CPMEM_REG_BASE 0x1F000000 -#define IPU_LUT_REG_BASE 0x1F020000 -#define IPU_SRM_REG_BASE 0x1F040000 -#define IPU_TPM_REG_BASE 0x1F060000 -#define IPU_DC_TMPL_REG_BASE 0x1F080000 -#define IPU_ISP_TBPR_REG_BASE 0x1F0C0000 -#define IPU_VDI_REG_BASE 0x1E068000 - +#define IPU_DISP1_BASE ({g_ipu_hw_rev < 4 ? \ + (IPU_MCU_T_DEFAULT << 25) : \ + (0x00000000); }) +#define IPUV3DEX_REG_BASE 0x1E000000 +#define IPUV3M_REG_BASE 0x1E000000 +#define IPUV3H_REG_BASE 0x00200000 + +#define IPU_CM_REG_BASE 0x00000000 +#define IPU_STAT_REG_BASE 0x00000200 +#define IPU_IDMAC_REG_BASE 0x00008000 +#define IPU_ISP_REG_BASE 0x00010000 +#define IPU_DP_REG_BASE 0x00018000 +#define IPU_IC_REG_BASE 0x00020000 +#define IPU_IRT_REG_BASE 0x00028000 +#define IPU_CSI0_REG_BASE 0x00030000 +#define IPU_CSI1_REG_BASE 0x00038000 +#define IPU_DI0_REG_BASE 0x00040000 +#define IPU_DI1_REG_BASE 0x00048000 +#define IPU_SMFC_REG_BASE 0x00050000 +#define IPU_DC_REG_BASE 0x00058000 +#define IPU_DMFC_REG_BASE 0x00060000 +#define IPU_VDI_REG_BASE 0x00068000 +#define IPU_CPMEM_REG_BASE ({g_ipu_hw_rev >= 4 ? \ + (0x00100000) : \ + (0x01000000); }) +#define IPU_LUT_REG_BASE ({g_ipu_hw_rev >= 4 ? \ + (0x00120000) : \ + (0x01020000); }) + +#define IPU_SRM_REG_BASE ({g_ipu_hw_rev >= 4 ? \ + (0x00140000) : \ + (0x01040000); }) +#define IPU_TPM_REG_BASE ({g_ipu_hw_rev >= 4 ? \ + (0x00160000) : \ + (0x01060000); }) +#define IPU_DC_TMPL_REG_BASE ({g_ipu_hw_rev >= 4 ? \ + (0x00180000) : \ + (0x01080000); }) +#define IPU_ISP_TBPR_REG_BASE ({g_ipu_hw_rev >= 4 ? \ + (0x001C0000) : \ + (0x010C0000); }) + +#define IPU_DISP_REG_BASE_ADDR ({g_ipu_hw_rev >= 4 ? \ + (IPU_CTRL_BASE_ADDR + IPUV3H_REG_BASE) : \ + (IPU_CTRL_BASE_ADDR + IPUV3M_REG_BASE); }) extern u32 *ipu_dc_tmpl_reg; @@ -303,7 +332,7 @@ struct ipu_dmfc { u32 stat; }; -#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \ +#define IPU_CM_REG ((struct ipu_cm *)(IPU_DISP_REG_BASE_ADDR + \ IPU_CM_REG_BASE)) #define IPU_CONF (&IPU_CM_REG->conf) #define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1) @@ -318,7 +347,7 @@ struct ipu_dmfc { #define IPU_GPR (&IPU_CM_REG->gpr) #define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32]) -#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \ +#define IPU_STAT ((struct ipu_stat *)(IPU_DISP_REG_BASE_ADDR + \ IPU_STAT_REG_BASE)) #define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32]) #define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32]) @@ -326,14 +355,14 @@ struct ipu_dmfc { #define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1]) -#define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \ +#define IDMAC_REG ((struct ipu_idmac *)(IPU_DISP_REG_BASE_ADDR + \ IPU_IDMAC_REG_BASE)) #define IDMAC_CONF (&IDMAC_REG->conf) #define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32]) #define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32]) #define IDMAC_WM_EN(ch) (&IDMAC_REG->wm_en[ch / 32]) -#define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \ +#define DI_REG(di) ((struct ipu_di *)(IPU_DISP_REG_BASE_ADDR + \ ((di == 1) ? IPU_DI1_REG_BASE : \ IPU_DI0_REG_BASE))) #define DI_GENERAL(di) (&DI_REG(di)->general) @@ -349,7 +378,7 @@ struct ipu_dmfc { #define DI_POL(di) (&DI_REG(di)->pol) #define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf) -#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \ +#define DMFC_REG ((struct ipu_dmfc *)(IPU_DISP_REG_BASE_ADDR + \ IPU_DMFC_REG_BASE)) #define DMFC_WR_CHAN (&DMFC_REG->wr_chan) #define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def) @@ -359,7 +388,7 @@ struct ipu_dmfc { #define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl) -#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \ +#define DC_REG ((struct ipu_dc *)(IPU_DISP_REG_BASE_ADDR + \ IPU_DC_REG_BASE)) #define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2]) #define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2]) @@ -402,7 +431,7 @@ static inline struct ipu_dc_ch *dc_ch_offset(int ch) #define DP_ASYNC0 0x60 #define DP_ASYNC1 0xBC -#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \ +#define DP_REG ((struct ipu_dp *)(IPU_DISP_REG_BASE_ADDR + \ IPU_DP_REG_BASE)) #define DP_COM_CONF(flow) (&DP_REG->com_conf_sync) #define DP_GRAPH_WIND_CTRL(flow) (&DP_REG->graph_wind_ctrl_sync) |