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Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/Kconfig2
-rw-r--r--drivers/net/pch_gbe.c28
-rw-r--r--drivers/net/xilinx_emaclite.c90
3 files changed, 62 insertions, 58 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index be3ed73..302c005 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -175,7 +175,7 @@ config XILINX_AXIEMAC
This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
config XILINX_EMACLITE
- depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+ depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || MIPS)
select PHYLIB
select MII
bool "Xilinx Ethernetlite"
diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c
index 137818b..d40fff0 100644
--- a/drivers/net/pch_gbe.c
+++ b/drivers/net/pch_gbe.c
@@ -118,14 +118,14 @@ static void pch_gbe_rx_descs_init(struct udevice *dev)
memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
for (i = 0; i < PCH_GBE_DESC_NUM; i++)
rx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev,
- (u32)(priv->rx_buff[i]));
+ (ulong)(priv->rx_buff[i]));
- writel(dm_pci_phys_to_mem(priv->dev, (u32)rx_desc),
+ writel(dm_pci_phys_to_mem(priv->dev, (ulong)rx_desc),
&mac_regs->rx_dsc_base);
writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
&mac_regs->rx_dsc_size);
- writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_desc + 1)),
+ writel(dm_pci_phys_to_mem(priv->dev, (ulong)(rx_desc + 1)),
&mac_regs->rx_dsc_sw_p);
}
@@ -137,11 +137,11 @@ static void pch_gbe_tx_descs_init(struct udevice *dev)
memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
- writel(dm_pci_phys_to_mem(priv->dev, (u32)tx_desc),
+ writel(dm_pci_phys_to_mem(priv->dev, (ulong)tx_desc),
&mac_regs->tx_dsc_base);
writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
&mac_regs->tx_dsc_size);
- writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_desc + 1)),
+ writel(dm_pci_phys_to_mem(priv->dev, (ulong)(tx_desc + 1)),
&mac_regs->tx_dsc_sw_p);
}
@@ -251,7 +251,7 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length)
if (length < 64)
frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
- tx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (u32)packet);
+ tx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (ulong)packet);
tx_desc->length = length;
tx_desc->tx_words_eob = length + 3;
tx_desc->tx_frame_ctrl = frame_ctrl;
@@ -262,7 +262,7 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length)
if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
priv->tx_idx = 0;
- writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_head + priv->tx_idx)),
+ writel(dm_pci_phys_to_mem(priv->dev, (ulong)(tx_head + priv->tx_idx)),
&mac_regs->tx_dsc_sw_p);
start = get_timer(0);
@@ -283,7 +283,7 @@ static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
struct pch_gbe_priv *priv = dev_get_priv(dev);
struct pch_gbe_regs *mac_regs = priv->mac_regs;
struct pch_gbe_rx_desc *rx_desc;
- u32 hw_desc, buffer_addr, length;
+ ulong hw_desc, buffer_addr, length;
rx_desc = &priv->rx_desc[priv->rx_idx];
@@ -291,7 +291,7 @@ static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
/* Just return if not receiving any packet */
- if ((u32)rx_desc == hw_desc)
+ if ((ulong)rx_desc == hw_desc)
return -EAGAIN;
buffer_addr = dm_pci_mem_to_phys(priv->dev, rx_desc->buffer_addr);
@@ -315,7 +315,7 @@ static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length)
if (++rx_swp >= PCH_GBE_DESC_NUM)
rx_swp = 0;
- writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_head + rx_swp)),
+ writel(dm_pci_phys_to_mem(priv->dev, (ulong)(rx_head + rx_swp)),
&mac_regs->rx_dsc_sw_p);
return 0;
@@ -421,7 +421,7 @@ int pch_gbe_probe(struct udevice *dev)
{
struct pch_gbe_priv *priv;
struct eth_pdata *plat = dev_get_platdata(dev);
- u32 iobase;
+ void *iobase;
/*
* The priv structure contains the descriptors and frame buffers which
@@ -432,11 +432,9 @@ int pch_gbe_probe(struct udevice *dev)
priv->dev = dev;
- dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
- iobase &= PCI_BASE_ADDRESS_MEM_MASK;
- iobase = dm_pci_mem_to_phys(dev, iobase);
+ iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);
- plat->iobase = iobase;
+ plat->iobase = (ulong)iobase;
priv->mac_regs = (struct pch_gbe_regs *)iobase;
/* Read MAC address from SROM and initialize dev->enetaddr with it */
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 7b85aa0..d86e7a3 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -19,6 +19,7 @@
#include <fdtdec.h>
#include <asm-generic/errno.h>
#include <linux/kernel.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -154,7 +155,7 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
unsigned long start = get_timer(0);
while (1) {
- val = readl(reg);
+ val = __raw_readl(reg);
if (!set)
val = ~val;
@@ -193,16 +194,17 @@ static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
if (mdio_wait(regs))
return 1;
- u32 ctrl_reg = in_be32(&regs->mdioctrl);
- out_be32(&regs->mdioaddr, XEL_MDIOADDR_OP_MASK |
- ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
- out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
+ u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
+ __raw_writel(XEL_MDIOADDR_OP_MASK
+ | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
+ | registernum), &regs->mdioaddr);
+ __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
if (mdio_wait(regs))
return 1;
/* Read data */
- *data = in_be32(&regs->mdiord);
+ *data = __raw_readl(&regs->mdiord);
return 0;
}
@@ -220,11 +222,12 @@ static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
* Data register. Finally, set the Status bit in the MDIO Control
* register to start a MDIO write transaction.
*/
- u32 ctrl_reg = in_be32(&regs->mdioctrl);
- out_be32(&regs->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
- ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
- out_be32(&regs->mdiowr, data);
- out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
+ u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
+ __raw_writel(~XEL_MDIOADDR_OP_MASK
+ & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
+ | registernum), &regs->mdioaddr);
+ __raw_writel(data, &regs->mdiowr);
+ __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
if (mdio_wait(regs))
return 1;
@@ -327,27 +330,27 @@ static int emaclite_start(struct udevice *dev)
* TX - TX_PING & TX_PONG initialization
*/
/* Restart PING TX */
- out_be32(&regs->tx_ping_tsr, 0);
+ __raw_writel(0, &regs->tx_ping_tsr);
/* Copy MAC address */
xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
ENET_ADDR_LENGTH);
/* Set the length */
- out_be32(&regs->tx_ping_tplr, ENET_ADDR_LENGTH);
+ __raw_writel(ENET_ADDR_LENGTH, &regs->tx_ping_tplr);
/* Update the MAC address in the EMAC Lite */
- out_be32(&regs->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
+ __raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_ping_tsr);
/* Wait for EMAC Lite to finish with the MAC address update */
- while ((in_be32 (&regs->tx_ping_tsr) &
+ while ((__raw_readl(&regs->tx_ping_tsr) &
XEL_TSR_PROG_MAC_ADDR) != 0)
;
if (emaclite->txpp) {
/* The same operation with PONG TX */
- out_be32(&regs->tx_pong_tsr, 0);
+ __raw_writel(0, &regs->tx_pong_tsr);
xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
ENET_ADDR_LENGTH);
- out_be32(&regs->tx_pong_tplr, ENET_ADDR_LENGTH);
- out_be32(&regs->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
- while ((in_be32(&regs->tx_pong_tsr) &
+ __raw_writel(ENET_ADDR_LENGTH, &regs->tx_pong_tplr);
+ __raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_pong_tsr);
+ while ((__raw_readl(&regs->tx_pong_tsr) &
XEL_TSR_PROG_MAC_ADDR) != 0)
;
}
@@ -356,13 +359,13 @@ static int emaclite_start(struct udevice *dev)
* RX - RX_PING & RX_PONG initialization
*/
/* Write out the value to flush the RX buffer */
- out_be32(&regs->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
+ __raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_ping_rsr);
if (emaclite->rxpp)
- out_be32(&regs->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
+ __raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_pong_rsr);
- out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
- if (in_be32(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
+ __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, &regs->mdioctrl);
+ if (__raw_readl(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
if (!setup_phy(dev))
return -1;
@@ -379,9 +382,9 @@ static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
* Read the other buffer register
* and determine if the other buffer is available
*/
- tmp = ~in_be32(&regs->tx_ping_tsr);
+ tmp = ~__raw_readl(&regs->tx_ping_tsr);
if (emaclite->txpp)
- tmp |= ~in_be32(&regs->tx_pong_tsr);
+ tmp |= ~__raw_readl(&regs->tx_pong_tsr);
return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
}
@@ -405,40 +408,42 @@ static int emaclite_send(struct udevice *dev, void *ptr, int len)
if (!maxtry) {
printf("Error: Timeout waiting for ethernet TX buffer\n");
/* Restart PING TX */
- out_be32(&regs->tx_ping_tsr, 0);
+ __raw_writel(0, &regs->tx_ping_tsr);
if (emaclite->txpp) {
- out_be32(&regs->tx_pong_tsr, 0);
+ __raw_writel(0, &regs->tx_pong_tsr);
}
return -1;
}
/* Determine if the expected buffer address is empty */
- reg = in_be32(&regs->tx_ping_tsr);
+ reg = __raw_readl(&regs->tx_ping_tsr);
if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
debug("Send packet from tx_ping buffer\n");
/* Write the frame to the buffer */
xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
- out_be32(&regs->tx_ping_tplr, len &
- (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
- reg = in_be32(&regs->tx_ping_tsr);
+ __raw_writel(len
+ & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
+ &regs->tx_ping_tplr);
+ reg = __raw_readl(&regs->tx_ping_tsr);
reg |= XEL_TSR_XMIT_BUSY_MASK;
- out_be32(&regs->tx_ping_tsr, reg);
+ __raw_writel(reg, &regs->tx_ping_tsr);
return 0;
}
if (emaclite->txpp) {
/* Determine if the expected buffer address is empty */
- reg = in_be32(&regs->tx_pong_tsr);
+ reg = __raw_readl(&regs->tx_pong_tsr);
if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
debug("Send packet from tx_pong buffer\n");
/* Write the frame to the buffer */
xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
- out_be32(&regs->tx_pong_tplr, len &
+ __raw_writel(len &
(XEL_TPLR_LENGTH_MASK_HI |
- XEL_TPLR_LENGTH_MASK_LO));
- reg = in_be32(&regs->tx_pong_tsr);
+ XEL_TPLR_LENGTH_MASK_LO),
+ &regs->tx_pong_tplr);
+ reg = __raw_readl(&regs->tx_pong_tsr);
reg |= XEL_TSR_XMIT_BUSY_MASK;
- out_be32(&regs->tx_pong_tsr, reg);
+ __raw_writel(reg, &regs->tx_pong_tsr);
return 0;
}
}
@@ -458,7 +463,7 @@ static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
try_again:
if (!emaclite->use_rx_pong_buffer_next) {
- reg = in_be32(&regs->rx_ping_rsr);
+ reg = __raw_readl(&regs->rx_ping_rsr);
debug("Testing data at rx_ping\n");
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
debug("Data found in rx_ping buffer\n");
@@ -478,7 +483,7 @@ try_again:
goto try_again;
}
} else {
- reg = in_be32(&regs->rx_pong_rsr);
+ reg = __raw_readl(&regs->rx_pong_rsr);
debug("Testing data at rx_pong\n");
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
debug("Data found in rx_pong buffer\n");
@@ -525,9 +530,9 @@ try_again:
length - first_read);
/* Acknowledge the frame */
- reg = in_be32(ack);
+ reg = __raw_readl(ack);
reg &= ~XEL_RSR_RECV_DONE_MASK;
- out_be32(ack, reg);
+ __raw_writel(reg, ack);
debug("Packet receive from 0x%p, length %dB\n", addr, length);
*packetp = etherrxbuff;
@@ -595,7 +600,8 @@ static int emaclite_ofdata_to_platdata(struct udevice *dev)
int offset = 0;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
- emaclite->regs = (struct emaclite_regs *)pdata->iobase;
+ emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
+ 0x10000);
emaclite->phyaddr = -1;
generated by cgit v1.1 at 2024-09-04 11:19:27 +0000