summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc85xx/Makefile4
-rw-r--r--cpu/mpc85xx/commproc.c28
-rw-r--r--cpu/mpc85xx/cpu.c124
-rw-r--r--cpu/mpc85xx/cpu_init.c16
-rw-r--r--cpu/mpc85xx/ether_fcc.c54
-rw-r--r--cpu/mpc85xx/fdt.c64
-rw-r--r--cpu/mpc85xx/interrupts.c10
-rw-r--r--cpu/mpc85xx/pci.c34
-rw-r--r--cpu/mpc85xx/qe_io.c4
-rw-r--r--cpu/mpc85xx/serial_scc.c35
-rw-r--r--cpu/mpc85xx/spd_sdram.c17
-rw-r--r--cpu/mpc85xx/speed.c34
-rw-r--r--cpu/mpc85xx/traps.c4
13 files changed, 196 insertions, 232 deletions
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index 32091fa..d179d70 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -29,8 +29,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o resetvec.o
+COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
- pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o
+ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \
+ $(COBJS-y)
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c
index 3504d50..b0ecd25 100644
--- a/cpu/mpc85xx/commproc.c
+++ b/cpu/mpc85xx/commproc.c
@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
void
m8560_cpm_reset(void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile ulong count;
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
@@ -50,11 +50,11 @@ m8560_cpm_reset(void)
/*
* Reset CPM
*/
- immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST;
+ cpm->im_cpm_cp.cpcr = CPM_CR_RST;
count = 0;
do { /* Spin until command processed */
__asm__ __volatile__ ("eieio");
- } while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
+ } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
}
/* Allocate some memory from the dual ported ram.
@@ -64,7 +64,7 @@ m8560_cpm_reset(void)
uint
m8560_cpm_dpalloc(uint size, uint align)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
uint retloc;
uint align_mask, off;
uint savebase;
@@ -86,7 +86,7 @@ m8560_cpm_dpalloc(uint size, uint align)
retloc = gd->dp_alloc_base;
gd->dp_alloc_base += size;
- memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size);
+ memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
return(retloc);
}
@@ -120,16 +120,16 @@ m8560_cpm_hostalloc(uint size, uint align)
void
m8560_cpm_setbrg(uint brg, uint rate)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+ bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
}
else {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+ bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
@@ -142,16 +142,16 @@ m8560_cpm_setbrg(uint brg, uint rate)
void
m8560_cpm_fastbrg(uint brg, uint rate, int div16)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile uint *bp;
/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+ bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
}
else {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+ bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
@@ -167,14 +167,14 @@ m8560_cpm_fastbrg(uint brg, uint rate, int div16)
void
m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile uint *bp;
if (brg < 4) {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+ bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
}
else {
- bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+ bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
brg -= 4;
}
bp += brg;
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index bbc5444..ac8b018 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -30,11 +30,6 @@
#include <command.h>
#include <asm/cache.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
-
int checkcpu (void)
{
sys_info_t sysinfo;
@@ -44,6 +39,8 @@ int checkcpu (void)
uint fam;
uint ver;
uint major, minor;
+ u32 ddr_ratio;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
svr = get_svr();
ver = SVR_VER(svr);
@@ -107,14 +104,25 @@ int checkcpu (void)
puts("Clock Configuration:\n");
printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
- printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
+
+ ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ switch (ddr_ratio) {
+ case 0x0:
+ printf(" DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000);
+ break;
+ case 0x7:
+ printf(" DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000);
+ break;
+ default:
+ printf(" DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000);
+ break;
+ }
#if defined(CFG_LBC_LCRR)
lcrr = CFG_LBC_LCRR;
#else
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
lcrr = lbc->lcrr;
}
@@ -214,8 +222,7 @@ reset_85xx_watchdog(void)
#if defined(CONFIG_DDR_ECC)
void dma_init(void) {
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
dma->satr0 = 0x02c40000;
dma->datr0 = 0x02c40000;
@@ -225,8 +232,7 @@ void dma_init(void) {
}
uint dma_check(void) {
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
volatile uint status = dma->sr0;
/* While the channel is busy, spin */
@@ -245,8 +251,7 @@ uint dma_check(void) {
}
int dma_xfer(void *dest, uint count, void *src) {
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
dma->dar0 = (uint) dest;
dma->sar0 = (uint) src;
@@ -258,94 +263,3 @@ int dma_xfer(void *dest, uint count, void *src) {
return dma_check();
}
#endif
-
-
-#ifdef CONFIG_OF_FLAT_TREE
-void
-ft_cpu_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- ulong clock;
- int len;
-
- clock = bd->bi_busfreq;
- p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(clock);
-
- p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(clock);
-
- p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(clock);
-
- p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
- if (p != NULL)
- *p = cpu_to_be32(clock);
-
-#if defined(CONFIG_HAS_ETH0)
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enetaddr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enetaddr, 6);
-#endif
-
-#if defined(CONFIG_HAS_ETH1)
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet1addr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet1addr, 6);
-#endif
-
-#if defined(CONFIG_HAS_ETH2)
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet2addr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet2addr, 6);
-
-#ifdef CONFIG_UEC_ETH
- p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet2addr, 6);
-
- p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet2addr, 6);
-
-#endif
-#endif
-
-#if defined(CONFIG_HAS_ETH3)
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet3addr, 6);
-
- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet3addr, 6);
-
-#ifdef CONFIG_UEC_ETH
- p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet3addr, 6);
-
- p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
- if (p)
- memcpy(p, bd->bi_enet3addr, 6);
-
-#endif
-#endif
-
-}
-#endif
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 79ad20c..fdb9ecb 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -59,7 +59,7 @@ static void config_qe_ioports(void)
#endif
#ifdef CONFIG_CPM2
-static void config_8560_ioports (volatile immap_t * immr)
+void config_8560_ioports (volatile ccsr_cpm_t * cpm)
{
int portnum;
@@ -99,7 +99,7 @@ static void config_8560_ioports (volatile immap_t * immr)
}
if (pmsk != 0) {
- volatile ioport_t *iop = ioport_addr (immr, portnum);
+ volatile ioport_t *iop = ioport_addr (cpm, portnum);
uint tpmsk = ~pmsk;
/*
@@ -131,8 +131,7 @@ static void config_8560_ioports (volatile immap_t * immr)
void cpu_init_f (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+ volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
extern void m8560_cpm_reset (void);
/* Pointer is writable since we allocated a register for it */
@@ -143,7 +142,7 @@ void cpu_init_f (void)
#ifdef CONFIG_CPM2
- config_8560_ioports(immap);
+ config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
#endif
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
@@ -222,18 +221,15 @@ void cpu_init_f (void)
int cpu_init_r(void)
{
-#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE)
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
-#endif
#ifdef CONFIG_CLEAR_LAW0
- volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
/* clear alternate boot location LAW (used for sdram, or ddr bank) */
ecm->lawar0 = 0;
#endif
#if defined(CONFIG_L2_CACHE)
- volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
+ volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
volatile uint cache_ctl;
uint svr, ver;
uint l2srbar;
diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c
index 5b23a80..bd62aab 100644
--- a/cpu/mpc85xx/ether_fcc.c
+++ b/cpu/mpc85xx/ether_fcc.c
@@ -230,8 +230,8 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
{
struct ether_fcc_info_s * info = dev->priv;
int i;
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp);
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+ volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
fcc_enet_t *pram_ptr;
unsigned long mem_addr;
@@ -242,35 +242,35 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
/* 28.9 - (1-2): ioports have been set up already */
/* 28.9 - (3): connect FCC's tx and rx clocks */
- immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */
- immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
+ cpm->im_cpm_mux.cmxuar = 0; /* ATM */
+ cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
info->cmxfcr_value;
/* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+ cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
} else if (info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+ cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
} else if (info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+ cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
}
/* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ cpm->im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
} else if (info->ether_index == 1){
- immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ cpm->im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
} else if (info->ether_index == 2){
- immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ cpm->im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
}
/* 28.9 - (6): FDSR: Ethernet Syn */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555;
+ cpm->im_cpm_fcc1.fdsr = 0xD555;
} else if (info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555;
+ cpm->im_cpm_fcc2.fdsr = 0xD555;
} else if (info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555;
+ cpm->im_cpm_fcc3.fdsr = 0xD555;
}
/* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
@@ -296,7 +296,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
/* 28.9 - (7): initialize parameter ram */
- pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]);
+ pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]);
/* clear whole structure to make sure all reserved fields are zero */
memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
@@ -385,14 +385,14 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
/* 28.9 - (8)(9): clear out events in FCCE */
/* 28.9 - (9): FCCM: mask all events */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.fcce = ~0x0;
- immr->im_cpm.im_cpm_fcc1.fccm = 0;
+ cpm->im_cpm_fcc1.fcce = ~0x0;
+ cpm->im_cpm_fcc1.fccm = 0;
} else if (info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.fcce = ~0x0;
- immr->im_cpm.im_cpm_fcc2.fccm = 0;
+ cpm->im_cpm_fcc2.fcce = ~0x0;
+ cpm->im_cpm_fcc2.fccm = 0;
} else if (info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.fcce = ~0x0;
- immr->im_cpm.im_cpm_fcc3.fccm = 0;
+ cpm->im_cpm_fcc3.fcce = ~0x0;
+ cpm->im_cpm_fcc3.fccm = 0;
}
/* 28.9 - (10-12): we don't use ethernet interrupts */
@@ -413,11 +413,11 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
/* 28.9 - (14): enable tx/rx in gfmr */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+ cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
} else if (info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+ cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
} else if (info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+ cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
}
return 1;
@@ -426,15 +426,15 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
static void fec_halt(struct eth_device* dev)
{
struct ether_fcc_info_s * info = dev->priv;
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
/* write GFMR: disable tx/rx */
if(info->ether_index == 0) {
- immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+ cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
} else if(info->ether_index == 1) {
- immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+ cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
} else if(info->ether_index == 2) {
- immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+ cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
}
}
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
new file mode 100644
index 0000000..737a6c4
--- /dev/null
+++ b/cpu/mpc85xx/fdt.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
+ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+ fdt_fixup_ethernet(blob, bd);
+#endif
+
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "timebase-frequency", bd->bi_busfreq / 8, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "clock-frequency", bd->bi_intfreq, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+ "bus-frequency", bd->bi_busfreq, 1);
+#ifdef CONFIG_QE
+ do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+ "bus-frequency", bd->bi_busfreq, 1);
+#endif
+
+#ifdef CFG_NS16550
+ do_fixup_by_compat_u32(blob, "ns16550",
+ "clock-frequency", bd->bi_busfreq, 1);
+#endif
+
+#ifdef CONFIG_CPM2
+ do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
+ "current-speed", bd->bi_baudrate, 1);
+
+ do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
+ "clock-frequency", bd->bi_brgfreq, 1);
+#endif
+
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c
index bf737d6..18e5377 100644
--- a/cpu/mpc85xx/interrupts.c
+++ b/cpu/mpc85xx/interrupts.c
@@ -80,19 +80,17 @@ int disable_interrupts (void)
int interrupt_init (void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
- immr->im_pic.gcr = MPC85xx_PICGCR_RST;
- while (immr->im_pic.gcr & MPC85xx_PICGCR_RST);
- immr->im_pic.gcr = MPC85xx_PICGCR_M;
+ pic->gcr = MPC85xx_PICGCR_RST;
+ while (pic->gcr & MPC85xx_PICGCR_RST);
+ pic->gcr = MPC85xx_PICGCR_M;
decrementer_count = get_tbclk() / CFG_HZ;
mtspr(SPRN_TCR, TCR_PIE);
set_dec (decrementer_count);
set_msr (get_msr () | MSR_EE);
#ifdef CONFIG_INTERRUPTS
- volatile ccsr_pic_t *pic = &immr->im_pic;
-
pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */
debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index db09e45..a5060cd 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -29,10 +29,6 @@
#include <asm/cpm_85xx.h>
#include <pci.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#endif
-
#if defined(CONFIG_PCI)
static struct pci_controller *pci_hose;
@@ -43,12 +39,11 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
u16 reg16;
u32 dev;
- volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
- volatile ccsr_pcix_t *pcix = &immap->im_pcix;
+ volatile ccsr_pcix_t *pcix = (void *)(CFG_MPC85xx_PCIX_ADDR);
#ifdef CONFIG_MPC85XX_PCI2
- volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
+ volatile ccsr_pcix_t *pcix2 = (void *)(CFG_MPC85xx_PCIX2_ADDR);
#endif
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
struct pci_controller * hose;
pci_hose = board_hose;
@@ -216,27 +211,4 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
hose->last_busno = pci_hose_scan(hose);
#endif
}
-
-#ifdef CONFIG_OF_FLAT_TREE
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
- if (p != NULL) {
- p[0] = pci_hose[0].first_busno;
- p[1] = pci_hose[0].last_busno;
- }
-
-#ifdef CONFIG_MPC85XX_PCI2
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
- if (p != NULL) {
- p[0] = pci_hose[1].first_busno;
- p[1] = pci_hose[1].last_busno;
- }
-#endif
-}
-#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_PCI */
diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c
index 8878bc5..98075bb 100644
--- a/cpu/mpc85xx/qe_io.c
+++ b/cpu/mpc85xx/qe_io.c
@@ -34,9 +34,9 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
u32 pin_2bit_assign;
u32 pin_1bit_mask;
u32 tmp_val;
- volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
volatile par_io_t *par_io = (volatile par_io_t *)
- &(im->im_gur.qe_par_io);
+ &(gur->qe_par_io);
/* Caculate pin location and 2bit mask and dir */
pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c
index 4e925f8..7ee3cc8 100644
--- a/cpu/mpc85xx/serial_scc.c
+++ b/cpu/mpc85xx/serial_scc.c
@@ -88,17 +88,17 @@ DECLARE_GLOBAL_DATA_PTR;
int serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
volatile ccsr_cpm_scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
- volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp);
+ volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
uint dpaddr;
/* initialize pointers to SCC */
- sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]);
- up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
+ sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]);
+ up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
/* Disable transmitter/receiver.
*/
@@ -107,8 +107,8 @@ int serial_init (void)
/* put the SCC channel into NMSI (non multiplexd serial interface)
* mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
*/
- im->im_cpm.im_cpm_mux.cmxscr = \
- (im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
+ cpm->im_cpm_mux.cmxscr = \
+ (cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
/* Set up the baud rate generator.
*/
@@ -123,7 +123,7 @@ int serial_init (void)
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
- rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]);
+ rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]);
rbdf->cbd_bufaddr = (uint) (rbdf+2);
rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
tbdf = rbdf + 1;
@@ -201,14 +201,13 @@ serial_putc(const char c)
{
volatile scc_uart_t *up;
volatile cbd_t *tbdf;
- volatile immap_t *im;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
if (c == '\n')
serial_putc ('\r');
- im = (immap_t *)CFG_IMMR;
- up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
- tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]);
+ up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
+ tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]);
/* Wait for last character to go.
*/
@@ -235,12 +234,11 @@ serial_getc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile immap_t *im;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
unsigned char c;
- im = (immap_t *)CFG_IMMR;
- up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
- rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
+ up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
+ rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
/* Wait for character to show up.
*/
@@ -260,11 +258,10 @@ serial_tstc()
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile immap_t *im;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
- im = (immap_t *)CFG_IMMR;
- up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
- rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
+ up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
+ rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
}
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 5dc223a..553f736 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -53,8 +53,8 @@ picos_to_clk(int picos)
{
int clks;
- clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
- if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+ clks = picos / (2000000000 / (get_ddr_freq(0) / 1000));
+ if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) {
clks++;
}
@@ -171,8 +171,7 @@ unsigned int determine_refresh_rate(unsigned int spd_refresh)
long int
spd_sdram(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
spd_eeprom_t spd;
unsigned int n_ranks;
unsigned int rank_density;
@@ -309,7 +308,7 @@ spd_sdram(void)
if ((SVR_VER(get_svr()) == SVR_8548_E) &&
(SVR_MJREV(get_svr()) == 1) &&
(spd.mem_type == SPD_MEMTYPE_DDR2)) {
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
gur->ddrioovcr = (0x80000000 /* Enable */
| 0x10000000);/* VSEL to 1.8V */
}
@@ -422,7 +421,7 @@ spd_sdram(void)
* Adjust the CAS Latency to allow for bus speeds that
* are slower than the DDR module.
*/
- busfreq = get_bus_freq(0) / 1000000; /* MHz */
+ busfreq = get_ddr_freq(0) / 1000000; /* MHz */
effective_data_rate = max_data_rate;
if (busfreq < 90) {
@@ -1023,8 +1022,7 @@ spd_sdram(void)
static unsigned int
setup_laws_and_tlbs(unsigned int memsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
unsigned int tlb_size;
unsigned int law_size;
unsigned int ram_tlb_index;
@@ -1130,8 +1128,7 @@ ddr_enable_ecc(unsigned int dram_size)
{
uint *p = 0;
uint i = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
dma_init();
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 12359a2..27de37a 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -35,8 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info (sys_info_t * sysInfo)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint plat_ratio,e500_ratio,half_freqSystemBus;
plat_ratio = (gur->porpllsr) & 0x0000003e;
@@ -49,6 +48,15 @@ void get_sys_info (sys_info_t * sysInfo)
* overflow for processor speeds above 2GHz */
half_freqSystemBus = sysInfo->freqSystemBus/2;
sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
+ sysInfo->freqDDRBus = sysInfo->freqSystemBus;
+
+#ifdef CONFIG_DDR_CLK_FREQ
+ {
+ u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+ if (ddr_ratio != 0x7)
+ sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
+ }
+#endif
}
@@ -56,12 +64,12 @@ int get_clocks (void)
{
sys_info_t sys_info;
#if defined(CONFIG_CPM2)
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
uint sccr, dfbrg;
/* set VCO = 4 * BRG */
- immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc;
- sccr = immap->im_cpm.im_cpm_intctl.sccr;
+ cpm->im_cpm_intctl.sccr &= 0xfffffffc;
+ sccr = cpm->im_cpm_intctl.sccr;
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
get_sys_info (&sys_info);
@@ -94,3 +102,19 @@ ulong get_bus_freq (ulong dummy)
return val;
}
+
+/********************************************
+ * get_ddr_freq
+ * return ddr bus freq in Hz
+ *********************************************/
+ulong get_ddr_freq (ulong dummy)
+{
+ ulong val;
+
+ sys_info_t sys_info;
+
+ get_sys_info (&sys_info);
+ val = sys_info.freqDDRBus;
+
+ return val;
+}
diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c
index efc80c7..2381fb0 100644
--- a/cpu/mpc85xx/traps.c
+++ b/cpu/mpc85xx/traps.c
@@ -288,8 +288,8 @@ UnknownException(struct pt_regs *regs)
void
ExtIntException(struct pt_regs *regs)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_pic_t *pic = &immap->im_pic;
+ volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
+
uint vect;
#if defined(CONFIG_CMD_KGDB)
generated by cgit v1.1 at 2024-11-07 05:17:39 +0000