summaryrefslogtreecommitdiff
path: root/cpu/ppc4xx/start.S
diff options
context:
space:
mode:
Diffstat (limited to 'cpu/ppc4xx/start.S')
-rw-r--r--cpu/ppc4xx/start.S128
1 files changed, 111 insertions, 17 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 60ed2d5..5a1ab38 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -117,12 +117,16 @@
.extern ext_bus_cntlr_init
.extern sdram_init
+#ifdef CONFIG_NAND_U_BOOT
+ .extern reconfig_tlb0
+#endif
/*
* Set up GOT: Global Offset Table
*
* Use r14 to access the GOT
*/
+#if !defined(CONFIG_NAND_SPL)
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
@@ -136,6 +140,18 @@
GOT_ENTRY(_end)
GOT_ENTRY(__bss_start)
END_GOT
+#endif /* CONFIG_NAND_SPL */
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+ /*
+ * NAND U-Boot image is started from offset 0
+ */
+ .text
+ bl reconfig_tlb0
+ GET_GOT
+ bl cpu_init_f /* run low-level CPU init code (from Flash) */
+ bl board_init_f
+#endif
/*
* 440 Startup -- on reset only the top 4k of the effective
@@ -150,11 +166,21 @@
*/
#if defined(CONFIG_440)
+#if !defined(CONFIG_NAND_SPL)
.section .bootpg,"ax"
+#endif
.globl _start_440
/**************************************************************************/
_start_440:
+ /*--------------------------------------------------------------------+
+ | 440EPX BUP Change - Hardware team request
+ +--------------------------------------------------------------------*/
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+ sync
+ nop
+ nop
+#endif
/*----------------------------------------------------------------+
| Core bug fix. Clear the esr
+-----------------------------------------------------------------*/
@@ -171,15 +197,19 @@ _start_440:
mtspr srr1,r0
mtspr csrr0,r0
mtspr csrr1,r0
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* NOTE: 440GX adds machine check status regs */
+ /* NOTE: 440GX adds machine check status regs */
+#if defined(CONFIG_440) && !defined(CONFIG_440GP)
mtspr mcsrr0,r0
mtspr mcsrr1,r0
- mfspr r1, mcsr
+ mfspr r1,mcsr
mtspr mcsr,r1
#endif
/*----------------------------------------------------------------*/
/* Initialize debug */
/*----------------------------------------------------------------*/
+ mfspr r1,dbcr0
+ andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
+ bne skip_debug_init /* if set, don't clear debug register */
mtspr dbcr0,r0
mtspr dbcr1,r0
mtspr dbcr2,r0
@@ -193,6 +223,7 @@ _start_440:
mfspr r1,dbsr
mtspr dbsr,r1 /* Clear all valid bits */
+skip_debug_init:
/*----------------------------------------------------------------*/
/* CCR0 init */
@@ -352,7 +383,53 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
/*----------------------------------------------------------------*/
/* Continue from 'normal' start */
/*----------------------------------------------------------------*/
-2: bl 3f
+2:
+
+#if defined(CONFIG_NAND_SPL)
+ /*
+ * Enable internal SRAM
+ */
+ lis r2,0x7fff
+ ori r2,r2,0xffff
+ mfdcr r1,isram0_dpc
+ and r1,r1,r2 /* Disable parity check */
+ mtdcr isram0_dpc,r1
+ mfdcr r1,isram0_pmeg
+ and r1,r1,r2 /* Disable pwr mgmt */
+ mtdcr isram0_pmeg,r1
+
+ /*
+ * Copy SPL from cache into internal SRAM
+ */
+ li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
+ mtctr r4
+ lis r2,CFG_NAND_BOOT_SPL_SRC@h
+ ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
+ lis r3,CFG_NAND_BOOT_SPL_DST@h
+ ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
+spl_loop:
+ lwzu r4,4(r2)
+ stwu r4,4(r3)
+ bdnz spl_loop
+
+ /*
+ * Jump to code in RAM
+ */
+ bl 00f
+00: mflr r10
+ lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
+ ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
+ sub r10,r10,r3
+ addi r10,r10,28
+ mtlr r10
+ blr
+
+start_ram:
+ sync
+ isync
+#endif
+
+ bl 3f
b _start
3: li r0,0
@@ -366,6 +443,7 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
*/
+#ifndef CONFIG_NAND_SPL
.text
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
@@ -379,6 +457,7 @@ version_string:
* location (0x100) is where the CriticalInput Execption should be.
*/
. = EXC_OFF_SYS_RESET
+#endif
.globl _start
_start:
@@ -417,7 +496,8 @@ _start:
/* Setup the internal SRAM */
/*----------------------------------------------------------------*/
li r0,0
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+#ifdef CFG_INIT_RAM_DCACHE
/* Clear Dcache to use as RAM */
addis r3,r0,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
@@ -433,19 +513,22 @@ _start:
dcbz r0,r3
addi r3,r3,32
bdnz ..d_ag
-#else
-#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#endif /* CFG_INIT_RAM_DCACHE */
+
+ /* 440EP & 440GR are only 440er PPC's without internal SRAM */
+#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
+ /* not all PPC's have internal SRAM usable as L2-cache */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
- mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
- li r2,0x7fff
+ lis r2,0x7fff
ori r2,r2,0xffff
mfdcr r1,isram0_dpc
and r1,r1,r2 /* Disable parity check */
mtdcr isram0_dpc,r1
mfdcr r1,isram0_pmeg
- andis. r1,r1,r2 /* Disable pwr mgmt */
+ and r1,r1,r2 /* Disable pwr mgmt */
mtdcr isram0_pmeg,r1
lis r1,0x8000 /* BAS = 8000_0000 */
@@ -474,11 +557,12 @@ _start:
lis r1, 0x0003
ori r1,r1, 0x0984 /* fourth 64k */
mtdcr isram0_sb3cr,r1
-#else
+#elif defined(CONFIG_440GP)
ori r1,r1,0x0380 /* 8k rw */
mtdcr isram0_sb0cr,r1
+ mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
#endif
-#endif
+#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
/*----------------------------------------------------------------*/
/* Setup the stack in internal SRAM */
@@ -495,10 +579,14 @@ _start:
stwu r1,-8(r1) /* Save back chain and move SP */
stw r0,+12(r1) /* Save return addr (underflow vect) */
+#ifdef CONFIG_NAND_SPL
+ bl nand_boot /* will not return */
+#else
GET_GOT
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
+#endif
#endif /* CONFIG_440 */
@@ -808,6 +896,7 @@ _start:
/*----------------------------------------------------------------------- */
+#ifndef CONFIG_NAND_SPL
/*****************************************************************************/
.globl _start_of_vectors
_start_of_vectors:
@@ -1013,6 +1102,7 @@ crit_return:
lwz r1,GPR1(r1)
SYNC
rfci
+#endif /* CONFIG_NAND_SPL */
/* Cache functions.
*/
@@ -1254,6 +1344,7 @@ ppcSync:
/*------------------------------------------------------------------------------*/
+#ifndef CONFIG_NAND_SPL
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
@@ -1267,7 +1358,9 @@ ppcSync:
*/
.globl relocate_code
relocate_code:
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SPE)
/*
* On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
* to speed up the boot process. Now this cache needs to be disabled.
@@ -1482,22 +1575,22 @@ trap_init:
cmplw 0, r7, r8
blt 4b
-#if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE)
+#if !defined(CONFIG_440)
addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
mtmsr r7 /* change MSR */
#else
- bl __440gx_msr_set
- b __440gx_msr_continue
+ bl __440_msr_set
+ b __440_msr_continue
-__440gx_msr_set:
+__440_msr_set:
addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
mtspr srr1,r7
mflr r7
mtspr srr0,r7
rfi
-__440gx_msr_continue:
+__440_msr_continue:
#endif
mtlr r4 /* restore link register */
@@ -1516,6 +1609,7 @@ trap_reloc:
stw r0, 4(r7)
blr
+#endif /* CONFIG_NAND_SPL */
/**************************************************************************/