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Diffstat (limited to 'cpu/ppc4xx/440spe_pcie.c')
-rw-r--r--cpu/ppc4xx/440spe_pcie.c47
1 files changed, 40 insertions, 7 deletions
diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c
index d6c4be5..bf68cc1 100644
--- a/cpu/ppc4xx/440spe_pcie.c
+++ b/cpu/ppc4xx/440spe_pcie.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2006
+ * (C) Copyright 2006 - 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (c) 2005 Cisco Systems. All rights reserved.
@@ -40,6 +40,34 @@ enum {
LNKW_X8 = 0x8
};
+static inline int pcie_in_8(const volatile unsigned char __iomem *addr)
+{
+ int ret;
+
+ PCIE_IN(lbzx, ret, addr);
+
+ return ret;
+}
+
+static inline int pcie_in_le16(const volatile unsigned short __iomem *addr)
+{
+ int ret;
+
+ PCIE_IN(lhbrx, ret, addr)
+
+ return ret;
+}
+
+static inline unsigned pcie_in_le32(const volatile unsigned __iomem *addr)
+{
+ unsigned ret;
+
+ PCIE_IN(lwbrx, ret, addr);
+
+ return ret;
+}
+
+
static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 *val) {
@@ -55,13 +83,13 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
switch (len) {
case 1:
- *val = in_8(hose->cfg_data + offset);
+ *val = pcie_in_8(hose->cfg_data + offset);
break;
case 2:
- *val = in_le16((u16 *)(hose->cfg_data + offset));
+ *val = pcie_in_le16((u16 *)(hose->cfg_data + offset));
break;
default:
- *val = in_le32((u32 *)(hose->cfg_data + offset));
+ *val = pcie_in_le32((u32*)(hose->cfg_data + offset));
break;
}
return 0;
@@ -783,9 +811,14 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
/*
* Set bus numbers on our root port
*/
- out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
- out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
- out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
+ if (ppc440spe_revB()) {
+ out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
+ out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
+ out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
+ } else {
+ out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
+ out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
+ }
/*
* Set up outbound translation to hose->mem_space from PLB