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-rw-r--r--cpu/arm920t/at91rm9200/usb.c8
-rw-r--r--cpu/arm920t/s3c24x0/Makefile2
-rw-r--r--cpu/arm920t/s3c24x0/usb_ohci.c14
-rw-r--r--cpu/arm920t/start.S128
4 files changed, 33 insertions, 119 deletions
diff --git a/cpu/arm920t/at91rm9200/usb.c b/cpu/arm920t/at91rm9200/usb.c
index 366262e..c121de6 100644
--- a/cpu/arm920t/at91rm9200/usb.c
+++ b/cpu/arm920t/at91rm9200/usb.c
@@ -28,7 +28,7 @@
#include <asm/arch/hardware.h>
-int usb_cpu_init()
+int usb_cpu_init(void)
{
/* Enable USB host clock. */
*AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */
@@ -36,7 +36,7 @@ int usb_cpu_init()
return 0;
}
-int usb_cpu_stop()
+int usb_cpu_stop(void)
{
/* Initialization failed */
*AT91C_PMC_PCDR = 1 << AT91C_ID_UHP; /* Peripheral Clock Disable Register */
@@ -44,9 +44,9 @@ int usb_cpu_stop()
return 0;
}
-int usb_cpu_init_fail()
+int usb_cpu_init_fail(void)
{
- usb_cpu_stop();
+ return usb_cpu_stop();
}
# endif /* CONFIG_AT91RM9200 */
diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile
index 0ff36c5..1ed9bf3 100644
--- a/cpu/arm920t/s3c24x0/Makefile
+++ b/cpu/arm920t/s3c24x0/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS = i2c.o interrupts.o serial.o speed.o \
- usb.o
+ usb.o usb_ohci.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c
index 869ca79..4075f2e 100644
--- a/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/cpu/arm920t/s3c24x0/usb_ohci.c
@@ -498,7 +498,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
if (ohci->ed_controltail == NULL) {
writel (ed, &ohci->regs->ed_controlhead);
} else {
- ohci->ed_controltail->hwNextED = m32_swap (ed);
+ ohci->ed_controltail->hwNextED = (__u32)m32_swap (ed);
}
ed->ed_prev = ohci->ed_controltail;
if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
@@ -514,7 +514,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
if (ohci->ed_bulktail == NULL) {
writel (ed, &ohci->regs->ed_bulkhead);
} else {
- ohci->ed_bulktail->hwNextED = m32_swap (ed);
+ ohci->ed_bulktail->hwNextED = (__u32)m32_swap (ed);
}
ed->ed_prev = ohci->ed_bulktail;
if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
@@ -606,7 +606,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
/* dummy td; end of td list for ed */
td = td_alloc (usb_dev);
- ed->hwTailP = m32_swap (td);
+ ed->hwTailP = (__u32)m32_swap (td);
ed->hwHeadP = ed->hwTailP;
ed->state = ED_UNLINK;
ed->type = usb_pipetype (pipe);
@@ -663,13 +663,13 @@ static void td_fill (ohci_t *ohci, unsigned int info,
if (!len)
data = 0;
- td->hwINFO = m32_swap (info);
- td->hwCBP = m32_swap (data);
+ td->hwINFO = (__u32)m32_swap (info);
+ td->hwCBP = (__u32)m32_swap (data);
if (data)
- td->hwBE = m32_swap (data + len - 1);
+ td->hwBE = (__u32)m32_swap (data + len - 1);
else
td->hwBE = 0;
- td->hwNextTD = m32_swap (td_pt);
+ td->hwNextTD = (__u32)m32_swap (td_pt);
/* append to queue */
td->ed->hwTailP = td->hwNextTD;
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index b9c364b..aefcdd1 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -27,9 +27,7 @@
#include <config.h>
#include <version.h>
-#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
-#include <led.h>
-#endif
+#include <status_led.h>
/*
*************************************************************************
@@ -41,7 +39,7 @@
.globl _start
-_start: b reset
+_start: b start_code
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -64,7 +62,7 @@ _fiq: .word fiq
/*
*************************************************************************
*
- * Startup Code (reset vector)
+ * Startup Code (called from the ARM reset exception vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
@@ -106,10 +104,10 @@ FIQ_STACK_START:
/*
- * the actual reset code
+ * the actual start code
*/
-reset:
+start_code:
/*
* set the cpu to SVC32 mode
*/
@@ -118,58 +116,12 @@ reset:
orr r0,r0,#0xd3
msr cpsr,r0
-#if CONFIG_AT91RM9200
-#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
- bl LED_init
+ bl coloured_LED_init
bl red_LED_on
-#endif
-#ifdef CONFIG_BOOTBINFUNC
-/* code based on entry.S from ATMEL */
-#define AT91C_BASE_CKGR 0xFFFFFC20
-#define CKGR_MOR 0
- /* Get the CKGR Base Address */
- ldr r1, =AT91C_BASE_CKGR
-
-/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
-/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
- ldr r0, =0x0000FF01
- str r0, [r1, #CKGR_MOR]
- /* Add loop to compensate Main Oscillator startup time */
- ldr r0, =0x00000010
-LoopOsc:
- subs r0, r0, #1
- bhi LoopOsc
- /* scratch stack */
- ldr r1, =0x00204000
- /* Insure word alignment */
- bic r1, r1, #3
- /* Init stack SYS */
- mov sp, r1
- /*
- * This does a lot more than just set up the memory, which
- * is why it's called lowlevelinit
- */
- bl lowlevelinit /* in memsetup.S */
- bl icache_enable;
- /* ------------------------------------
- * Read/modify/write CP15 control register
- * -------------------------------------
- * read cp15 control register (cp15 r1) in r0
- * ------------------------------------
- */
- mrc p15, 0, r0, c1, c0, 0
- /* Reset bit :Little Endian end fast bus mode */
- ldr r3, =0xC0000080
- /* Set bit :Asynchronous clock mode, Not Fast Bus */
- ldr r4, =0xC0000000
- bic r0, r0, r3
- orr r0, r0, r4
- /* write r0 in cp15 control register (cp15 r1) */
- mcr p15, 0, r0, c1, c0, 0
-#endif /* CONFIG_BOOTBINFUNC */
+#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
/*
- * relocate exeception table
+ * relocate exception table
*/
ldr r0, =_start
ldr r1, =0x0
@@ -181,19 +133,20 @@ copyex:
bne copyex
#endif
-/* turn off the watchdog */
-#if defined(CONFIG_S3C2400)
-# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
-# define CLKDIVN 0x14800014 /* clock divisor register */
-#elif defined(CONFIG_S3C2410)
-# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
-# define INTSUBMSK 0x4A00001C
-# define CLKDIVN 0x4C000014 /* clock divisor register */
-#endif
-
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
+ /* turn off the watchdog */
+
+# if defined(CONFIG_S3C2400)
+# define pWTCON 0x15300000
+# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+# define CLKDIVN 0x14800014 /* clock divisor register */
+#else
+# define pWTCON 0x53000000
+# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+# define INTSUBMSK 0x4A00001C
+# define CLKDIVN 0x4C000014 /* clock divisor register */
+# endif
+
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
@@ -226,25 +179,7 @@ copyex:
#endif
#ifdef CONFIG_AT91RM9200
-#ifdef CONFIG_BOOTBINFUNC
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-#endif /* CONFIG_BOOTBINFUNC */
-#else
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
@@ -284,27 +219,6 @@ clbss_l:str r2, [r0] /* clear loop... */
cmp r0, r1
ble clbss_l
-#if 0
- /* try doing this stuff after the relocation */
- ldr r0, =pWTCON
- mov r1, #0x0
- str r1, [r0]
-
- /*
- * mask all IRQs by setting all bits in the INTMR - default
- */
- mov r1, #0xffffffff
- ldr r0, =INTMR
- str r1, [r0]
-
- /* FCLK:HCLK:PCLK = 1:2:4 */
- /* default FCLK is 120 MHz ! */
- ldr r0, =CLKDIVN
- mov r1, #3
- str r1, [r0]
- /* END stuff after relocation */
-#endif
-
ldr pc, _start_armboot
_start_armboot: .word start_armboot
generated by cgit v1.1 at 2024-11-07 05:14:28 +0000