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-rw-r--r--board/freescale/mx6qsabreauto/mx6qsabreauto.c231
1 files changed, 196 insertions, 35 deletions
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 2d3ba8b..5376414 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -32,6 +32,9 @@
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
+#ifdef CONFIG_CMD_SATA
+#include <asm/imx-common/sata.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
@@ -42,6 +45,11 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+/*Need more drive strength for SD1 slot on base board*/
+#define USDHC1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
@@ -56,6 +64,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define SPI_PAD_CTRL (PAD_CTL_HYS | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
@@ -90,6 +102,7 @@ static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
@@ -171,6 +184,7 @@ static int port_exp_direction_output(unsigned gpio, int value)
return 0;
}
+#ifdef CONFIG_SYS_USE_EIMNOR
static iomux_v3_cfg_t const eimnor_pads[] = {
MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
@@ -239,12 +253,26 @@ static void setup_iomux_eimnor(void)
eimnor_cs_setup();
}
+#endif
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ /*To avoid pin conflict with NAND, set usdhc1 to 4 pins*/
+ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC1_PAD_CTRL),
+ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC1_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC1_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC1_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC1_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC1_PAD_CTRL),
+
+ /*CD pin*/
+ MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -266,7 +294,12 @@ static void setup_iomux_uart(void)
}
#ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(6, 15)
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR},
};
@@ -292,16 +325,58 @@ int mmc_map_to_kernel_blk(int devno)
int board_mmc_getcd(struct mmc *mmc)
{
- gpio_direction_input(IMX_GPIO_NR(6, 15));
- return !gpio_get_value(IMX_GPIO_NR(6, 15));
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ gpio_direction_input(USDHC1_CD_GPIO);
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ gpio_direction_input(USDHC3_CD_GPIO);
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ }
+
+ return ret;
}
int board_mmc_init(bd_t *bis)
{
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ int i;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC3
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return 0;
+ }
+
+ if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ }
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ return 0;
}
#endif
@@ -376,14 +451,21 @@ int board_phy_config(struct phy_device *phydev)
static void setup_fec(void)
{
+ int ret;
+
if (is_mx6dqp()) {
/*
* select ENET MAC0 TX clock from PLL
*/
imx_iomux_set_gpr_register(5, 9, 1, 1);
- enable_fec_anatop_clock(0, ENET_125MHZ);
+ } else {
+ imx_iomux_set_gpr_register(1, 21, 1, 1);
}
+ ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+ if (ret)
+ printf("Error fec anatop clock settings!\n");
+
setup_iomux_enet();
}
@@ -471,21 +553,21 @@ struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
+ .detect = NULL,
.enable = do_enable_hdmi,
.mode = {
.name = "HDMI",
.refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 39721,
+ .left_margin = 48,
+ .right_margin = 16,
+ .upper_margin = 33,
+ .lower_margin = 10,
+ .hsync_len = 96,
+ .vsync_len = 2,
+ .sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
} } };
size_t display_count = ARRAY_SIZE(displays);
@@ -565,14 +647,34 @@ int overwrite_console(void)
return 1;
}
-int board_early_init_f(void)
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* Steer logic */
+ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_spinor(void)
{
- setup_iomux_uart();
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+ ARRAY_SIZE(ecspi1_pads));
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+ gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
+}
-#ifdef CONFIG_NAND_MXS
- setup_gpmi_nand();
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(3, 19)) : -1;
+}
#endif
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
return 0;
}
@@ -595,35 +697,94 @@ int board_init(void)
#ifdef CONFIG_VIDEO_IPUV3
setup_display();
#endif
- setup_iomux_eimnor();
- return 0;
-}
#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
-}
+ setup_spinor();
#endif
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+
+#ifdef CONFIG_SYS_USE_EIMNOR
+ setup_iomux_eimnor();
+#endif
+ return 0;
+}
+
int power_init_board(void)
{
- struct pmic *p;
+ struct pmic *pfuze;
unsigned int value;
+ int ret;
- p = pfuze_common_init(I2C_PMIC);
- if (!p)
+ pfuze = pfuze_common_init(I2C_PMIC);
+ if (!pfuze)
return -ENODEV;
+ if (is_mx6dqp())
+ ret = pfuze_mode_init(pfuze, APS_APS);
+ else
+ ret = pfuze_mode_init(pfuze, APS_PFM);
+
+ if (ret < 0)
+ return ret;
+
if (is_mx6dqp()) {
+ /* set SW1C staby volatage 1.075V*/
+ pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
+ value &= ~0x3f;
+ value |= 0x1f;
+ pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
+
+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+ pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
+ value &= ~0xc0;
+ value |= 0x40;
+ pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
+
/* set SW2 staby volatage 0.975V*/
- pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+ pmic_reg_read(pfuze, PFUZE100_SW2STBY, &value);
value &= ~0x3f;
value |= 0x17;
- pmic_reg_write(p, PFUZE100_SW2STBY, value);
+ pmic_reg_write(pfuze, PFUZE100_SW2STBY, value);
+
+ /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
+ pmic_reg_read(pfuze, PFUZE100_SW2CONF, &value);
+ value &= ~0xc0;
+ value |= 0x40;
+ pmic_reg_write(pfuze, PFUZE100_SW2CONF, value);
+ } else {
+ /* set SW1AB staby volatage 0.975V*/
+ pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
+ value &= ~0x3f;
+ value |= 0x1b;
+ pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
+
+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
+ value &= ~0xc0;
+ value |= 0x40;
+ pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
+
+ /* set SW1C staby volatage 0.975V*/
+ pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
+ value &= ~0x3f;
+ value |= 0x1b;
+ pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
+
+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+ pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
+ value &= ~0xc0;
+ value |= 0x40;
+ pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
}
- return pfuze_mode_init(p, APS_PFM);
+ return 0;
}
#ifdef CONFIG_CMD_BMODE
generated by cgit v1.1 at 2024-12-23 22:52:05 +0000