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-rw-r--r--board/freescale/mpc8323erdb/mpc8323erdb.c2
-rw-r--r--board/mpc8313erdb/sdram.c3
-rw-r--r--board/mpc832xemds/mpc832xemds.c2
-rw-r--r--board/mpc8349emds/mpc8349emds.c8
-rw-r--r--board/mpc8349itx/mpc8349itx.c3
-rw-r--r--board/mpc8360emds/mpc8360emds.c5
-rw-r--r--board/sbc8349/sbc8349.c5
-rw-r--r--board/tqm834x/tqm834x.c4
8 files changed, 6 insertions, 26 deletions
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index 850d1c3..e738613 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -91,8 +91,6 @@ long int initdram(int board_type)
msize = fixed_sdram();
- puts("\n DDR RAM: ");
-
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
diff --git a/board/mpc8313erdb/sdram.c b/board/mpc8313erdb/sdram.c
index 4b67788..e6e8410 100644
--- a/board/mpc8313erdb/sdram.c
+++ b/board/mpc8313erdb/sdram.c
@@ -112,8 +112,6 @@ long int initdram(int board_type)
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
- puts("Initializing\n");
-
/* DDR SDRAM - Main SODIMM */
msize = fixed_sdram();
@@ -127,7 +125,6 @@ long int initdram(int board_type)
resume_from_sleep();
#endif
- puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return msize;
}
diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c
index 207fcdf..7a45ded 100644
--- a/board/mpc832xemds/mpc832xemds.c
+++ b/board/mpc832xemds/mpc832xemds.c
@@ -114,8 +114,6 @@ long int initdram(int board_type)
msize = fixed_sdram();
- puts("\n DDR RAM: ");
-
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c
index 2ad25ec..39c0916 100644
--- a/board/mpc8349emds/mpc8349emds.c
+++ b/board/mpc8349emds/mpc8349emds.c
@@ -70,8 +70,6 @@ long int initdram (int board_type)
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
- puts("Initializing\n");
-
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
@@ -90,7 +88,7 @@ long int initdram (int board_type)
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
- puts(" DDR RAM: ");
+
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
@@ -191,9 +189,6 @@ void sdram_init(void)
volatile lbus83xx_t *lbc= &immap->lbus;
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
- puts("\n SDRAM on Local Bus: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
@@ -255,7 +250,6 @@ void sdram_init(void)
#else
void sdram_init(void)
{
- puts(" SDRAM on Local Bus is NOT available!\n");
}
#endif
diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c
index 125e6c0..c82f784 100644
--- a/board/mpc8349itx/mpc8349itx.c
+++ b/board/mpc8349itx/mpc8349itx.c
@@ -76,7 +76,7 @@ int fixed_sdram(void)
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
- im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR;
+ im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
im->ddr.sdram_mode =
(0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
im->ddr.sdram_interval =
@@ -162,7 +162,6 @@ long int initdram(int board_type)
ddr_enable_ecc(msize * 1048576);
#endif
- puts(" DDR RAM: ");
/* return total bus RAM size(bytes) */
return msize * 1024 * 1024;
}
diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c
index d6d0f4e..0751c6f 100644
--- a/board/mpc8360emds/mpc8360emds.c
+++ b/board/mpc8360emds/mpc8360emds.c
@@ -149,7 +149,7 @@ long int initdram(int board_type)
* Initialize SDRAM if it is on local bus.
*/
sdram_init();
- puts(" DDR RAM: ");
+
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
@@ -234,8 +234,6 @@ void sdram_init(void)
volatile lbus83xx_t *lbc = &immap->lbus;
uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
- puts("\n SDRAM on Local Bus: ");
- print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
@@ -291,7 +289,6 @@ void sdram_init(void)
#else
void sdram_init(void)
{
- puts("SDRAM on Local Bus is NOT available!\n");
}
#endif
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 4cd447e..86166ea 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -64,8 +64,6 @@ long int initdram (int board_type)
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
- puts("Initializing\n");
-
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
@@ -84,7 +82,6 @@ long int initdram (int board_type)
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
- puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
@@ -130,7 +127,7 @@ int fixed_sdram(void)
#if defined(CONFIG_DDR_2T_TIMING)
| SDRAM_CFG_2T_EN
#endif
- | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+ | SDRAM_CFG_SDRAM_TYPE_DDR1;
#if defined (CONFIG_DDR_32BIT)
/* for 32-bit mode burst length is 8 */
im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index 9c35e22..7d0b055 100644
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -114,7 +114,7 @@ long int initdram (int board_type)
/* enable DDR controller */
im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
SDRAM_CFG_SREN |
- SDRAM_CFG_SDRAM_TYPE_DDR);
+ SDRAM_CFG_SDRAM_TYPE_DDR1);
SYNC;
/* size detection */
@@ -388,7 +388,7 @@ static void set_ddr_config(void) {
/* don't enable DDR controller yet */
im->ddr.sdram_cfg =
SDRAM_CFG_SREN |
- SDRAM_CFG_SDRAM_TYPE_DDR;
+ SDRAM_CFG_SDRAM_TYPE_DDR1;
SYNC;
/* Set SDRAM mode */
generated by cgit v1.1 at 2024-11-03 08:07:08 +0000