diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx53_pcba/Makefile | 47 | ||||
| -rw-r--r-- | board/freescale/mx53_pcba/config.mk | 3 | ||||
| -rw-r--r-- | board/freescale/mx53_pcba/flash_header.S | 125 | ||||
| -rw-r--r-- | board/freescale/mx53_pcba/lowlevel_init.S | 247 | ||||
| -rw-r--r-- | board/freescale/mx53_pcba/mx53_pcba.c | 660 | ||||
| -rw-r--r-- | board/freescale/mx53_pcba/u-boot.lds | 74 |
6 files changed, 1156 insertions, 0 deletions
diff --git a/board/freescale/mx53_pcba/Makefile b/board/freescale/mx53_pcba/Makefile new file mode 100644 index 0000000..8bdf14c --- /dev/null +++ b/board/freescale/mx53_pcba/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx53_pcba.o +SOBJS := lowlevel_init.o flash_header.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx53_pcba/config.mk b/board/freescale/mx53_pcba/config.mk new file mode 100644 index 0000000..34f830a --- /dev/null +++ b/board/freescale/mx53_pcba/config.mk @@ -0,0 +1,3 @@ +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +TEXT_BASE = 0x77800000 diff --git a/board/freescale/mx53_pcba/flash_header.S b/board/freescale/mx53_pcba/flash_header.S new file mode 100644 index 0000000..4622fa2 --- /dev/null +++ b/board/freescale/mx53_pcba/flash_header.S @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/mx53.h> + +#ifdef CONFIG_FLASH_HEADER +#ifndef CONFIG_FLASH_HEADER_OFFSET +# error "Must define the offset of flash header" +#endif + +#define CPU_2_BE_32(l) \ + ((((l) & 0x000000FF) << 24) | \ + (((l) & 0x0000FF00) << 8) | \ + (((l) & 0x00FF0000) >> 8) | \ + (((l) & 0xFF000000) >> 24)) + +#define MXC_DCD_ITEM(i, addr, val) \ +dcd_node_##i: \ + .word CPU_2_BE_32(addr) ; \ + .word CPU_2_BE_32(val) ; \ + +.section ".text.flasheader", "x" + b _start + .org CONFIG_FLASH_HEADER_OFFSET +ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */ +app_code_jump_v: .word _start +reserv1: .word 0x0 +dcd_ptr: .word dcd_hdr +boot_data_ptr: .word boot_data +self_ptr: .word ivt_header +app_code_csf: .word 0x0 +reserv2: .word 0x0 + +boot_data: .word 0x77800000 +image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET +plugin: .word 0x0 + +dcd_hdr: .word 0x40B001D2 /* Tag=0xD2, Len=53*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x04AC01CC /* Tag=0xCC, Len=53*8 + 4, Param=4 */ + +/* DCD */ +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x6f4, 0x00000000) +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x714, 0x00000000) +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000) +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x724, 0x04000000) + +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x72c, 0x00300000) +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x554, 0x00300000) +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x558, 0x00300040) +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x728, 0x00300000) + +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x560, 0x00300000) +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x568, 0x00300040) +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x71c, 0x00300000) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x594, 0x00300000) + +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00300040) +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x718, 0x00300000) +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x584, 0x00300000) +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x57c, 0x00300040) + +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x578, 0x00300000) +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x570, 0x00300000) +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x574, 0x00300000) +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x588, 0x00300000) + +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x6f0, 0x00300000) +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x720, 0x00300000) +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x564, 0x00300040) +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x580, 0x00300040) + +MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x098, 0x00000000) +MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x088, 0x35343535) +MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x090, 0x4f485146) +MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x07c, 0x01350139) + +MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x080, 0x013a0136) +MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x018, 0x00011740) +MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x000, 0xc3190000) +MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x00c, 0x9f515333) + +MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x010, 0xb68e8a63) +MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x014, 0x01ff00db) +MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2) +MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x030, 0x009f0e21) + +MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x008, 0x12373030) +MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x004, 0x4402002d) +MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x00008032) +MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00008033) + +MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x00028031) +MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x092080b0) +MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x04008040) +MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a) + +MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b) +MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x00028039) +MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x09208138) +MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x01c, 0x04008048) + +MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x020, 0x00001800) +MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x040, 0x04b80003) +MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x058, 0x00022227) +MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x01C, 0x00000000) + +MXC_DCD_ITEM(53, IOMUXC_BASE_ADDR + 0x004, 0x00194005) +#endif diff --git a/board/freescale/mx53_pcba/lowlevel_init.S b/board/freescale/mx53_pcba/lowlevel_init.S new file mode 100644 index 0000000..9e4b50f --- /dev/null +++ b/board/freescale/mx53_pcba/lowlevel_init.S @@ -0,0 +1,247 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/mx53.h> + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* explicitly disable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #0x2 + mcr 15, 0, r0, c1, c0, 1 + + /* reconfigure L2 cache aux control reg */ + mov r0, #0xC0 /* tag RAM */ + add r0, r0, #0x4 /* data RAM */ + orr r0, r0, #(1 << 24) /* disable write allocate delay */ + orr r0, r0, #(1 << 23) /* disable write allocate combine */ + orr r0, r0, #(1 << 22) /* disable write allocate */ + + mcr 15, 1, r0, c9, c0, 2 +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x0] + str r1, [r0, #0x4] +.endm /* init_aips */ + +.macro setup_pll pll, freq + ldr r0, =\pll + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] + mov r1, #0x2 + str r1, [r0, #PLL_DP_CONFIG] + + ldr r1, W_DP_OP_\freq + str r1, [r0, #PLL_DP_OP] + str r1, [r0, #PLL_DP_HFS_OP] + + ldr r1, W_DP_MFD_\freq + str r1, [r0, #PLL_DP_MFD] + str r1, [r0, #PLL_DP_HFS_MFD] + + ldr r1, W_DP_MFN_\freq + str r1, [r0, #PLL_DP_MFN] + str r1, [r0, #PLL_DP_HFS_MFN] + + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] +1: ldr r1, [r0, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endm + +.macro init_clock + ldr r0, =ROM_SI_REV + ldr r1, [r0] + cmp r1, #0x20 + + /* For TO2 only, set LDO to 1.3V */ + ldr r0, =0x53fa8000 + ldr r1, =0x00194005 + streq r1, [r0, #0x04] + + ldr r0, CCM_BASE_ADDR_W + + /* Switch ARM to step clock */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + + setup_pll PLL1_BASE_ADDR, 800 + + setup_pll PLL3_BASE_ADDR, 400 + + /* Switch peripheral to PLL3 */ + ldr r0, CCM_BASE_ADDR_W + ldr r1, CCM_VAL_0x00015154 + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, CCM_VAL_0x02888945 + orr r1, r1, #(1 << 16) + str r1, [r0, #CLKCTL_CBCDR] + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ + + /* Switch peripheral to PLL2 */ + ldr r0, CCM_BASE_ADDR_W + ldr r1, CCM_VAL_0x00808145 + orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10) + orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16) + orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19) + str r1, [r0, #CLKCTL_CBCDR] + + ldr r1, CCM_VAL_0x00016154 + str r1, [r0, #CLKCTL_CBCMR] + + /*change uart clk parent to pll2*/ + ldr r1, [r0, #CLKCTL_CSCMR1] + and r1, r1, #0xfcffffff + orr r1, r1, #0x01000000 + str r1, [r0, #CLKCTL_CSCMR1] + + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL3_BASE_ADDR, 216 + + setup_pll PLL4_BASE_ADDR, 455 + + /* Set the platform clock dividers */ + ldr r0, PLATFORM_BASE_ADDR_W + ldr r1, PLATFORM_CLOCK_DIV_W + str r1, [r0, #PLATFORM_ICGC] + + ldr r0, CCM_BASE_ADDR_W + mov r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* Switch ARM back to PLL 1. */ + mov r1, #0x0 + str r1, [r0, #CLKCTL_CCSR] + + /* make uart div=6*/ + ldr r1, [r0, #CLKCTL_CSCDR1] + and r1, r1, #0xffffffc0 + orr r1, r1, #0x0a + str r1, [r0, #CLKCTL_CSCDR1] + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFF003F + str r1, [r0, #CLKCTL_CCGR0] + ldr r1, =0xC00C03C0 + str r1, [r0, #CLKCTL_CCGR1] + ldr r1, =0x033FFC00 + str r1, [r0, #CLKCTL_CCGR2] + ldr r1, =0x0000FFFF + str r1, [r0, #CLKCTL_CCGR3] + ldr r1, =0x3FFC000C + str r1, [r0, #CLKCTL_CCGR4] + ldr r1, =0x00FFF000 + str r1, [r0, #CLKCTL_CCGR5] + ldr r1, =0x0000000F + str r1, [r0, #CLKCTL_CCGR6] + ldr r1, =0x00000000 + str r1, [r0, #CLKCTL_CCGR7] + + mov r1, #0x00000 + str r1, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +.endm + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */ + bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop + nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endif + + /* ARM errata ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1 + + init_l2cc + + init_aips + + init_clock + + mov pc, lr + +/* Board level setting value */ +CCM_BASE_ADDR_W: .word CCM_BASE_ADDR +CCM_VAL_0x00016154: .word 0x00016154 +CCM_VAL_0x00808145: .word 0x00808145 +CCM_VAL_0x00015154: .word 0x00015154 +CCM_VAL_0x02888945: .word 0x02888945 +W_DP_OP_1000: .word DP_OP_1000 +W_DP_MFD_1000: .word DP_MFD_1000 +W_DP_MFN_1000: .word DP_MFN_1000 +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_600: .word DP_OP_600 +W_DP_MFD_600: .word DP_MFD_600 +W_DP_MFN_600: .word DP_MFN_600 +W_DP_OP_400: .word DP_OP_400 +W_DP_MFD_400: .word DP_MFD_400 +W_DP_MFN_400: .word DP_MFN_400 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216 +W_DP_OP_455: .word DP_OP_455 +W_DP_MFD_455: .word DP_MFD_455 +W_DP_MFN_455: .word DP_MFN_455 +PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR +PLATFORM_CLOCK_DIV_W: .word 0x00000124 diff --git a/board/freescale/mx53_pcba/mx53_pcba.c b/board/freescale/mx53_pcba/mx53_pcba.c new file mode 100644 index 0000000..e4a3020 --- /dev/null +++ b/board/freescale/mx53_pcba/mx53_pcba.c @@ -0,0 +1,660 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mx53.h> +#include <asm/arch/mx53_pins.h> +#include <asm/arch/iomux.h> +#include <asm/errno.h> + +#if CONFIG_I2C_MXC +#include <i2c.h> +#endif + +#ifdef CONFIG_CMD_MMC +#include <mmc.h> +#include <fsl_esdhc.h> +#endif + +#ifdef CONFIG_ARCH_MMU +#include <asm/mmu.h> +#include <asm/arch/mmu.h> +#endif + +#ifdef CONFIG_CMD_CLOCK +#include <asm/clock.h> +#endif + +#ifdef CONFIG_ANDROID_RECOVERY +#include "../common/recovery.h" +#include <part.h> +#include <ext2fs.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <ubi_uboot.h> +#include <jffs2/load_kernel.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; +static enum boot_device boot_dev; + +static inline void setup_boot_device(void) +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; + uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; + + switch (bt_mem_ctl) { + case 0x0: + if (bt_mem_type) + boot_dev = ONE_NAND_BOOT; + else + boot_dev = WEIM_NOR_BOOT; + break; + case 0x2: + if (bt_mem_type) + boot_dev = SATA_BOOT; + else + boot_dev = PATA_BOOT; + break; + case 0x3: + if (bt_mem_type) + boot_dev = SPI_NOR_BOOT; + else + boot_dev = I2C_BOOT; + break; + case 0x4: + case 0x5: + boot_dev = SD_BOOT; + break; + case 0x6: + case 0x7: + boot_dev = MMC_BOOT; + break; + case 0x8 ... 0xf: + boot_dev = NAND_BOOT; + break; + default: + boot_dev = UNKNOWN_BOOT; + break; + } +} + +enum boot_device get_boot_device(void) +{ + return boot_dev; +} + +u32 get_board_rev(void) +{ + return system_rev; +} + +static inline void setup_soc_rev(void) +{ + int reg; + + /* Si rev is obtained from ROM */ + reg = __REG(ROM_SI_REV); + + switch (reg) { + case 0x10: + system_rev = 0x53000 | CHIP_REV_1_0; + break; + case 0x20: + system_rev = 0x53000 | CHIP_REV_2_0; + break; + case 0x21: + system_rev = 0x53000 | CHIP_REV_2_1; + break; + default: + system_rev = 0x53000 | CHIP_REV_UNKNOWN; + } +} + +inline int is_soc_rev(int rev) +{ + return (system_rev & 0xFF) - rev; +} + +#ifdef CONFIG_ARCH_MMU +void board_mmu_init(void) +{ + unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000; + unsigned long i; + + /* + * Set the TTB register + */ + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); + + /* + * Set the Domain Access Control Register + */ + i = ARM_ACCESS_DACR_DEFAULT; + asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); + + /* + * First clear all TT entries - ie Set them to Faulting + */ + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + /* Actual Virtual Size Attributes Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ + X_ARM_MMU_SECTION(0x000, 0x000, 0x10, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */ + X_ARM_MMU_SECTION(0x070, 0x070, 0x010, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IRAM */ + X_ARM_MMU_SECTION(0x100, 0x100, 0x040, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SATA */ + X_ARM_MMU_SECTION(0x180, 0x180, 0x100, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IPUv3M */ + X_ARM_MMU_SECTION(0x200, 0x200, 0x200, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* GPU */ + X_ARM_MMU_SECTION(0x400, 0x400, 0x300, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* periperals */ + X_ARM_MMU_SECTION(0x700, 0x700, 0x200, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */ + X_ARM_MMU_SECTION(0x700, 0x900, 0x200, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */ + X_ARM_MMU_SECTION(0xB00, 0xB00, 0x200, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */ + X_ARM_MMU_SECTION(0xB00, 0xD00, 0x200, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */ + X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/ + X_ARM_MMU_SECTION(0xF7F, 0xF7F, 0x040, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */ + X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* iRam */ + + /* Workaround for arm errata #709718 */ + /* Setup PRRR so device is always mapped to non-shared */ + asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/); + i &= (~(3 << 0x10)); + asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/); + + /* Enable MMU */ + MMU_ON(); +} +#endif + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + return 0; +} + +static void setup_uart(void) +{ + /* UART1 RXD */ + mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_ATA_DMACK, 0x1E4); + mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); + + /* UART1 TXD */ + mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_ATA_DIOW, 0x1E4); +} + +#ifdef CONFIG_I2C_MXC +static void setup_i2c(unsigned int module_base) +{ + switch (module_base) { + case I2C1_BASE_ADDR: + /* i2c1 SDA */ + mxc_request_iomux(MX53_PIN_EIM_D28, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH1); + mxc_iomux_set_pad(MX53_PIN_EIM_D28, PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + /* i2c1 SCL */ + mxc_request_iomux(MX53_PIN_EIM_D21, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH1); + mxc_iomux_set_pad(MX53_PIN_EIM_D21, PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + break; + case I2C2_BASE_ADDR: + /* i2c2 SDA */ + mxc_request_iomux(MX53_PIN_KEY_ROW3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + + /* i2c2 SCL */ + mxc_request_iomux(MX53_PIN_KEY_COL3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_COL3, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + + break; + case I2C3_BASE_ADDR: + /* GPIO_3 for I2C3_SCL */ + mxc_request_iomux(MX53_PIN_GPIO_5, + IOMUX_CONFIG_ALT6 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C3_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH1); + mxc_iomux_set_pad(MX53_PIN_GPIO_5, + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_360K_PD | + PAD_CTL_HYS_ENABLE); + /* GPIO_16 for I2C3_SDA */ + mxc_request_iomux(MX53_PIN_GPIO_6, + IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C3_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH1); + mxc_iomux_set_pad(MX53_PIN_GPIO_6, + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_360K_PD | + PAD_CTL_HYS_ENABLE); + /* No device is connected via I2C3 in EVK and ARM2 */ + break; + default: + printf("Invalid I2C base: 0x%x\n", module_base); + break; + } +} + +void setup_pmic_voltages(void) +{ + int value; + unsigned char buf[4] = { 0 }; + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (!i2c_probe(0x8)) { + if (i2c_read(0x8, 24, 1, &buf[0], 3)) { + printf("%s:i2c_read:error\n", __func__); + } + /* increase VDDGP as 1.25V for 1GHZ on SW1 */ + buf[2] = 0x30; + if (i2c_write(0x8, 24, 1, buf, 3)) { + printf("%s:i2c_write:error\n", __func__); + } + } else + printf("Error: Dont't found mc34708 on board.\n"); +} + +#endif + +#ifdef CONFIG_CMD_MMC + +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC3_BASE_ADDR, 1, 1}, +}; + +#ifdef CONFIG_DYNAMIC_MMC_DEVNO +int get_mmc_env_devno() +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + return (soc_sbmr & 0x00300000) ? 1 : 0; +} +#endif + +#ifdef CONFIG_EMMC_DDR_PORT_DETECT +int detect_mmc_emmc_ddr_port(struct fsl_esdhc_cfg *cfg) +{ + return (MMC_SDHC3_BASE_ADDR == cfg->esdhc_base) ? 1 : 0; +} +#endif + +int esdhc_gpio_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0); + + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4); + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4); + break; + case 1: + mxc_request_iomux(MX53_PIN_ATA_RESET_B, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_IORDY, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA8, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA9, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA10, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA11, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA0, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA1, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA2, + IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_ATA_DATA3, + IOMUX_CONFIG_ALT4); + + mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 0x1E4); + mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 0xD4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4); + + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + + return status; +} + +int board_mmc_init(bd_t *bis) +{ + if (!esdhc_gpio_init(bis)) + return 0; + else + return -1; +} + +#endif + +int board_init(void) +{ +#ifdef CONFIG_MFG +/* MFG firmware need reset usb to avoid host crash firstly */ +#define USBCMD 0x140 + int val = readl(OTG_BASE_ADDR + USBCMD); + val &= ~0x1; /*RS bit*/ + writel(val, OTG_BASE_ADDR + USBCMD); +#endif + setup_boot_device(); + setup_soc_rev(); + + gd->bd->bi_arch_number = MACH_TYPE_MX53_PCBA;/* board id for linux */ + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + setup_uart(); + +#ifdef CONFIG_I2C_MXC + setup_i2c(CONFIG_SYS_I2C_PORT); + /* Increase VDDGP voltage */ + setup_pmic_voltages(); + /* Switch to 1GHZ */ + clk_config(CONFIG_REF_CLK_FREQ, 1000, CPU_CLK); +#endif + + return 0; +} + + +#ifdef CONFIG_ANDROID_RECOVERY +struct reco_envs supported_reco_envs[BOOT_DEV_NUM] = { + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC, + .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC, + }, + { + .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC, + .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC, + }, + { + .cmd = NULL, + .args = NULL, + }, +}; + +int check_recovery_cmd_file(void) +{ + disk_partition_t info; + ulong part_length; + int filelen = 0; + char *env; + int i; + + /* For test only */ + /* When detecting android_recovery_switch, + * enter recovery mode directly */ + env = getenv("android_recovery_switch"); + if (!strcmp(env, "1")) { + printf("Env recovery detected!\nEnter recovery mode!\n"); + return 1; + } + + printf("Checking for recovery command file...\n"); + switch (get_boot_device()) { + case MMC_BOOT: + case SD_BOOT: + { + for (i = 0; i < 2; i++) { + block_dev_desc_t *dev_desc = NULL; + struct mmc *mmc = find_mmc_device(i); + + dev_desc = get_dev("mmc", i); + + if (NULL == dev_desc) { + printf("** Block device MMC %d not supported\n", i); + continue; + } + + mmc_init(mmc); + + if (get_partition_info(dev_desc, + CONFIG_ANDROID_CACHE_PARTITION_MMC, + &info)) { + printf("** Bad partition %d **\n", + CONFIG_ANDROID_CACHE_PARTITION_MMC); + continue; + } + + part_length = ext2fs_set_blk_dev(dev_desc, + CONFIG_ANDROID_CACHE_PARTITION_MMC); + if (part_length == 0) { + printf("** Bad partition - mmc %d:%d **\n", i, + CONFIG_ANDROID_CACHE_PARTITION_MMC); + ext2fs_close(); + continue; + } + + if (!ext2fs_mount(part_length)) { + printf("** Bad ext2 partition or " + "disk - mmc i:%d **\n", + i, CONFIG_ANDROID_CACHE_PARTITION_MMC); + ext2fs_close(); + continue; + } + + filelen = ext2fs_open(CONFIG_ANDROID_RECOVERY_CMD_FILE); + + ext2fs_close(); + break; + } + } + break; + case NAND_BOOT: + return 0; + break; + case SPI_NOR_BOOT: + return 0; + break; + case UNKNOWN_BOOT: + default: + return 0; + break; + } + + return (filelen > 0) ? 1 : 0; + +} +#endif + +int board_late_init(void) +{ + return 0; +} + +int checkboard(void) +{ + printf("Board: MX53-PCBA "); + + printf("Boot Reason: ["); + + switch (__REG(SRC_BASE_ADDR + 0x8)) { + case 0x0001: + printf("POR"); + break; + case 0x0009: + printf("RST"); + break; + case 0x0010: + case 0x0011: + printf("WDOG"); + break; + default: + printf("unknown"); + } + printf("]\n"); + + printf("Boot Device: "); + switch (get_boot_device()) { + case WEIM_NOR_BOOT: + printf("NOR\n"); + break; + case ONE_NAND_BOOT: + printf("ONE NAND\n"); + break; + case PATA_BOOT: + printf("PATA\n"); + break; + case SATA_BOOT: + printf("SATA\n"); + break; + case I2C_BOOT: + printf("I2C\n"); + break; + case SPI_NOR_BOOT: + printf("SPI NOR\n"); + break; + case SD_BOOT: + printf("SD\n"); + break; + case MMC_BOOT: + printf("MMC\n"); + break; + case NAND_BOOT: + printf("NAND\n"); + break; + case UNKNOWN_BOOT: + default: + printf("UNKNOWN\n"); + break; + } + return 0; +} diff --git a/board/freescale/mx53_pcba/u-boot.lds b/board/freescale/mx53_pcba/u-boot.lds new file mode 100644 index 0000000..467f585 --- /dev/null +++ b/board/freescale/mx53_pcba/u-boot.lds @@ -0,0 +1,74 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * (C) Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + board/freescale/mx53_pcba/flash_header.o (.text.flasheader) + cpu/arm_cortexa8/start.o + board/freescale/mx53_pcba/libmx53_pcba.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + drivers/mmc/libmmc.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _end_of_copy = .; /* end_of ROM copy code here */ + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} |