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-rw-r--r--board/amcc/acadia/pll.c28
-rw-r--r--board/mpl/mip405/init.S3
-rw-r--r--board/mpl/mip405/mip405.c1
-rw-r--r--board/mpl/pip405/init.S3
-rw-r--r--board/sc3/sc3.c10
5 files changed, 22 insertions, 23 deletions
diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c
index 452961d..6327d6c 100644
--- a/board/amcc/acadia/pll.c
+++ b/board/amcc/acadia/pll.c
@@ -53,9 +53,9 @@ void board_pll_init_f(void)
/* Initialize PLL */
mtcpr(CPR0_PLLC, 0x0000033c);
mtcpr(CPR0_PLLD, 0x0c010200);
- mtcpr(CPC0_PRIMAD, 0x04060c0c);
- mtcpr(CPC0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
- mtcpr(CPR0_CLKUP, 0x40000000);
+ mtcpr(CPR0_PRIMAD, 0x04060c0c);
+ mtcpr(CPR0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(CPR0_CLKUPD, 0x40000000);
}
#elif defined(PLLMR0_266_160_80)
@@ -85,10 +85,10 @@ void board_pll_init_f(void)
/* Initialize PLL */
mtcpr(CPR0_PLLC, 0x20000238);
mtcpr(CPR0_PLLD, 0x03010400);
- mtcpr(CPC0_PRIMAD, 0x03050a0a);
- mtcpr(CPC0_PERC0, 0x00000000);
- mtcpr(CPC0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
- mtcpr(CPC0_PERD1, 0x07323200);
+ mtcpr(CPR0_PRIMAD, 0x03050a0a);
+ mtcpr(CPR0_PERC0, 0x00000000);
+ mtcpr(CPR0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(CPR0_PERD1, 0x07323200);
mtcpr(CPR0_CLKUP, 0x40000000);
}
@@ -119,9 +119,9 @@ void board_pll_init_f(void)
/* Initialize PLL */
mtcpr(CPR0_PLLC, 0x0000033C);
mtcpr(CPR0_PLLD, 0x0a010000);
- mtcpr(CPC0_PRIMAD, 0x02040808);
- mtcpr(CPC0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
- mtcpr(CPC0_PERD1, 0xA6A60300);
+ mtcpr(CPR0_PRIMAD, 0x02040808);
+ mtcpr(CPR0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(CPR0_PERD1, 0xA6A60300);
mtcpr(CPR0_CLKUP, 0x40000000);
}
@@ -145,9 +145,9 @@ void board_pll_init_f(void)
/* Initialize PLL */
mtcpr(CPR0_PLLC, 0x000003BC);
mtcpr(CPR0_PLLD, 0x06060600);
- mtcpr(CPC0_PRIMAD, 0x02020004);
- mtcpr(CPC0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
- mtcpr(CPC0_PERD1, 0xC8C81600);
+ mtcpr(CPR0_PRIMAD, 0x02020004);
+ mtcpr(CPR0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(CPR0_PERD1, 0xC8C81600);
mtcpr(CPR0_CLKUP, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
@@ -172,7 +172,7 @@ unsigned long get_tbclk(void)
/*
* Read CPR_PRIMAD register
*/
- mfcpr(CPC0_PRIMAD, cpr_primad);
+ mfcpr(CPR0_PRIMAD, cpr_primad);
/*
* Determine CPU clock frequency
diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S
index 67988ba..39a1d68 100644
--- a/board/mpl/mip405/init.S
+++ b/board/mpl/mip405/init.S
@@ -39,8 +39,6 @@
* Bank 6 - not used
* Bank 7 - PLD Register
*-----------------------------------------------------------------------------*/
-#include <asm/ppc4xx.h>
-
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <configs/MIP405.h>
@@ -49,6 +47,7 @@
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
#include "mip405.h"
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 3db06e7..e93d994 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -65,6 +65,7 @@
#include <common.h>
#include "mip405.h"
#include <asm/processor.h>
+#include <asm/ppc4xx.h>
#include <asm/ppc4xx-i2c.h>
#include <miiphy.h>
#include "../common/common_util.h"
diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S
index e82be89..b77517f 100644
--- a/board/mpl/pip405/init.S
+++ b/board/mpl/pip405/init.S
@@ -39,8 +39,6 @@
* Bank 6 - used to switch on the 12V for the Multipurpose socket
* Bank 7 - Config Register
*-----------------------------------------------------------------------------*/
-#include <asm/ppc4xx.h>
-
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <configs/PIP405.h>
@@ -49,6 +47,7 @@
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
#include "pip405.h"
.globl ext_bus_cntlr_init
diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c
index 63927f7..f148ad6 100644
--- a/board/sc3/sc3.c
+++ b/board/sc3/sc3.c
@@ -331,16 +331,16 @@ int board_early_init_f (void)
}
/* Code decompression disabled */
- mtdcr (KIAR, KCONF);
- mtdcr (KIDR, 0x2B);
+ mtdcr (DCP0_CFGADDR, KCONF);
+ mtdcr (DCP0_CFGDATA, 0x2B);
/* CPC0_ER: enable sleep mode of (currently) unused components */
/* CPC0_FR: force unused components into sleep mode */
- mtdcr (CPMER, 0x3F800000);
- mtdcr (CPMFR, 0x14000000);
+ mtdcr (CPC0_ER, 0x3F800000);
+ mtdcr (CPC0_FR, 0x14000000);
/* set PLB priority */
- mtdcr (0x87, 0x08000000);
+ mtdcr (PLB0_ACR, 0x08000000);
/* --------------- DMA stuff ------------------------------------- */
mtdcr (0x126, 0x49200000);