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-rw-r--r--board/mpc8349emds/Makefile2
-rw-r--r--board/mpc8349emds/mpc8349emds.c40
-rw-r--r--board/mpc8349emds/pci.c53
-rw-r--r--board/mpc8349itx/Makefile48
-rw-r--r--board/mpc8349itx/config.mk33
-rw-r--r--board/mpc8349itx/mpc8349itx.c477
-rw-r--r--board/mpc8349itx/pci.c357
-rw-r--r--board/mpc8349itx/u-boot.lds120
-rw-r--r--board/mpc8360emds/Makefile50
-rw-r--r--board/mpc8360emds/config.mk28
-rw-r--r--board/mpc8360emds/mpc8360emds.c657
-rw-r--r--board/mpc8360emds/pci.c313
-rw-r--r--board/mpc8360emds/u-boot.lds123
-rw-r--r--board/tqm834x/pci.c18
-rw-r--r--board/tqm834x/tqm834x.c4
15 files changed, 2289 insertions, 34 deletions
diff --git a/board/mpc8349emds/Makefile b/board/mpc8349emds/Makefile
index acc9544..5ec7a87 100644
--- a/board/mpc8349emds/Makefile
+++ b/board/mpc8349emds/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o
+COBJS := $(BOARD).o pci.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c
index b5ccb53..873bdd0 100644
--- a/board/mpc8349emds/mpc8349emds.c
+++ b/board/mpc8349emds/mpc8349emds.c
@@ -33,6 +33,10 @@
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#endif
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
int fixed_sdram(void);
void sdram_init(void);
@@ -59,7 +63,7 @@ int board_early_init_f (void)
long int initdram (int board_type)
{
- volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
@@ -96,7 +100,7 @@ long int initdram (int board_type)
************************************************************************/
int fixed_sdram(void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
@@ -167,8 +171,8 @@ int checkboard (void)
void sdram_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile lbus8349_t *lbc= &immap->lbus;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile lbus83xx_t *lbc= &immap->lbus;
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
puts("\n SDRAM on Local Bus: ");
@@ -245,8 +249,8 @@ void sdram_init(void)
*/
void ecc_print_status(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile ddr8349_t *ddr = &immap->ddr;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ddr83xx_t *ddr = &immap->ddr;
printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
@@ -320,8 +324,8 @@ void ecc_print_status(void)
int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile ddr8349_t *ddr = &immap->ddr;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ddr83xx_t *ddr = &immap->ddr;
volatile u32 val;
u64 *addr, count, val64;
register u64 *i;
@@ -564,3 +568,23 @@ U_BOOT_CMD(
" - re-inits memory"
);
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
+}
+#endif
diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c
index 63e4405..bb60e73 100644
--- a/board/mpc8349emds/pci.c
+++ b/board/mpc8349emds/pci.c
@@ -68,12 +68,13 @@ static struct pci_controller pci_hose[] = {
void
pib_init(void)
{
- u8 val8;
+ u8 val8, orig_i2c_bus;
/*
* Assign PIB PMC slot to desired PCI bus
*/
- mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ /* Switch temporarily to I2C bus #2 */
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
val8 = 0;
i2c_write(0x23, 0x6, 1, &val8, 1);
@@ -118,6 +119,8 @@ pib_init(void)
printf("PCI1: 32-bit on PMC1, PMC2\n");
printf("PCI2: 32-bit on PMC3\n");
#endif
+ /* Reset to original I2C bus */
+ i2c_set_bus_num(orig_i2c_bus);
}
/**************************************************************************
@@ -130,18 +133,18 @@ void
pci_init_board(void)
{
volatile immap_t * immr;
- volatile clk8349_t * clk;
- volatile law8349_t * pci_law;
- volatile pot8349_t * pci_pot;
- volatile pcictrl8349_t * pci_ctrl;
- volatile pciconf8349_t * pci_conf;
+ volatile clk83xx_t * clk;
+ volatile law83xx_t * pci_law;
+ volatile pot83xx_t * pci_pot;
+ volatile pcictrl83xx_t * pci_ctrl;
+ volatile pciconf83xx_t * pci_conf;
u16 reg16;
u32 reg32;
u32 dev;
struct pci_controller * hose;
- immr = (immap_t *)CFG_IMMRBAR;
- clk = (clk8349_t *)&immr->clk;
+ immr = (immap_t *)CFG_IMMR;
+ clk = (clk83xx_t *)&immr->clk;
pci_law = immr->sysconf.pcilaw;
pci_pot = immr->ios.pot;
pci_ctrl = immr->pci_ctrl;
@@ -254,8 +257,8 @@ pci_init_board(void)
hose->region_count = 4;
pci_setup_indirect(hose,
- (CFG_IMMRBAR+0x8300),
- (CFG_IMMRBAR+0x8304));
+ (CFG_IMMR+0x8300),
+ (CFG_IMMR+0x8304));
pci_register_hose(hose);
@@ -350,8 +353,8 @@ pci_init_board(void)
hose->region_count = 4;
pci_setup_indirect(hose,
- (CFG_IMMRBAR+0x8380),
- (CFG_IMMRBAR+0x8384));
+ (CFG_IMMR+0x8380),
+ (CFG_IMMR+0x8384));
pci_register_hose(hose);
@@ -379,4 +382,26 @@ pci_init_board(void)
}
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
+ if (p != NULL) {
+ p[0] = pci_hose[0].first_busno;
+ p[1] = pci_hose[0].last_busno;
+ }
+
+#ifdef CONFIG_MPC83XX_PCI2
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
+ if (p != NULL) {
+ p[0] = pci_hose[1].first_busno;
+ p[1] = pci_hose[1].last_busno;
+ }
+#endif
+}
+#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_PCI */
diff --git a/board/mpc8349itx/Makefile b/board/mpc8349itx/Makefile
new file mode 100644
index 0000000..31bcdb8
--- /dev/null
+++ b/board/mpc8349itx/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o pci.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mpc8349itx/config.mk b/board/mpc8349itx/config.mk
new file mode 100644
index 0000000..2e11311
--- /dev/null
+++ b/board/mpc8349itx/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC8349ITX
+#
+
+TEXT_BASE = 0xFEF00000
+
+ifneq ($(OBJTREE),$(SRCTREE))
+# We are building u-boot in a separate directory, use generated
+# .lds script from OBJTREE directory.
+LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds
+endif
diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c
new file mode 100644
index 0000000..4838e70
--- /dev/null
+++ b/board/mpc8349itx/mpc8349itx.c
@@ -0,0 +1,477 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+
+#ifdef CONFIG_PCI
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#endif
+
+#ifdef CONFIG_SPD_EEPROM
+#include <spd_sdram.h>
+#else
+#include <asm/mmu.h>
+#endif
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+#ifndef CONFIG_SPD_EEPROM
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *) CFG_IMMR;
+ u32 ddr_size; /* The size of RAM, in bytes */
+ u32 ddr_size_log2 = 0;
+
+ for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
+ if (ddr_size & 1) {
+ return -1;
+ }
+ ddr_size_log2++;
+ }
+
+ im->sysconf.ddrlaw[0].ar =
+ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+ im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff;
+
+ /* Only one CS0 for DDR */
+ im->ddr.csbnds[0].csbnds = 0x0000000f;
+ im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+
+ debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
+ debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
+
+ debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
+ debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
+
+ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
+ im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR;
+ im->ddr.sdram_mode =
+ (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
+ im->ddr.sdram_interval =
+ (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
+ SDRAM_INTERVAL_BSTOPRE_SHIFT);
+ im->ddr.sdram_clk_cntl =
+ DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
+
+ udelay(200);
+
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+ debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
+ debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
+ debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
+ debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
+ debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
+
+ return CFG_DDR_SIZE;
+}
+#endif
+
+#ifdef CONFIG_PCI
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
+ {
+ PCI_ANY_ID,
+ PCI_ANY_ID,
+ PCI_ANY_ID,
+ PCI_ANY_ID,
+ 0x0f,
+ PCI_ANY_ID,
+ pci_cfgfunc_config_device,
+ {
+ PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
+ },
+ {}
+}
+#endif
+
+volatile static struct pci_controller hose[] = {
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc83xxmitx_config_table,
+#endif
+ },
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc83xxmitx_config_table,
+#endif
+ }
+};
+#endif /* CONFIG_PCI */
+
+/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. */
+
+void sdram_init(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile lbus83xx_t *lbc = &immap->lbus;
+
+#if defined(CFG_BR2_PRELIM) \
+ && defined(CFG_OR2_PRELIM) \
+ && defined(CFG_LBLAWBAR2_PRELIM) \
+ && defined(CFG_LBLAWAR2_PRELIM) \
+ && !defined(CONFIG_COMPACT_FLASH)
+
+ uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
+
+ puts("\n SDRAM on Local Bus: ");
+ print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+ */
+
+ /*setup mtrpt, lsrt and lbcr for LB bus */
+ lbc->lbcr = CFG_LBC_LBCR;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->lsrt = CFG_LBC_LSRT;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller Machine Mode register.
+ */
+ lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+
+ lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733; precharge all the banks */
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_2; /*0x48636733; auto refresh */
+ asm("sync");
+ *sdram_addr = 0xff; /*1 time*/
+ udelay(100);
+ *sdram_addr = 0xff; /*2 times*/
+ udelay(100);
+ *sdram_addr = 0xff; /*3 times*/
+ udelay(100);
+ *sdram_addr = 0xff; /*4 times*/
+ udelay(100);
+ *sdram_addr = 0xff; /*5 times*/
+ udelay(100);
+ *sdram_addr = 0xff; /*6 times*/
+ udelay(100);
+ *sdram_addr = 0xff; /*7 times*/
+ udelay(100);
+ *sdram_addr = 0xff; /*8 times*/
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation */
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation */
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+#else
+ puts("SDRAM on Local Bus is NOT available!\n");
+
+#ifdef CFG_BR2_PRELIM
+ lbc->bank[2].br = CFG_BR2_PRELIM;
+ lbc->bank[2].or = CFG_OR2_PRELIM;
+#endif
+
+#ifdef CFG_BR3_PRELIM
+ lbc->bank[3].br = CFG_BR3_PRELIM;
+ lbc->bank[3].or = CFG_OR3_PRELIM;
+#endif
+#endif
+}
+
+long int initdram(int board_type)
+{
+ volatile immap_t *im = (immap_t *) CFG_IMMR;
+ u32 msize = 0;
+#ifdef CONFIG_DDR_ECC
+ volatile ddr83xx_t *ddr = &im->ddr;
+#endif
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+#ifdef CONFIG_SPD_EEPROM
+ msize = spd_sdram();
+#else
+ msize = fixed_sdram();
+#endif
+
+#ifdef CONFIG_DDR_ECC
+ if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
+ /* Unlike every other board, on the 83xx spd_sdram() returns
+ megabytes instead of just bytes. That's why we need to
+ multiple by 1MB when calling ddr_enable_ecc(). */
+ ddr_enable_ecc(msize * 1048576);
+#endif
+
+ /*
+ * Initialize SDRAM if it is on local bus.
+ */
+ sdram_init();
+ puts(" DDR RAM: ");
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+ puts("Board: Freescale MPC8349E-mITX\n");
+
+ return 0;
+}
+
+/*
+ * Implement a work-around for a hardware problem with compact
+ * flash.
+ *
+ * Program the UPM if compact flash is enabled.
+ */
+int misc_init_f(void)
+{
+ volatile u32 *vsc7385_cpuctrl;
+
+ /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
+ default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
+ means it is 0 when the IRQ is not active. This makes the wire-AND
+ logic always assert IRQ7 to CPU even if there is no request from the
+ switch. Since the compact flash and the switch share the same IRQ,
+ the Linux kernel will think that the compact flash is requesting irq
+ and get stuck when it tries to clear the IRQ. Thus we need to set
+ the L2_IRQ0 and L2_IRQ1 to active low.
+
+ The following code sets the L1_IRQ and L2_IRQ polarity to active low.
+ Without this code, compact flash will not work in Linux because
+ unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
+ don't enable compact flash for U-Boot.
+ */
+
+ vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0);
+ *vsc7385_cpuctrl |= 0x0c;
+
+#ifdef CONFIG_COMPACT_FLASH
+ /* UPM Table Configuration Code */
+ static uint UPMATable[] = {
+ 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
+ 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+ 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
+ 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
+ };
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile lbus83xx_t *lbus = &immap->lbus;
+
+ lbus->bank[3].br = CFG_BR3_PRELIM;
+ lbus->bank[3].or = CFG_OR3_PRELIM;
+
+ /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
+ GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
+ */
+ lbus->mamr = 0x08404440;
+
+ upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
+
+ puts("UPMA: Configured for compact flash\n");
+#endif
+
+ return 0;
+}
+
+/*
+ * Make sure the EEPROM has the HRCW correctly programmed.
+ * Make sure the RTC is correctly programmed.
+ *
+ * The MPC8349E-mITX can be configured to load the HRCW from
+ * EEPROM instead of flash. This is controlled via jumpers
+ * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
+ * jumpered), but if they're set to 001 or 010, then the HRCW is
+ * read from the "I2C EEPROM".
+ *
+ * This function makes sure that the I2C EEPROM is programmed
+ * correctly.
+ */
+int misc_init_r(void)
+{
+ int rc = 0;
+
+#ifdef CONFIG_HARD_I2C
+
+ unsigned int orig_bus = i2c_get_bus_num();;
+ u8 i2c_data;
+
+#ifdef CFG_I2C_RTC_ADDR
+ u8 ds1339_data[17];
+#endif
+
+#ifdef CFG_I2C_EEPROM_ADDR
+ static u8 eeprom_data[] = /* HRCW data */
+ {
+ 0xaa, 0x55, 0xaa,
+ 0x7c, 0x02, 0x40, 0x05, 0x04, 0x00, 0x00,
+ 0x7c, 0x02, 0x41, 0xb4, 0x60, 0xa0, 0x00,
+ };
+
+ u8 data[sizeof(eeprom_data)];
+#endif
+
+ printf("Board revision: ");
+ i2c_set_bus_num(1);
+ if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+ printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
+ else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+ printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
+ else {
+ printf("Unknown\n");
+ rc = 1;
+ }
+
+#ifdef CFG_I2C_EEPROM_ADDR
+ i2c_set_bus_num(0);
+
+ if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
+ if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
+ if (i2c_write
+ (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
+ sizeof(eeprom_data)) != 0) {
+ puts("Failure writing the HRCW to EEPROM via I2C.\n");
+ rc = 1;
+ }
+ }
+ } else {
+ puts("Failure reading the HRCW from EEPROM via I2C.\n");
+ rc = 1;
+ }
+#endif
+
+#ifdef CFG_I2C_RTC_ADDR
+ i2c_set_bus_num(1);
+
+ if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
+ == 0) {
+
+ /* Work-around for MPC8349E-mITX bug #13601.
+ If the RTC does not contain valid register values, the DS1339
+ Linux driver will not work.
+ */
+
+ /* Make sure status register bits 6-2 are zero */
+ ds1339_data[0x0f] &= ~0x7c;
+
+ /* Check for a valid day register value */
+ ds1339_data[0x03] &= ~0xf8;
+ if (ds1339_data[0x03] == 0) {
+ ds1339_data[0x03] = 1;
+ }
+
+ /* Check for a valid date register value */
+ ds1339_data[0x04] &= ~0xc0;
+ if ((ds1339_data[0x04] == 0) ||
+ ((ds1339_data[0x04] & 0x0f) > 9) ||
+ (ds1339_data[0x04] >= 0x32)) {
+ ds1339_data[0x04] = 1;
+ }
+
+ /* Check for a valid month register value */
+ ds1339_data[0x05] &= ~0x60;
+
+ if ((ds1339_data[0x05] == 0) ||
+ ((ds1339_data[0x05] & 0x0f) > 9) ||
+ ((ds1339_data[0x05] >= 0x13)
+ && (ds1339_data[0x05] <= 0x19))) {
+ ds1339_data[0x05] = 1;
+ }
+
+ /* Enable Oscillator and rate select */
+ ds1339_data[0x0e] = 0x1c;
+
+ /* Work-around for MPC8349E-mITX bug #13330.
+ Ensure that the RTC control register contains the value 0x1c.
+ This affects SATA performance.
+ */
+
+ if (i2c_write
+ (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data,
+ sizeof(ds1339_data))) {
+ puts("Failure writing to the RTC via I2C.\n");
+ rc = 1;
+ }
+ } else {
+ puts("Failure reading from the RTC via I2C.\n");
+ rc = 1;
+ }
+#endif
+
+ i2c_set_bus_num(orig_bus);
+#endif
+
+ return rc;
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
+}
+#endif
diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c
new file mode 100644
index 0000000..e81ad27
--- /dev/null
+++ b/board/mpc8349itx/pci.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_PCI
+
+#include <asm/mmu.h>
+#include <asm/global_data.h>
+#include <pci.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc8349itx_config_table[] = {
+ {
+ PCI_ANY_ID,
+ PCI_ANY_ID,
+ PCI_ANY_ID,
+ PCI_ANY_ID,
+ PCI_IDSEL_NUMBER,
+ PCI_ANY_ID,
+ pci_cfgfunc_config_device,
+ {
+ PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
+ },
+ {}
+};
+#endif
+
+static struct pci_controller pci_hose[] = {
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc8349itx_config_table,
+#endif
+ },
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc8349itx_config_table,
+#endif
+ }
+};
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not currently supported
+ *
+ */
+void pci_init_board(void)
+{
+ volatile immap_t *immr;
+ volatile clk83xx_t *clk;
+ volatile law83xx_t *pci_law;
+ volatile pot83xx_t *pci_pot;
+ volatile pcictrl83xx_t *pci_ctrl;
+ volatile pciconf83xx_t *pci_conf;
+ u8 reg8;
+ u16 reg16;
+ u32 reg32;
+ u32 dev;
+ struct pci_controller *hose;
+
+ immr = (immap_t *) CFG_IMMR;
+ clk = (clk83xx_t *) & immr->clk;
+ pci_law = immr->sysconf.pcilaw;
+ pci_pot = immr->ios.pot;
+ pci_ctrl = immr->pci_ctrl;
+ pci_conf = immr->pci_conf;
+
+ hose = &pci_hose[0];
+
+ /*
+ * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
+ */
+
+ reg32 = clk->occr;
+ udelay(2000);
+
+#ifdef CONFIG_HARD_I2C
+ i2c_set_bus_num(1);
+ /* Read the PCI_M66EN jumper setting */
+ if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
+ (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
+ if (reg8 & I2C_8574_PCI66)
+ clk->occr = 0xff000000; /* 66 MHz PCI */
+ else
+ clk->occr = 0xff600001; /* 33 MHz PCI */
+ } else {
+ clk->occr = 0xff600001; /* 33 MHz PCI */
+ }
+#else
+ clk->occr = 0xff000000; /* 66 MHz PCI */
+#endif
+
+ udelay(2000);
+
+ /*
+ * Release PCI RST Output signal
+ */
+ pci_ctrl[0].gcr = 0;
+ udelay(2000);
+ pci_ctrl[0].gcr = 1;
+
+#ifdef CONFIG_MPC83XX_PCI2
+ pci_ctrl[1].gcr = 0;
+ udelay(2000);
+ pci_ctrl[1].gcr = 1;
+#endif
+
+ /* We need to wait at least a 1sec based on PCI specs */
+ {
+ int i;
+
+ for (i = 0; i < 1000; i++)
+ udelay(1000);
+ }
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+ pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
+
+ /*
+ * Configure PCI Outbound Translation Windows
+ */
+
+ /* PCI1 mem space - prefetch */
+ pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;
+
+ /* PCI1 IO space */
+ pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
+
+ /* PCI1 mmio - non-prefetch mem space */
+ pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
+
+ /*
+ * Configure PCI Inbound Translation Windows
+ */
+
+ /* we need RAM mapped to PCI space for the devices to
+ * access main memory */
+ pci_ctrl[0].pitar1 = 0x0;
+ pci_ctrl[0].pibar1 = 0x0;
+ pci_ctrl[0].piebar1 = 0x0;
+ pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+ PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* PCI memory prefetch space */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MMIO_BASE,
+ CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+
+ /* System memory space */
+ pci_set_region(hose->regions + 3,
+ CONFIG_PCI_SYS_MEM_BUS,
+ CONFIG_PCI_SYS_MEM_PHYS,
+ gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ hose->region_count = 4;
+
+ pci_setup_indirect(hose,
+ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+
+ pci_register_hose(hose);
+
+ /*
+ * Write to Command register
+ */
+ reg16 = 0xff;
+ dev = PCI_BDF(hose->first_busno, 0, 0);
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
+#endif
+ /*
+ * Hose scan.
+ */
+ hose->last_busno = pci_hose_scan(hose);
+
+#ifdef CONFIG_MPC83XX_PCI2
+ hose = &pci_hose[1];
+
+ /*
+ * Configure PCI Outbound Translation Windows
+ */
+
+ /* PCI2 mem space - prefetch */
+ pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M;
+
+ /* PCI2 IO space */
+ pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;
+
+ /* PCI2 mmio - non-prefetch mem space */
+ pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;
+
+ /*
+ * Configure PCI Inbound Translation Windows
+ */
+
+ /* we need RAM mapped to PCI space for the devices to
+ * access main memory */
+ pci_ctrl[1].pitar1 = 0x0;
+ pci_ctrl[1].pibar1 = 0x0;
+ pci_ctrl[1].piebar1 = 0x0;
+ pci_ctrl[1].piwar1 =
+ PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
+ (__ilog2(gd->ram_size) - 1);
+
+ hose->first_busno = pci_hose[0].last_busno + 1;
+ hose->last_busno = 0xff;
+
+ /* PCI memory prefetch space */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI2_MEM_BASE,
+ CFG_PCI2_MEM_PHYS,
+ CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI2_MMIO_BASE,
+ CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI2_IO_BASE,
+ CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO);
+
+ /* System memory space */
+ pci_set_region(hose->regions + 3,
+ CONFIG_PCI_SYS_MEM_BUS,
+ CONFIG_PCI_SYS_MEM_PHYS,
+ gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ hose->region_count = 4;
+
+ pci_setup_indirect(hose,
+ (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384));
+
+ pci_register_hose(hose);
+
+ /*
+ * Write to Command register
+ */
+ reg16 = 0xff;
+ dev = PCI_BDF(hose->first_busno, 0, 0);
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+ /*
+ * Hose scan.
+ */
+ hose->last_busno = pci_hose_scan(hose);
+#endif
+}
+
+#endif /* CONFIG_PCI */
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
+ if (p != NULL) {
+ p[0] = pci_hose[0].first_busno;
+ p[1] = pci_hose[0].last_busno;
+ }
+
+#ifdef CONFIG_MPC83XX_PCI2
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
+ if (p != NULL) {
+ p[0] = pci_hose[1].first_busno;
+ p[1] = pci_hose[1].last_busno;
+ }
+#endif
+}
+#endif /* CONFIG_OF_FLAT_TREE */
diff --git a/board/mpc8349itx/u-boot.lds b/board/mpc8349itx/u-boot.lds
new file mode 100644
index 0000000..f044c0f
--- /dev/null
+++ b/board/mpc8349itx/u-boot.lds
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc83xx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/mpc8360emds/Makefile b/board/mpc8360emds/Makefile
new file mode 100644
index 0000000..5ec7a87
--- /dev/null
+++ b/board/mpc8360emds/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o pci.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mpc8360emds/config.mk b/board/mpc8360emds/config.mk
new file mode 100644
index 0000000..9ace886
--- /dev/null
+++ b/board/mpc8360emds/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC8360EMDS
+#
+
+TEXT_BASE = 0xFE000000
diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c
new file mode 100644
index 0000000..ddc1047
--- /dev/null
+++ b/board/mpc8360emds/mpc8360emds.c
@@ -0,0 +1,657 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on board/mpc8349emds/mpc8349emds.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <command.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#if defined(CONFIG_SPD_EEPROM)
+#include <spd_sdram.h>
+#else
+#include <asm/mmu.h>
+#endif
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* GETH1 */
+ {0, 3, 1, 0, 1}, /* TxD0 */
+ {0, 4, 1, 0, 1}, /* TxD1 */
+ {0, 5, 1, 0, 1}, /* TxD2 */
+ {0, 6, 1, 0, 1}, /* TxD3 */
+ {1, 6, 1, 0, 3}, /* TxD4 */
+ {1, 7, 1, 0, 1}, /* TxD5 */
+ {1, 9, 1, 0, 2}, /* TxD6 */
+ {1, 10, 1, 0, 2}, /* TxD7 */
+ {0, 9, 2, 0, 1}, /* RxD0 */
+ {0, 10, 2, 0, 1}, /* RxD1 */
+ {0, 11, 2, 0, 1}, /* RxD2 */
+ {0, 12, 2, 0, 1}, /* RxD3 */
+ {0, 13, 2, 0, 1}, /* RxD4 */
+ {1, 1, 2, 0, 2}, /* RxD5 */
+ {1, 0, 2, 0, 2}, /* RxD6 */
+ {1, 4, 2, 0, 2}, /* RxD7 */
+ {0, 7, 1, 0, 1}, /* TX_EN */
+ {0, 8, 1, 0, 1}, /* TX_ER */
+ {0, 15, 2, 0, 1}, /* RX_DV */
+ {0, 16, 2, 0, 1}, /* RX_ER */
+ {0, 0, 2, 0, 1}, /* RX_CLK */
+ {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
+ {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
+ /* GETH2 */
+ {0, 17, 1, 0, 1}, /* TxD0 */
+ {0, 18, 1, 0, 1}, /* TxD1 */
+ {0, 19, 1, 0, 1}, /* TxD2 */
+ {0, 20, 1, 0, 1}, /* TxD3 */
+ {1, 2, 1, 0, 1}, /* TxD4 */
+ {1, 3, 1, 0, 2}, /* TxD5 */
+ {1, 5, 1, 0, 3}, /* TxD6 */
+ {1, 8, 1, 0, 3}, /* TxD7 */
+ {0, 23, 2, 0, 1}, /* RxD0 */
+ {0, 24, 2, 0, 1}, /* RxD1 */
+ {0, 25, 2, 0, 1}, /* RxD2 */
+ {0, 26, 2, 0, 1}, /* RxD3 */
+ {0, 27, 2, 0, 1}, /* RxD4 */
+ {1, 12, 2, 0, 2}, /* RxD5 */
+ {1, 13, 2, 0, 3}, /* RxD6 */
+ {1, 11, 2, 0, 2}, /* RxD7 */
+ {0, 21, 1, 0, 1}, /* TX_EN */
+ {0, 22, 1, 0, 1}, /* TX_ER */
+ {0, 29, 2, 0, 1}, /* RX_DV */
+ {0, 30, 2, 0, 1}, /* RX_ER */
+ {0, 31, 2, 0, 1}, /* RX_CLK */
+ {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
+ {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
+
+ {0, 1, 3, 0, 2}, /* MDIO */
+ {0, 2, 1, 0, 1}, /* MDC */
+
+ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+int board_early_init_f(void)
+{
+ volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
+
+ /* Enable flash write */
+ bcsr[0xa] &= ~0x04;
+
+ return 0;
+}
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+int fixed_sdram(void);
+void sdram_init(void);
+
+long int initdram(int board_type)
+{
+ volatile immap_t *im = (immap_t *) CFG_IMMR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+ msize = spd_sdram();
+#else
+ msize = fixed_sdram();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+ /*
+ * Initialize DDR ECC byte
+ */
+ ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+ /*
+ * Initialize SDRAM if it is on local bus.
+ */
+ sdram_init();
+ puts(" DDR RAM: ");
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *) CFG_IMMR;
+ u32 msize = 0;
+ u32 ddr_size;
+ u32 ddr_size_log2;
+
+ msize = CFG_DDR_SIZE;
+ for (ddr_size = msize << 20, ddr_size_log2 = 0;
+ (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+ if (ddr_size & 1) {
+ return -1;
+ }
+ }
+ im->sysconf.ddrlaw[0].ar =
+ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+#if (CFG_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+ im->ddr.csbnds[0].csbnds = 0x00000007;
+ im->ddr.csbnds[1].csbnds = 0x0008000f;
+
+ im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+ im->ddr.cs_config[1] = CFG_DDR_CONFIG;
+
+ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+ im->ddr.sdram_cfg = CFG_DDR_CONTROL;
+
+ im->ddr.sdram_mode = CFG_DDR_MODE;
+ im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ udelay(200);
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+ return msize;
+}
+#endif /*!CFG_SPD_EEPROM */
+
+int checkboard(void)
+{
+ puts("Board: Freescale MPC8360EMDS\n");
+ return 0;
+}
+
+/*
+ * if MPC8360EMDS is soldered with SDRAM
+ */
+#if defined(CFG_BR2_PRELIM) \
+ && defined(CFG_OR2_PRELIM) \
+ && defined(CFG_LBLAWBAR2_PRELIM) \
+ && defined(CFG_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void sdram_init(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile lbus83xx_t *lbc = &immap->lbus;
+ uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
+
+ puts("\n SDRAM on Local Bus: ");
+ print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+ /*
+ * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+ */
+ /*setup mtrpt, lsrt and lbcr for LB bus */
+ lbc->lbcr = CFG_LBC_LBCR;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->lsrt = CFG_LBC_LSRT;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller Machine Mode Register.
+ */
+ lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */
+ lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ /*
+ * We need do 8 times auto refresh operation.
+ */
+ lbc->lsdmr = CFG_LBC_LSDMR_2;
+ asm("sync");
+ *sdram_addr = 0xff; /* 1 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 2 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 3 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 4 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 5 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 6 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 7 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 8 times */
+ udelay(100);
+
+ /* Mode register write operation */
+ lbc->lsdmr = CFG_LBC_LSDMR_4;
+ asm("sync");
+ *(sdram_addr + 0xcc) = 0xff;
+ udelay(100);
+
+ /* Normal operation */
+ lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+}
+#else
+void sdram_init(void)
+{
+ puts("SDRAM on Local Bus is NOT available!\n");
+}
+#endif
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
+/*
+ * ECC user commands
+ */
+void ecc_print_status(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ddr83xx_t *ddr = &immap->ddr;
+
+ printf("\nECC mode: %s\n\n",
+ (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
+
+ /* Interrupts */
+ printf("Memory Error Interrupt Enable:\n");
+ printf(" Multiple-Bit Error Interrupt Enable: %d\n",
+ (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
+ printf(" Single-Bit Error Interrupt Enable: %d\n",
+ (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
+ printf(" Memory Select Error Interrupt Enable: %d\n\n",
+ (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
+
+ /* Error disable */
+ printf("Memory Error Disable:\n");
+ printf(" Multiple-Bit Error Disable: %d\n",
+ (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
+ printf(" Sinle-Bit Error Disable: %d\n",
+ (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
+ printf(" Memory Select Error Disable: %d\n\n",
+ (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
+
+ /* Error injection */
+ printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
+ ddr->data_err_inject_hi, ddr->data_err_inject_lo);
+
+ printf("Memory Data Path Error Injection Mask ECC:\n");
+ printf(" ECC Mirror Byte: %d\n",
+ (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
+ printf(" ECC Injection Enable: %d\n",
+ (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
+ printf(" ECC Error Injection Mask: 0x%02x\n\n",
+ ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
+
+ /* SBE counter/threshold */
+ printf("Memory Single-Bit Error Management (0..255):\n");
+ printf(" Single-Bit Error Threshold: %d\n",
+ (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
+ printf(" Single-Bit Error Counter: %d\n\n",
+ (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
+
+ /* Error detect */
+ printf("Memory Error Detect:\n");
+ printf(" Multiple Memory Errors: %d\n",
+ (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
+ printf(" Multiple-Bit Error: %d\n",
+ (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
+ printf(" Single-Bit Error: %d\n",
+ (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
+ printf(" Memory Select Error: %d\n\n",
+ (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
+
+ /* Capture data */
+ printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
+ printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
+ ddr->capture_data_hi, ddr->capture_data_lo);
+ printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
+ ddr->capture_ecc & CAPTURE_ECC_ECE);
+
+ printf("Memory Error Attributes Capture:\n");
+ printf(" Data Beat Number: %d\n",
+ (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
+ ECC_CAPT_ATTR_BNUM_SHIFT);
+ printf(" Transaction Size: %d\n",
+ (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
+ ECC_CAPT_ATTR_TSIZ_SHIFT);
+ printf(" Transaction Source: %d\n",
+ (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
+ ECC_CAPT_ATTR_TSRC_SHIFT);
+ printf(" Transaction Type: %d\n",
+ (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
+ ECC_CAPT_ATTR_TTYP_SHIFT);
+ printf(" Error Information Valid: %d\n\n",
+ ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
+}
+
+int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ddr83xx_t *ddr = &immap->ddr;
+ volatile u32 val;
+ u64 *addr;
+ u32 count;
+ register u64 *i;
+ u32 ret[2];
+ u32 pattern[2];
+ u32 writeback[2];
+
+ /* The pattern is written into memory to generate error */
+ pattern[0] = 0xfedcba98UL;
+ pattern[1] = 0x76543210UL;
+
+ /* After injecting error, re-initialize the memory with the value */
+ writeback[0] = 0x01234567UL;
+ writeback[1] = 0x89abcdefUL;
+
+ if (argc > 4) {
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ if (argc == 2) {
+ if (strcmp(argv[1], "status") == 0) {
+ ecc_print_status();
+ return 0;
+ } else if (strcmp(argv[1], "captureclear") == 0) {
+ ddr->capture_address = 0;
+ ddr->capture_data_hi = 0;
+ ddr->capture_data_lo = 0;
+ ddr->capture_ecc = 0;
+ ddr->capture_attributes = 0;
+ return 0;
+ }
+ }
+ if (argc == 3) {
+ if (strcmp(argv[1], "sbecnt") == 0) {
+ val = simple_strtoul(argv[2], NULL, 10);
+ if (val > 255) {
+ printf("Incorrect Counter value, "
+ "should be 0..255\n");
+ return 1;
+ }
+
+ val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
+ val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
+
+ ddr->err_sbe = val;
+ return 0;
+ } else if (strcmp(argv[1], "sbethr") == 0) {
+ val = simple_strtoul(argv[2], NULL, 10);
+ if (val > 255) {
+ printf("Incorrect Counter value, "
+ "should be 0..255\n");
+ return 1;
+ }
+
+ val = (val << ECC_ERROR_MAN_SBET_SHIFT);
+ val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
+
+ ddr->err_sbe = val;
+ return 0;
+ } else if (strcmp(argv[1], "errdisable") == 0) {
+ val = ddr->err_disable;
+
+ if (strcmp(argv[2], "+sbe") == 0) {
+ val |= ECC_ERROR_DISABLE_SBED;
+ } else if (strcmp(argv[2], "+mbe") == 0) {
+ val |= ECC_ERROR_DISABLE_MBED;
+ } else if (strcmp(argv[2], "+mse") == 0) {
+ val |= ECC_ERROR_DISABLE_MSED;
+ } else if (strcmp(argv[2], "+all") == 0) {
+ val |= (ECC_ERROR_DISABLE_SBED |
+ ECC_ERROR_DISABLE_MBED |
+ ECC_ERROR_DISABLE_MSED);
+ } else if (strcmp(argv[2], "-sbe") == 0) {
+ val &= ~ECC_ERROR_DISABLE_SBED;
+ } else if (strcmp(argv[2], "-mbe") == 0) {
+ val &= ~ECC_ERROR_DISABLE_MBED;
+ } else if (strcmp(argv[2], "-mse") == 0) {
+ val &= ~ECC_ERROR_DISABLE_MSED;
+ } else if (strcmp(argv[2], "-all") == 0) {
+ val &= ~(ECC_ERROR_DISABLE_SBED |
+ ECC_ERROR_DISABLE_MBED |
+ ECC_ERROR_DISABLE_MSED);
+ } else {
+ printf("Incorrect err_disable field\n");
+ return 1;
+ }
+
+ ddr->err_disable = val;
+ __asm__ __volatile__("sync");
+ __asm__ __volatile__("isync");
+ return 0;
+ } else if (strcmp(argv[1], "errdetectclr") == 0) {
+ val = ddr->err_detect;
+
+ if (strcmp(argv[2], "mme") == 0) {
+ val |= ECC_ERROR_DETECT_MME;
+ } else if (strcmp(argv[2], "sbe") == 0) {
+ val |= ECC_ERROR_DETECT_SBE;
+ } else if (strcmp(argv[2], "mbe") == 0) {
+ val |= ECC_ERROR_DETECT_MBE;
+ } else if (strcmp(argv[2], "mse") == 0) {
+ val |= ECC_ERROR_DETECT_MSE;
+ } else if (strcmp(argv[2], "all") == 0) {
+ val |= (ECC_ERROR_DETECT_MME |
+ ECC_ERROR_DETECT_MBE |
+ ECC_ERROR_DETECT_SBE |
+ ECC_ERROR_DETECT_MSE);
+ } else {
+ printf("Incorrect err_detect field\n");
+ return 1;
+ }
+
+ ddr->err_detect = val;
+ return 0;
+ } else if (strcmp(argv[1], "injectdatahi") == 0) {
+ val = simple_strtoul(argv[2], NULL, 16);
+
+ ddr->data_err_inject_hi = val;
+ return 0;
+ } else if (strcmp(argv[1], "injectdatalo") == 0) {
+ val = simple_strtoul(argv[2], NULL, 16);
+
+ ddr->data_err_inject_lo = val;
+ return 0;
+ } else if (strcmp(argv[1], "injectecc") == 0) {
+ val = simple_strtoul(argv[2], NULL, 16);
+ if (val > 0xff) {
+ printf("Incorrect ECC inject mask, "
+ "should be 0x00..0xff\n");
+ return 1;
+ }
+ val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
+
+ ddr->ecc_err_inject = val;
+ return 0;
+ } else if (strcmp(argv[1], "inject") == 0) {
+ val = ddr->ecc_err_inject;
+
+ if (strcmp(argv[2], "en") == 0)
+ val |= ECC_ERR_INJECT_EIEN;
+ else if (strcmp(argv[2], "dis") == 0)
+ val &= ~ECC_ERR_INJECT_EIEN;
+ else
+ printf("Incorrect command\n");
+
+ ddr->ecc_err_inject = val;
+ __asm__ __volatile__("sync");
+ __asm__ __volatile__("isync");
+ return 0;
+ } else if (strcmp(argv[1], "mirror") == 0) {
+ val = ddr->ecc_err_inject;
+
+ if (strcmp(argv[2], "en") == 0)
+ val |= ECC_ERR_INJECT_EMB;
+ else if (strcmp(argv[2], "dis") == 0)
+ val &= ~ECC_ERR_INJECT_EMB;
+ else
+ printf("Incorrect command\n");
+
+ ddr->ecc_err_inject = val;
+ return 0;
+ }
+ }
+ if (argc == 4) {
+ if (strcmp(argv[1], "testdw") == 0) {
+ addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
+ count = simple_strtoul(argv[3], NULL, 16);
+
+ if ((u32) addr % 8) {
+ printf("Address not alligned on "
+ "double word boundary\n");
+ return 1;
+ }
+ disable_interrupts();
+
+ for (i = addr; i < addr + count; i++) {
+
+ /* enable injects */
+ ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
+ __asm__ __volatile__("sync");
+ __asm__ __volatile__("isync");
+
+ /* write memory location injecting errors */
+ ppcDWstore((u32 *) i, pattern);
+ __asm__ __volatile__("sync");
+
+ /* disable injects */
+ ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
+ __asm__ __volatile__("sync");
+ __asm__ __volatile__("isync");
+
+ /* read data, this generates ECC error */
+ ppcDWload((u32 *) i, ret);
+ __asm__ __volatile__("sync");
+
+ /* re-initialize memory, double word write the location again,
+ * generates new ECC code this time */
+ ppcDWstore((u32 *) i, writeback);
+ __asm__ __volatile__("sync");
+ }
+ enable_interrupts();
+ return 0;
+ }
+ if (strcmp(argv[1], "testword") == 0) {
+ addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
+ count = simple_strtoul(argv[3], NULL, 16);
+
+ if ((u32) addr % 8) {
+ printf("Address not alligned on "
+ "double word boundary\n");
+ return 1;
+ }
+ disable_interrupts();
+
+ for (i = addr; i < addr + count; i++) {
+
+ /* enable injects */
+ ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
+ __asm__ __volatile__("sync");
+ __asm__ __volatile__("isync");
+
+ /* write memory location injecting errors */
+ *(u32 *) i = 0xfedcba98UL;
+ __asm__ __volatile__("sync");
+
+ /* sub double word write,
+ * bus will read-modify-write,
+ * generates ECC error */
+ *((u32 *) i + 1) = 0x76543210UL;
+ __asm__ __volatile__("sync");
+
+ /* disable injects */
+ ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
+ __asm__ __volatile__("sync");
+ __asm__ __volatile__("isync");
+
+ /* re-initialize memory,
+ * double word write the location again,
+ * generates new ECC code this time */
+ ppcDWstore((u32 *) i, writeback);
+ __asm__ __volatile__("sync");
+ }
+ enable_interrupts();
+ return 0;
+ }
+ }
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(ecc, 4, 0, do_ecc,
+ "ecc - support for DDR ECC features\n",
+ "status - print out status info\n"
+ "ecc captureclear - clear capture regs data\n"
+ "ecc sbecnt <val> - set Single-Bit Error counter\n"
+ "ecc sbethr <val> - set Single-Bit Threshold\n"
+ "ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
+ " [-|+]sbe - Single-Bit Error\n"
+ " [-|+]mbe - Multiple-Bit Error\n"
+ " [-|+]mse - Memory Select Error\n"
+ " [-|+]all - all errors\n"
+ "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
+ " mme - Multiple Memory Errors\n"
+ " sbe - Single-Bit Error\n"
+ " mbe - Multiple-Bit Error\n"
+ " mse - Memory Select Error\n"
+ " all - all errors\n"
+ "ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
+ "ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
+ "ecc injectecc <ecc> - set ECC Error Injection Mask\n"
+ "ecc inject <en|dis> - enable/disable error injection\n"
+ "ecc mirror <en|dis> - enable/disable mirror byte\n"
+ "ecc testdw <addr> <cnt> - test mem region with double word access:\n"
+ " - enables injects\n"
+ " - writes pattern injecting errors with double word access\n"
+ " - disables injects\n"
+ " - reads pattern back with double word access, generates error\n"
+ " - re-inits memory\n"
+ "ecc testword <addr> <cnt> - test mem region with word access:\n"
+ " - enables injects\n"
+ " - writes pattern injecting errors with word access\n"
+ " - writes pattern with word access, generates error\n"
+ " - disables injects\n" " - re-inits memory");
+#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
+}
+#endif
diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c
new file mode 100644
index 0000000..15a48dc
--- /dev/null
+++ b/board/mpc8360emds/pci.c
@@ -0,0 +1,313 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/*
+ * PCI Configuration space access support for MPC83xx PCI Bridge
+ */
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <pci.h>
+#include <i2c.h>
+
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_PCI)
+#define PCI_FUNCTION_CONFIG 0x44
+#define PCI_FUNCTION_CFG_LOCK 0x20
+
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxemds_config_table[] = {
+ {
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ pci_cfgfunc_config_device,
+ {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
+ },
+ {}
+}
+#endif
+static struct pci_controller hose[] = {
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc83xxemds_config_table,
+#endif
+ },
+};
+
+/**********************************************************************
+ * pci_init_board()
+ *********************************************************************/
+void pci_init_board(void)
+#ifdef CONFIG_PCISLAVE
+{
+ u16 reg16;
+ volatile immap_t *immr;
+ volatile law83xx_t *pci_law;
+ volatile pot83xx_t *pci_pot;
+ volatile pcictrl83xx_t *pci_ctrl;
+ volatile pciconf83xx_t *pci_conf;
+
+ immr = (immap_t *) CFG_IMMR;
+ pci_law = immr->sysconf.pcilaw;
+ pci_pot = immr->ios.pot;
+ pci_ctrl = immr->pci_ctrl;
+ pci_conf = immr->pci_conf;
+ /*
+ * Configure PCI Inbound Translation Windows
+ */
+ pci_ctrl[0].pitar0 = 0x0;
+ pci_ctrl[0].pibar0 = 0x0;
+ pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
+ PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
+
+ pci_ctrl[0].pitar1 = 0x0;
+ pci_ctrl[0].pibar1 = 0x0;
+ pci_ctrl[0].piebar1 = 0x0;
+ pci_ctrl[0].piwar1 &= ~PIWAR_EN;
+
+ pci_ctrl[0].pitar2 = 0x0;
+ pci_ctrl[0].pibar2 = 0x0;
+ pci_ctrl[0].piebar2 = 0x0;
+ pci_ctrl[0].piwar2 &= ~PIWAR_EN;
+
+ hose[0].first_busno = 0;
+ hose[0].last_busno = 0xff;
+ pci_setup_indirect(&hose[0],
+ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+ reg16 = 0xff;
+
+ pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
+ PCI_COMMAND, &reg16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
+ PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
+ PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
+ PCI_LATENCY_TIMER, 0x80);
+
+ /*
+ * Unlock configuration lock in PCI function configuration register.
+ */
+ pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
+ PCI_FUNCTION_CONFIG, &reg16);
+ reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
+ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
+ PCI_FUNCTION_CONFIG, reg16);
+
+ printf("Enabled PCI 32bit Agent Mode\n");
+}
+#else
+{
+ volatile immap_t *immr;
+ volatile clk83xx_t *clk;
+ volatile law83xx_t *pci_law;
+ volatile pot83xx_t *pci_pot;
+ volatile pcictrl83xx_t *pci_ctrl;
+ volatile pciconf83xx_t *pci_conf;
+
+ u8 val8, orig_i2c_bus;
+ u16 reg16;
+ u32 val32;
+ u32 dev;
+
+ immr = (immap_t *) CFG_IMMR;
+ clk = (clk83xx_t *) & immr->clk;
+ pci_law = immr->sysconf.pcilaw;
+ pci_pot = immr->ios.pot;
+ pci_ctrl = immr->pci_ctrl;
+ pci_conf = immr->pci_conf;
+ /*
+ * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
+ */
+ val32 = clk->occr;
+ udelay(2000);
+#if defined(PCI_66M)
+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+ printf("PCI clock is 66MHz\n");
+#elif defined(PCI_33M)
+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
+ OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
+ printf("PCI clock is 33MHz\n");
+#else
+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+ printf("PCI clock is 66MHz\n");
+#endif
+ udelay(2000);
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+ pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
+
+ /*
+ * Configure PCI Outbound Translation Windows
+ */
+
+ /* PCI mem space - prefetch */
+ pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[0].pocmr =
+ POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
+
+ /* PCI mmio - non-prefetch mem space */
+ pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+ /* PCI IO space */
+ pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+ pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+ pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
+
+ /*
+ * Configure PCI Inbound Translation Windows
+ */
+ pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
+ pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
+ pci_ctrl[0].piebar1 = 0x0;
+ pci_ctrl[0].piwar1 =
+ PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
+ PIWAR_IWS_2G;
+
+ /*
+ * Assign PIB PMC slot to desired PCI bus
+ */
+
+ /* Switch temporarily to I2C bus #2 */
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ val8 = 0;
+ i2c_write(0x23, 0x6, 1, &val8, 1);
+ i2c_write(0x23, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x23, 0x2, 1, &val8, 1);
+ i2c_write(0x23, 0x3, 1, &val8, 1);
+
+ val8 = 0;
+ i2c_write(0x26, 0x6, 1, &val8, 1);
+ val8 = 0x34;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+
+ val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */
+ i2c_write(0x26, 0x2, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+
+ val8 = 0;
+ i2c_write(0x27, 0x6, 1, &val8, 1);
+ i2c_write(0x27, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x27, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x27, 0x3, 1, &val8, 1);
+ asm("eieio");
+
+ /* Reset to original I2C bus */
+ i2c_set_bus_num(orig_i2c_bus);
+
+ /*
+ * Release PCI RST Output signal
+ */
+ udelay(2000);
+ pci_ctrl[0].gcr = 1;
+ udelay(2000);
+
+ hose[0].first_busno = 0;
+ hose[0].last_busno = 0xff;
+
+ /* PCI memory prefetch space */
+ pci_set_region(hose[0].regions + 0,
+ CFG_PCI_MEM_BASE,
+ CFG_PCI_MEM_PHYS,
+ CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+
+ /* PCI memory space */
+ pci_set_region(hose[0].regions + 1,
+ CFG_PCI_MMIO_BASE,
+ CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose[0].regions + 2,
+ CFG_PCI_IO_BASE,
+ CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
+
+ /* System memory space */
+ pci_set_region(hose[0].regions + 3,
+ CFG_PCI_SLV_MEM_LOCAL,
+ CFG_PCI_SLV_MEM_BUS,
+ CFG_PCI_SLV_MEM_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ hose[0].region_count = 4;
+
+ pci_setup_indirect(&hose[0],
+ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+
+ pci_register_hose(hose);
+
+ /*
+ * Write command register
+ */
+ reg16 = 0xff;
+ dev = PCI_BDF(0, 0, 0);
+ pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, &reg16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
+ pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+ printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n");
+
+ /*
+ * Hose scan.
+ */
+ hose->last_busno = pci_hose_scan(hose);
+}
+#endif /* CONFIG_PCISLAVE */
+
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
+ if (p != NULL) {
+ p[0] = hose[0].first_busno;
+ p[1] = hose[0].last_busno;
+ }
+}
+#endif /* CONFIG_OF_FLAT_TREE */
+#endif /* CONFIG_PCI */
diff --git a/board/mpc8360emds/u-boot.lds b/board/mpc8360emds/u-boot.lds
new file mode 100644
index 0000000..937c87a
--- /dev/null
+++ b/board/mpc8360emds/u-boot.lds
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc83xx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c
index 5a23e6c..d896f17 100644
--- a/board/tqm834x/pci.c
+++ b/board/tqm834x/pci.c
@@ -69,17 +69,17 @@ void
pci_init_board(void)
{
volatile immap_t * immr;
- volatile clk8349_t * clk;
- volatile law8349_t * pci_law;
- volatile pot8349_t * pci_pot;
- volatile pcictrl8349_t * pci_ctrl;
- volatile pciconf8349_t * pci_conf;
+ volatile clk83xx_t * clk;
+ volatile law83xx_t * pci_law;
+ volatile pot83xx_t * pci_pot;
+ volatile pcictrl83xx_t * pci_ctrl;
+ volatile pciconf83xx_t * pci_conf;
u16 reg16;
u32 reg32;
struct pci_controller * hose;
- immr = (immap_t *)CFG_IMMRBAR;
- clk = (clk8349_t *)&immr->clk;
+ immr = (immap_t *)CFG_IMMR;
+ clk = (clk83xx_t *)&immr->clk;
pci_law = immr->sysconf.pcilaw;
pci_pot = immr->ios.pot;
pci_ctrl = immr->pci_ctrl;
@@ -186,8 +186,8 @@ pci_init_board(void)
hose->region_count = 3;
pci_setup_indirect(hose,
- (CFG_IMMRBAR+0x8300),
- (CFG_IMMRBAR+0x8304));
+ (CFG_IMMR+0x8300),
+ (CFG_IMMR+0x8304));
pci_register_hose(hose);
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index 41b34cc..36d901f 100644
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -69,7 +69,7 @@ static void set_cs_config(short cs, long config);
static void set_ddr_config(void);
/* Local variable */
-static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+static volatile immap_t *im = (immap_t *)CFG_IMMR;
/**************************************************************************
* Board initialzation after relocation to RAM. Used to detect the number
@@ -147,7 +147,7 @@ int checkboard (void)
volatile immap_t * immr;
u32 w, f;
- immr = (immap_t *)CFG_IMMRBAR;
+ immr = (immap_t *)CFG_IMMR;
if (!(immr->reset.rcwh & RCWH_PCIHOST)) {
printf("PCI: NOT in host mode..?!\n");
return 0;
generated by cgit v1.1 at 2024-11-06 03:47:46 +0000