diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/ti/am335x/board.c | 87 |
1 files changed, 80 insertions, 7 deletions
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 51c4358..8f47692 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -16,6 +16,7 @@ #include <asm/arch/omap.h> #include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> +#include <asm/arch/clk_synthesizer.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> @@ -37,8 +38,13 @@ DECLARE_GLOBAL_DATA_PTR; /* GPIO that controls power to DDR on EVM-SK */ -#define GPIO_DDR_VTT_EN 7 -#define ICE_GPIO_DDR_VTT_EN 18 +#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) +#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7) +#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18) +#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4) +#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) +#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) +#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) #if defined(CONFIG_SPL_BUILD) || \ (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH)) @@ -474,6 +480,49 @@ void sdram_init(void) } #endif +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void request_and_set_gpio(int gpio, char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret < 0) { + printf("%s: Unable to request %s\n", __func__, name); + return; + } + + ret = gpio_direction_output(gpio, 0); + if (ret < 0) { + printf("%s: Unable to set %s as output\n", __func__, name); + goto err_free_gpio; + } + + gpio_set_value(gpio, 1); + + return; + +err_free_gpio: + gpio_free(gpio); +} + +#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N); + +/** + * RMII mode on ICEv2 board needs 50MHz clock. Given the clock + * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle + * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to + * give 50MHz output for Eth0 and 1. + */ +static struct clk_synth cdce913_data = { + .id = 0x81, + .capacitor = 0x90, + .mux = 0x6d, + .pdiv2 = 0x2, + .pdiv3 = 0x2, +}; +#endif + /* * Basic board specific setup. Pinmux has been handled already. */ @@ -487,6 +536,23 @@ int board_init(void) #if defined(CONFIG_NOR) || defined(CONFIG_NAND) gpmc_init(); #endif +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) + int rv; + + if (board_is_icev2()) { + REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); + REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL); + REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); + REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); + + rv = setup_clock_synthesizer(&cdce913_data); + if (rv) { + printf("Clock synthesizer setup failed %d\n", rv); + return rv; + } + } +#endif + return 0; } @@ -554,6 +620,12 @@ static struct cpsw_platform_data cpsw_data = { }; #endif +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\ + defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) + /* * This function will: * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr @@ -565,11 +637,6 @@ static struct cpsw_platform_data cpsw_data = { * Build in only these cases to avoid warnings about unused variables * when we build an SPL that has neither option but full U-Boot will. */ -#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ - && defined(CONFIG_SPL_BUILD)) || \ - ((defined(CONFIG_DRIVER_TI_CPSW) || \ - defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \ - !defined(CONFIG_SPL_BUILD)) int board_eth_init(bd_t *bis) { int rv, n = 0; @@ -620,6 +687,12 @@ int board_eth_init(bd_t *bis) writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; + } else if (board_is_icev2()) { + writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; + cpsw_slaves[0].phy_addr = 1; + cpsw_slaves[1].phy_addr = 3; } else { writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = |