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-rw-r--r--board/Barix/ipam390/ipam390-ais-uart.cfg2
-rw-r--r--board/Barix/ipam390/ipam390.c29
-rw-r--r--board/atmel/at91sam9n12ek/at91sam9n12ek.c11
-rw-r--r--board/boundary/nitrogen6x/6x_upgrade.txt2
-rw-r--r--board/compulab/cm_t35/Makefile3
-rw-r--r--board/compulab/cm_t35/cm_t35.c7
-rw-r--r--board/compulab/common/Makefile10
-rw-r--r--board/compulab/common/eeprom.c (renamed from board/compulab/cm_t35/eeprom.c)51
-rw-r--r--board/compulab/common/eeprom.h (renamed from board/compulab/cm_t35/eeprom.h)8
-rw-r--r--board/compulab/common/omap3_display.c (renamed from board/compulab/cm_t35/display.c)8
-rw-r--r--board/corscience/tricorder/Makefile2
-rw-r--r--board/corscience/tricorder/led.c80
-rw-r--r--board/corscience/tricorder/tricorder-eeprom.c251
-rw-r--r--board/corscience/tricorder/tricorder-eeprom.h41
-rw-r--r--board/corscience/tricorder/tricorder.c126
-rw-r--r--board/corscience/tricorder/tricorder.h4
-rw-r--r--board/enbw/enbw_cmc/enbw_cmc.c1
-rw-r--r--board/ppcag/bg0900/Makefile (renamed from board/prodrive/pdnb3/Makefile)8
-rw-r--r--board/ppcag/bg0900/bg0900.c86
-rw-r--r--board/ppcag/bg0900/spl_boot.c153
-rw-r--r--board/prodrive/pdnb3/flash.c73
-rw-r--r--board/prodrive/pdnb3/nand.c129
-rw-r--r--board/prodrive/pdnb3/pdnb3.c220
-rw-r--r--board/ti/am335x/board.c6
-rw-r--r--board/udoo/Makefile7
-rw-r--r--board/udoo/udoo.c110
-rw-r--r--board/wandboard/README4
27 files changed, 936 insertions, 496 deletions
diff --git a/board/Barix/ipam390/ipam390-ais-uart.cfg b/board/Barix/ipam390/ipam390-ais-uart.cfg
index e1a99f2..709cf23 100644
--- a/board/Barix/ipam390/ipam390-ais-uart.cfg
+++ b/board/Barix/ipam390/ipam390-ais-uart.cfg
@@ -109,7 +109,7 @@ CLK2XSRC = 0x00000000
;NANDFCR = 0x00000000
[EMIF25ASYNC]
A1CR = 0x00000000
-A2CR = 0x3FFFFFFE
+A2CR = 0x04202110
A3CR = 0x00000000
A4CR = 0x00000000
NANDFCR = 0x00000012
diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c
index f3f276e..ae88b42 100644
--- a/board/Barix/ipam390/ipam390.c
+++ b/board/Barix/ipam390/ipam390.c
@@ -264,7 +264,7 @@ void show_boot_progress(int status)
static int green;
if (red == 0)
- red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF);
+ red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
if (red != CONFIG_IPAM390_GPIO_LED_RED)
return;
if (green == 0)
@@ -277,10 +277,10 @@ void show_boot_progress(int status)
case BOOTSTAGE_ID_RUN_OS:
/*
* set normal state
- * LED Red : off
+ * LED Red : on
* LED green: off
*/
- gpio_set_value(red, LED_OFF);
+ gpio_set_value(red, LED_ON);
gpio_set_value(green, LED_OFF);
break;
case BOOTSTAGE_ID_MAIN_LOOP:
@@ -326,23 +326,12 @@ int spl_start_uboot(void)
if (!bootmode)
if (ret == 0)
bootmode = 1;
- if (bootmode) {
- /*
- * Booting U-Boot
- * LED Red : on
- * LED green: off
- */
- init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
- init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF);
- } else {
- /*
- * Booting Linux
- * LED Red : off
- * LED green: off
- */
- init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF);
- init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF);
- }
+ /*
+ * LED red : on
+ * LED green: off
+ */
+ init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
+ init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF);
return bootmode;
}
#endif
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index 2ec32eb..9adc992 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -199,6 +199,13 @@ void at91sam9n12ek_ks8851_hw_init(void)
}
#endif
+#ifdef CONFIG_USB_ATMEL
+void at91sam9n12ek_usb_hw_init(void)
+{
+ at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
+}
+#endif
+
int board_early_init_f(void)
{
/* Enable clocks for all PIOs */
@@ -230,6 +237,10 @@ int board_init(void)
at91sam9n12ek_ks8851_hw_init();
#endif
+#ifdef CONFIG_USB_ATMEL
+ at91sam9n12ek_usb_hw_init();
+#endif
+
return 0;
}
diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt
index 1f9a889..1a62bbf 100644
--- a/board/boundary/nitrogen6x/6x_upgrade.txt
+++ b/board/boundary/nitrogen6x/6x_upgrade.txt
@@ -17,7 +17,7 @@ if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk
sleep 1 ;
done
echo "erasing" ;
- sf erase 0 0x50000 ;
+ sf erase 0 0xC0000 ;
# two steps to prevent bricking
echo "programming" ;
sf write 0x12000000 $offset $filesize ;
diff --git a/board/compulab/cm_t35/Makefile b/board/compulab/cm_t35/Makefile
index 66b264a..6e2e1cb 100644
--- a/board/compulab/cm_t35/Makefile
+++ b/board/compulab/cm_t35/Makefile
@@ -7,7 +7,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
-obj-$(CONFIG_LCD) += display.o
-
obj-y += cm_t35.o leds.o
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index 19945c1..b9a9965 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -33,7 +33,7 @@
#include <asm/ehci-omap.h>
#include <asm/gpio.h>
-#include "eeprom.h"
+#include "../common/eeprom.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -160,7 +160,7 @@ static u32 cm_t3x_rev;
u32 get_board_rev(void)
{
if (!cm_t3x_rev)
- cm_t3x_rev = cm_t3x_eeprom_get_board_rev();
+ cm_t3x_rev = cl_eeprom_get_board_rev();
return cm_t3x_rev;
};
@@ -509,7 +509,7 @@ static int handle_mac_address(void)
if (rc)
return 0;
- rc = cm_t3x_eeprom_read_mac_addr(enetaddr);
+ rc = cl_eeprom_read_mac_addr(enetaddr);
if (rc)
return rc;
@@ -599,5 +599,4 @@ int ehci_hcd_stop(void)
{
return omap_ehci_hcd_stop();
}
-
#endif /* CONFIG_USB_EHCI_OMAP */
diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile
new file mode 100644
index 0000000..831be2e
--- /dev/null
+++ b/board/compulab/common/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Author: Igor Grinberg <grinberg@compulab.co.il>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
+obj-$(CONFIG_LCD) += omap3_display.o
diff --git a/board/compulab/cm_t35/eeprom.c b/board/compulab/common/eeprom.c
index df91acd..5aa3dbd 100644
--- a/board/compulab/cm_t35/eeprom.c
+++ b/board/compulab/common/eeprom.c
@@ -22,30 +22,30 @@
#define LAYOUT_INVALID 0
#define LAYOUT_LEGACY 0xff
-static int eeprom_layout; /* Implicitly LAYOUT_INVALID */
+static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */
-static int cm_t3x_eeprom_read(uint offset, uchar *buf, int len)
+static int cl_eeprom_read(uint offset, uchar *buf, int len)
{
return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len);
}
-static int eeprom_setup_layout(void)
+static int cl_eeprom_setup_layout(void)
{
int res;
- if (eeprom_layout != LAYOUT_INVALID)
+ if (cl_eeprom_layout != LAYOUT_INVALID)
return 0;
- res = cm_t3x_eeprom_read(EEPROM_LAYOUT_VER_OFFSET,
- (uchar *)&eeprom_layout, 1);
+ res = cl_eeprom_read(EEPROM_LAYOUT_VER_OFFSET,
+ (uchar *)&cl_eeprom_layout, 1);
if (res) {
- eeprom_layout = LAYOUT_INVALID;
+ cl_eeprom_layout = LAYOUT_INVALID;
return res;
}
- if (eeprom_layout == 0 || eeprom_layout >= 0x20)
- eeprom_layout = LAYOUT_LEGACY;
+ if (cl_eeprom_layout == 0 || cl_eeprom_layout >= 0x20)
+ cl_eeprom_layout = LAYOUT_LEGACY;
return 0;
}
@@ -56,12 +56,14 @@ void get_board_serial(struct tag_serialnr *serialnr)
uint offset;
memset(serialnr, 0, sizeof(*serialnr));
- if (eeprom_setup_layout())
+
+ if (cl_eeprom_setup_layout())
return;
- offset = (eeprom_layout != LAYOUT_LEGACY) ?
- BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY;
- if (cm_t3x_eeprom_read(offset, (uchar *)serial, 8))
+ offset = (cl_eeprom_layout != LAYOUT_LEGACY) ?
+ BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY;
+
+ if (cl_eeprom_read(offset, (uchar *)serial, 8))
return;
if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) {
@@ -71,45 +73,46 @@ void get_board_serial(struct tag_serialnr *serialnr)
}
/*
- * Routine: cm_t3x_eeprom_read_mac_addr
+ * Routine: cl_eeprom_read_mac_addr
* Description: read mac address and store it in buf.
*/
-int cm_t3x_eeprom_read_mac_addr(uchar *buf)
+int cl_eeprom_read_mac_addr(uchar *buf)
{
uint offset;
- if (eeprom_setup_layout())
+ if (cl_eeprom_setup_layout())
return 0;
- offset = (eeprom_layout != LAYOUT_LEGACY) ?
+ offset = (cl_eeprom_layout != LAYOUT_LEGACY) ?
MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY;
- return cm_t3x_eeprom_read(offset, buf, 6);
+
+ return cl_eeprom_read(offset, buf, 6);
}
/*
- * Routine: cm_t3x_eeprom_get_board_rev
+ * Routine: cl_eeprom_get_board_rev
* Description: read system revision from eeprom
*/
-u32 cm_t3x_eeprom_get_board_rev(void)
+u32 cl_eeprom_get_board_rev(void)
{
u32 rev = 0;
char str[5]; /* Legacy representation can contain at most 4 digits */
uint offset = BOARD_REV_OFFSET_LEGACY;
- if (eeprom_setup_layout())
+ if (cl_eeprom_setup_layout())
return 0;
- if (eeprom_layout != LAYOUT_LEGACY)
+ if (cl_eeprom_layout != LAYOUT_LEGACY)
offset = BOARD_REV_OFFSET;
- if (cm_t3x_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE))
+ if (cl_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE))
return 0;
/*
* Convert legacy syntactic representation to semantic
* representation. i.e. for rev 1.00: 0x100 --> 0x64
*/
- if (eeprom_layout == LAYOUT_LEGACY) {
+ if (cl_eeprom_layout == LAYOUT_LEGACY) {
sprintf(str, "%x", rev);
rev = simple_strtoul(str, NULL, 10);
}
diff --git a/board/compulab/cm_t35/eeprom.h b/board/compulab/common/eeprom.h
index 02ffbb1..cf8c302 100644
--- a/board/compulab/cm_t35/eeprom.h
+++ b/board/compulab/common/eeprom.h
@@ -11,14 +11,14 @@
#define _EEPROM_
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
-int cm_t3x_eeprom_read_mac_addr(uchar *buf);
-u32 cm_t3x_eeprom_get_board_rev(void);
+int cl_eeprom_read_mac_addr(uchar *buf);
+u32 cl_eeprom_get_board_rev(void);
#else
-static inline int cm_t3x_eeprom_read_mac_addr(uchar *buf)
+static inline int cl_eeprom_read_mac_addr(uchar *buf)
{
return 1;
}
-static inline u32 cm_t3x_eeprom_get_board_rev(void)
+static inline u32 cl_eeprom_get_board_rev(void)
{
return 0;
}
diff --git a/board/compulab/cm_t35/display.c b/board/compulab/common/omap3_display.c
index fae8d95..ead821e 100644
--- a/board/compulab/cm_t35/display.c
+++ b/board/compulab/common/omap3_display.c
@@ -51,6 +51,7 @@ static const struct panel_config preset_dvi_640X480 = {
.lcd_size = PANEL_LCD_SIZE(640, 480),
.timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96),
.timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2),
+ .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
.divisor = 12 | (1 << 16),
.data_lines = LCD_INTERFACE_24_BIT,
.panel_type = ACTIVE_DISPLAY,
@@ -62,6 +63,7 @@ static const struct panel_config preset_dvi_800X600 = {
.lcd_size = PANEL_LCD_SIZE(800, 600),
.timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128),
.timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4),
+ .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
.divisor = 8 | (1 << 16),
.data_lines = LCD_INTERFACE_24_BIT,
.panel_type = ACTIVE_DISPLAY,
@@ -73,6 +75,7 @@ static const struct panel_config preset_dvi_1024X768 = {
.lcd_size = PANEL_LCD_SIZE(1024, 768),
.timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136),
.timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6),
+ .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
.divisor = 5 | (1 << 16),
.data_lines = LCD_INTERFACE_24_BIT,
.panel_type = ACTIVE_DISPLAY,
@@ -84,7 +87,8 @@ static const struct panel_config preset_dvi_1152X864 = {
.lcd_size = PANEL_LCD_SIZE(1152, 864),
.timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128),
.timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3),
- .divisor = 3 | (1 << 16),
+ .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
+ .divisor = 4 | (1 << 16),
.data_lines = LCD_INTERFACE_24_BIT,
.panel_type = ACTIVE_DISPLAY,
.load_mode = 2,
@@ -95,6 +99,7 @@ static const struct panel_config preset_dvi_1280X960 = {
.lcd_size = PANEL_LCD_SIZE(1280, 960),
.timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112),
.timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3),
+ .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
.divisor = 3 | (1 << 16),
.data_lines = LCD_INTERFACE_24_BIT,
.panel_type = ACTIVE_DISPLAY,
@@ -106,6 +111,7 @@ static const struct panel_config preset_dvi_1280X1024 = {
.lcd_size = PANEL_LCD_SIZE(1280, 1024),
.timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112),
.timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3),
+ .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
.divisor = 3 | (1 << 16),
.data_lines = LCD_INTERFACE_24_BIT,
.panel_type = ACTIVE_DISPLAY,
diff --git a/board/corscience/tricorder/Makefile b/board/corscience/tricorder/Makefile
index d5316f8..266432d 100644
--- a/board/corscience/tricorder/Makefile
+++ b/board/corscience/tricorder/Makefile
@@ -8,4 +8,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := tricorder.o
+obj-y := tricorder.o tricorder-eeprom.o led.o
diff --git a/board/corscience/tricorder/led.c b/board/corscience/tricorder/led.c
new file mode 100644
index 0000000..30f2f50
--- /dev/null
+++ b/board/corscience/tricorder/led.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2013 Corscience GmbH & Co.KG
+ * Andreas Bießmann <andreas.biessmann@corscience.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <status_led.h>
+#include <twl4030.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+
+#define TRICORDER_STATUS_LED_YELLOW 42
+#define TRICORDER_STATUS_LED_GREEN 43
+
+void __led_init(led_id_t mask, int state)
+{
+ __led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+ int toggle_gpio = 0;
+#ifdef STATUS_LED_BIT
+ if (!toggle_gpio && STATUS_LED_BIT & mask)
+ toggle_gpio = TRICORDER_STATUS_LED_GREEN;
+#endif
+#ifdef STATUS_LED_BIT1
+ if (!toggle_gpio && STATUS_LED_BIT1 & mask)
+ toggle_gpio = TRICORDER_STATUS_LED_YELLOW;
+#endif
+#ifdef STATUS_LED_BIT2
+ if (!toggle_gpio && STATUS_LED_BIT2 & mask) {
+ uint8_t val;
+ twl4030_i2c_read_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN,
+ &val);
+ val ^= (TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDAPWM);
+ twl4030_i2c_write_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN,
+ val);
+ }
+#endif
+ if (toggle_gpio) {
+ int state;
+ gpio_request(toggle_gpio, "");
+ state = gpio_get_value(toggle_gpio);
+ gpio_set_value(toggle_gpio, !state);
+ }
+}
+
+void __led_set(led_id_t mask, int state)
+{
+#ifdef STATUS_LED_BIT
+ if (STATUS_LED_BIT & mask) {
+ gpio_request(TRICORDER_STATUS_LED_GREEN, "");
+ gpio_direction_output(TRICORDER_STATUS_LED_GREEN, 0);
+ gpio_set_value(TRICORDER_STATUS_LED_GREEN, state);
+ }
+#endif
+#ifdef STATUS_LED_BIT1
+ if (STATUS_LED_BIT1 & mask) {
+ gpio_request(TRICORDER_STATUS_LED_YELLOW, "");
+ gpio_direction_output(TRICORDER_STATUS_LED_YELLOW, 0);
+ gpio_set_value(TRICORDER_STATUS_LED_YELLOW, state);
+ }
+#endif
+#ifdef STATUS_LED_BIT2
+ if (STATUS_LED_BIT2 & mask) {
+ if (STATUS_LED_OFF == state)
+ twl4030_i2c_write_u8(TWL4030_CHIP_LED,
+ TWL4030_LED_LEDEN, 0);
+ else
+ twl4030_i2c_write_u8(TWL4030_CHIP_LED,
+ TWL4030_LED_LEDEN,
+ (TWL4030_LED_LEDEN_LEDAON |
+ TWL4030_LED_LEDEN_LEDAPWM));
+ }
+#endif
+}
diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c
new file mode 100644
index 0000000..1c74a0f
--- /dev/null
+++ b/board/corscience/tricorder/tricorder-eeprom.c
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2013
+ * Corscience GmbH & Co. KG, <www.corscience.de>
+ * Andreas Bießmann <andreas.biessmann@corscience.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <i2c.h>
+
+#include "tricorder-eeprom.h"
+
+static inline void warn_wrong_value(const char *msg, unsigned int a,
+ unsigned int b)
+{
+ printf("Expected EEPROM %s %08x, got %08x\n", msg, a, b);
+}
+
+static int handle_eeprom_v0(struct tricorder_eeprom *eeprom)
+{
+ struct tricorder_eeprom_v0 {
+ uint32_t magic;
+ uint16_t length;
+ uint16_t version;
+ char board_name[TRICORDER_BOARD_NAME_LENGTH];
+ char board_version[TRICORDER_BOARD_VERSION_LENGTH];
+ char board_serial[TRICORDER_BOARD_SERIAL_LENGTH];
+ uint32_t crc32;
+ } __packed eepromv0;
+ uint32_t crc;
+
+ printf("Old EEPROM (v0), consider rewrite!\n");
+
+ if (be16_to_cpu(eeprom->length) != sizeof(eepromv0)) {
+ warn_wrong_value("length", sizeof(eepromv0),
+ be16_to_cpu(eeprom->length));
+ return 1;
+ }
+
+ memcpy(&eepromv0, eeprom, sizeof(eepromv0));
+
+ crc = crc32(0L, (unsigned char *)&eepromv0,
+ sizeof(eepromv0) - sizeof(eepromv0.crc32));
+ if (be32_to_cpu(eepromv0.crc32) != crc) {
+ warn_wrong_value("CRC", be32_to_cpu(eepromv0.crc32),
+ crc);
+ return 1;
+ }
+
+ /* Ok the content is correct, do the conversion */
+ memset(eeprom->interface_version, 0x0,
+ TRICORDER_INTERFACE_VERSION_LENGTH);
+ crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE);
+ eeprom->crc32 = cpu_to_be32(crc);
+
+ return 0;
+}
+
+static int handle_eeprom_v1(struct tricorder_eeprom *eeprom)
+{
+ uint32_t crc;
+
+ if (be16_to_cpu(eeprom->length) != TRICORDER_EEPROM_SIZE) {
+ warn_wrong_value("length", TRICORDER_EEPROM_SIZE,
+ be16_to_cpu(eeprom->length));
+ return 1;
+ }
+
+ crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE);
+ if (be32_to_cpu(eeprom->crc32) != crc) {
+ warn_wrong_value("CRC", be32_to_cpu(eeprom->crc32), crc);
+ return 1;
+ }
+
+ return 0;
+}
+
+int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom)
+{
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
+
+ i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE);
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+ if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) {
+ warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC,
+ be32_to_cpu(eeprom->magic));
+ return 1;
+ }
+
+ switch (be16_to_cpu(eeprom->version)) {
+ case 0:
+ return handle_eeprom_v0(eeprom);
+ case 1:
+ return handle_eeprom_v1(eeprom);
+ default:
+ warn_wrong_value("version", TRICORDER_EEPROM_VERSION,
+ be16_to_cpu(eeprom->version));
+ return 1;
+ }
+}
+
+#if !defined(CONFIG_SPL)
+int tricorder_eeprom_read(unsigned devaddr)
+{
+ struct tricorder_eeprom eeprom;
+ int ret = tricorder_get_eeprom(devaddr, &eeprom);
+
+ if (ret)
+ return ret;
+
+ printf("Board type: %.*s\n",
+ sizeof(eeprom.board_name), eeprom.board_name);
+ printf("Board version: %.*s\n",
+ sizeof(eeprom.board_version), eeprom.board_version);
+ printf("Board serial: %.*s\n",
+ sizeof(eeprom.board_serial), eeprom.board_serial);
+ printf("Board interface version: %.*s\n",
+ sizeof(eeprom.interface_version),
+ eeprom.interface_version);
+
+ return ret;
+}
+
+int tricorder_eeprom_write(unsigned devaddr, const char *name,
+ const char *version, const char *serial, const char *interface)
+{
+ struct tricorder_eeprom eeprom, eeprom_verify;
+ size_t length;
+ uint32_t crc;
+ int ret;
+ unsigned char *p;
+ int i;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
+ memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE);
+
+ eeprom.magic = cpu_to_be32(TRICORDER_EEPROM_MAGIC);
+ eeprom.length = cpu_to_be16(TRICORDER_EEPROM_SIZE);
+ eeprom.version = cpu_to_be16(TRICORDER_EEPROM_VERSION);
+
+ length = min(sizeof(eeprom.board_name), strlen(name));
+ strncpy(eeprom.board_name, name, length);
+
+ length = min(sizeof(eeprom.board_version), strlen(version));
+ strncpy(eeprom.board_version, version, length);
+
+ length = min(sizeof(eeprom.board_serial), strlen(serial));
+ strncpy(eeprom.board_serial, serial, length);
+
+ if (interface) {
+ length = min(sizeof(eeprom.interface_version),
+ strlen(interface));
+ strncpy(eeprom.interface_version, interface, length);
+ }
+
+ crc = crc32(0L, (unsigned char *)&eeprom, TRICORDER_EEPROM_CRC_SIZE);
+ eeprom.crc32 = cpu_to_be32(crc);
+
+#if defined(DEBUG)
+ puts("Tricorder EEPROM content:\n");
+ print_buffer(0, &eeprom, 1, sizeof(eeprom), 16);
+#endif
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ /* do page write to the eeprom */
+ for (i = 0, p = (unsigned char *)&eeprom;
+ i < sizeof(eeprom);
+ i += 32, p += 32) {
+ ret = i2c_write(devaddr, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ p, min(sizeof(eeprom) - i, 32));
+ if (ret)
+ break;
+ udelay(5000); /* 5ms write cycle timing */
+ }
+
+ ret = i2c_read(devaddr, 0, 2, (unsigned char *)&eeprom_verify,
+ TRICORDER_EEPROM_SIZE);
+
+ if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) {
+ printf("Tricorder: Could not verify EEPROM content!\n");
+ ret = 1;
+ }
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+ return ret;
+}
+
+int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ if (argc == 3) {
+ ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
+ eeprom_init();
+ if (strcmp(argv[1], "read") == 0) {
+ int rcode;
+
+ rcode = tricorder_eeprom_read(dev_addr);
+
+ return rcode;
+ }
+ } else if (argc == 6 || argc == 7) {
+ ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
+ char *name = argv[3];
+ char *version = argv[4];
+ char *serial = argv[5];
+ char *interface = NULL;
+ eeprom_init();
+
+ if (argc == 7)
+ interface = argv[6];
+
+ if (strcmp(argv[1], "write") == 0) {
+ int rcode;
+
+ rcode = tricorder_eeprom_write(dev_addr, name, version,
+ serial, interface);
+
+ return rcode;
+ }
+ }
+
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ tricordereeprom, 7, 1, do_tricorder_eeprom,
+ "Tricorder EEPROM",
+ "read devaddr\n"
+ " - read Tricorder EEPROM at devaddr and print content\n"
+ "tricordereeprom write devaddr name version serial [interface]\n"
+ " - write Tricorder EEPROM at devaddr with 'name', 'version'"
+ "and 'serial'\n"
+ " optional add an HW interface parameter"
+);
+#endif /* CONFIG_SPL */
diff --git a/board/corscience/tricorder/tricorder-eeprom.h b/board/corscience/tricorder/tricorder-eeprom.h
new file mode 100644
index 0000000..06ed9a5
--- /dev/null
+++ b/board/corscience/tricorder/tricorder-eeprom.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2013
+ * Corscience GmbH & Co. KG, <www.corscience.de>
+ * Andreas Bießmann <andreas.biessmann@corscience.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef TRICORDER_EEPROM_H_
+#define TRICORDER_EEPROM_H_
+
+#include <linux/compiler.h>
+
+#define TRICORDER_EEPROM_MAGIC 0xc2a94f52
+#define TRICORDER_EEPROM_VERSION 1
+
+#define TRICORDER_BOARD_NAME_LENGTH 12
+#define TRICORDER_BOARD_VERSION_LENGTH 4
+#define TRICORDER_BOARD_SERIAL_LENGTH 12
+#define TRICORDER_INTERFACE_VERSION_LENGTH 4
+
+struct tricorder_eeprom {
+ uint32_t magic;
+ uint16_t length;
+ uint16_t version;
+ char board_name[TRICORDER_BOARD_NAME_LENGTH];
+ char board_version[TRICORDER_BOARD_VERSION_LENGTH];
+ char board_serial[TRICORDER_BOARD_SERIAL_LENGTH];
+ char interface_version[TRICORDER_INTERFACE_VERSION_LENGTH];
+ uint32_t crc32;
+} __packed;
+
+#define TRICORDER_EEPROM_SIZE sizeof(struct tricorder_eeprom)
+#define TRICORDER_EEPROM_CRC_SIZE (TRICORDER_EEPROM_SIZE - \
+ sizeof(uint32_t))
+
+/**
+ * @brief read eeprom information from a specific eeprom address
+ */
+int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom);
+
+#endif /* TRICORDER_EEPROM_H_ */
diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c
index c7099e5..2dfcb27 100644
--- a/board/corscience/tricorder/tricorder.c
+++ b/board/corscience/tricorder/tricorder.c
@@ -13,11 +13,13 @@
#include <common.h>
#include <twl4030.h>
#include <asm/io.h>
+#include <asm/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include "tricorder.h"
+#include "tricorder-eeprom.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -34,16 +36,91 @@ int board_init(void)
return 0;
}
+/**
+ * get_eeprom - read the eeprom
+ *
+ * @eeprom - pointer to a eeprom struct to fill
+ *
+ * This function will panic() on wrong EEPROM content
+ */
+static void get_eeprom(struct tricorder_eeprom *eeprom)
+{
+ int ret;
+
+ if (!eeprom)
+ panic("No eeprom given!\n");
+
+ ret = gpio_request(7, "BMS");
+ if (ret)
+ panic("gpio: requesting BMS pin failed\n");
+
+ ret = gpio_direction_input(7);
+ if (ret)
+ panic("gpio: set BMS as input failed\n");
+
+ ret = gpio_get_value(7);
+ if (ret < 0)
+ panic("gpio: get BMS pin state failed\n");
+
+ gpio_free(7);
+
+ if (ret == 0) {
+ /* BMS is _not_ set, do the EEPROM check */
+ ret = tricorder_get_eeprom(0x51, eeprom);
+ if (!ret) {
+ if (strncmp(eeprom->board_name, "CS10411", 7) != 0)
+ panic("Wrong board name '%.*s'\n",
+ sizeof(eeprom->board_name),
+ eeprom->board_name);
+ if (eeprom->board_version[0] < 'D')
+ panic("Wrong board version '%.*s'\n",
+ sizeof(eeprom->board_version),
+ eeprom->board_version);
+ } else {
+ panic("Could not get board revision\n");
+ }
+ }
+}
+
+/**
+ * print_hwversion - print out a HW version string
+ *
+ * @eeprom - pointer to the eeprom
+ */
+static void print_hwversion(struct tricorder_eeprom *eeprom)
+{
+ size_t len;
+ if (!eeprom)
+ panic("No eeprom given!");
+
+ printf("Board %.*s:%.*s serial %.*s",
+ sizeof(eeprom->board_name), eeprom->board_name,
+ sizeof(eeprom->board_version), eeprom->board_version,
+ sizeof(eeprom->board_serial), eeprom->board_serial);
+
+ len = strnlen(eeprom->interface_version,
+ sizeof(eeprom->interface_version));
+ if (len > 0)
+ printf(" HW interface version %.*s",
+ sizeof(eeprom->interface_version),
+ eeprom->interface_version);
+ puts("\n");
+}
+
/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
int misc_init_r(void)
{
+ struct tricorder_eeprom eeprom;
+ get_eeprom(&eeprom);
+ print_hwversion(&eeprom);
+
twl4030_power_init();
-#ifdef CONFIG_TWL4030_LED
- twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
-#endif
+ status_led_set(0, STATUS_LED_ON);
+ status_led_set(1, STATUS_LED_ON);
+ status_led_set(2, STATUS_LED_ON);
dieid_num_r();
@@ -77,12 +154,43 @@ int board_mmc_init(bd_t *bis)
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
+ struct tricorder_eeprom eeprom;
+ get_eeprom(&eeprom);
+
/* General SDRC config */
- timings->mcfg = MICRON_V_MCFG_165(128 << 20);
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ if (eeprom.board_version[0] > 'D') {
+ /* use optimized timings for our SDRAM device */
+ timings->mcfg = MCFG((256 << 20), 14);
+#define MT46H64M32_TDAL 6 /* Twr/Tck + Trp/tck */
+ /* 15/6 + 18/6 = 5.5 -> 6 */
+#define MT46H64M32_TDPL 3 /* 15/6 = 2.5 -> 3 (Twr) */
+#define MT46H64M32_TRRD 2 /* 12/6 = 2 */
+#define MT46H64M32_TRCD 3 /* 18/6 = 3 */
+#define MT46H64M32_TRP 3 /* 18/6 = 3 */
+#define MT46H64M32_TRAS 7 /* 42/6 = 7 */
+#define MT46H64M32_TRC 10 /* 60/6 = 10 */
+#define MT46H64M32_TRFC 12 /* 72/6 = 12 */
+ timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC,
+ MT46H64M32_TRAS, MT46H64M32_TRP,
+ MT46H64M32_TRCD, MT46H64M32_TRRD,
+ MT46H64M32_TDPL,
+ MT46H64M32_TDAL);
+
+#define MT46H64M32_TWTR 1
+#define MT46H64M32_TCKE 1
+#define MT46H64M32_XSR 19 /* 112.5/6 = 18.75 => ~19 */
+#define MT46H64M32_TXP 1
+ timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE,
+ MT46H64M32_TXP, MT46H64M32_XSR);
- /* AC timings */
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- timings->mr = MICRON_V_MR_165;
+ timings->mr = MICRON_V_MR_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ } else {
+ /* use conservative beagleboard timings as default */
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->mr = MICRON_V_MR_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ }
}
diff --git a/board/corscience/tricorder/tricorder.h b/board/corscience/tricorder/tricorder.h
index 820a50c..67c35c5 100644
--- a/board/corscience/tricorder/tricorder.h
+++ b/board/corscience/tricorder/tricorder.h
@@ -75,8 +75,8 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO 42*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO 43*/\
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c
index c477962..39efe20 100644
--- a/board/enbw/enbw_cmc/enbw_cmc.c
+++ b/board/enbw/enbw_cmc/enbw_cmc.c
@@ -36,6 +36,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/sdmmc_defs.h>
#include <asm/arch/timer_defs.h>
+#include <asm/davinci_rtc.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/prodrive/pdnb3/Makefile b/board/ppcag/bg0900/Makefile
index 06120f3..74c6db5 100644
--- a/board/prodrive/pdnb3/Makefile
+++ b/board/ppcag/bg0900/Makefile
@@ -1,8 +1,12 @@
#
-# (C) Copyright 2006
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := flash.o pdnb3.o nand.o
+ifndef CONFIG_SPL_BUILD
+obj-y := bg0900.o
+else
+obj-y := spl_boot.o
+endif
diff --git a/board/ppcag/bg0900/bg0900.c b/board/ppcag/bg0900/bg0900.c
new file mode 100644
index 0000000..06612fa
--- /dev/null
+++ b/board/ppcag/bg0900/bg0900.c
@@ -0,0 +1,86 @@
+/*
+ * PPC-AG BG0900 board
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP2 clock at 160MHz */
+ mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct eth_device *dev;
+ int ret;
+
+ ret = cpu_eth_init(bis);
+
+ /* BG0900 uses ENET_CLK PAD to drive FEC clock */
+ writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
+ &clkctrl_regs->hw_clkctrl_enet);
+
+ /* Reset FEC PHYs */
+ gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
+ udelay(200);
+ gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
+
+ ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+ if (ret) {
+ puts("FEC MXS: Unable to init FEC0\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC0");
+ if (!dev) {
+ puts("FEC MXS: Unable to get FEC0 device entry\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+#endif
diff --git a/board/ppcag/bg0900/spl_boot.c b/board/ppcag/bg0900/spl_boot.c
new file mode 100644
index 0000000..a04c955
--- /dev/null
+++ b/board/ppcag/bg0900/spl_boot.c
@@ -0,0 +1,153 @@
+/*
+ * PPC-AG BG0900 Boot setup
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* DUART */
+ MX28_PAD_PWM0__DUART_RX,
+ MX28_PAD_PWM1__DUART_TX,
+
+ /* GPMI NAND */
+ MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+ MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+
+ /* FEC0 */
+ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+ /* FEC0 Reset */
+ MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+ /* EMI */
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+ /* SPI2 (for SPI flash) */
+ MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_SS0__SSP2_D3 |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+};
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ /*
+ * DDR Controller Registers
+ * Manufacturer: Winbond
+ * Device Part Number: W972GG6JB-25I
+ * Clock Freq.: 200MHz
+ * Density: 2Gb
+ * Chip Selects: 1
+ * Number of Banks: 8
+ * Row address: 14
+ * Column address: 10
+ */
+
+ dram_vals[0x74 / 4] = 0x0102010A;
+ dram_vals[0x98 / 4] = 0x04005003;
+ dram_vals[0x9c / 4] = 0x090000c8;
+
+ dram_vals[0xa8 / 4] = 0x0036b009;
+ dram_vals[0xac / 4] = 0x03270612;
+
+ dram_vals[0xb0 / 4] = 0x02020202;
+ dram_vals[0xb4 / 4] = 0x00c80029;
+
+ dram_vals[0xc0 / 4] = 0x00011900;
+
+ dram_vals[0x12c / 4] = 0x07400300;
+ dram_vals[0x130 / 4] = 0x07400300;
+ dram_vals[0x2c4 / 4] = 0x02030303;
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c
deleted file mode 100644
index 75b5d05..0000000
--- a/board/prodrive/pdnb3/flash.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-
-#if !defined(CONFIG_FLASH_CFI_DRIVER)
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*
- * Prototypes
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-
-static inline ulong ld(ulong x)
-{
- ulong k = 0;
-
- while (x >>= 1)
- ++k;
-
- return k;
-}
-
-unsigned long flash_init(void)
-{
- unsigned long size;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++)
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN)
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
-
- /* Reconfigure CS0 to actual FLASH size */
- *IXP425_EXP_CS0 = (*IXP425_EXP_CS0 & ~0x00003C00) | ((ld(size) - 9) << 10);
-
- /* Monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
- /* Environment protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
- /* Redundant environment protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
- flash_info[0].size = size;
-
- return size;
-}
-
-#endif /* CONFIG_FLASH_CFI_DRIVER */
diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c
deleted file mode 100644
index e1d2c63..0000000
--- a/board/prodrive/pdnb3/nand.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-
-struct pdnb3_ndfc_regs {
- uchar cmd;
- uchar wait;
- uchar addr;
- uchar term;
- uchar data;
-};
-
-static u8 hwctl;
-static struct pdnb3_ndfc_regs *pdnb3_ndfc;
-
-#define readb(addr) *(volatile u_char *)(addr)
-#define readl(addr) *(volatile u_long *)(addr)
-#define writeb(d,addr) *(volatile u_char *)(addr) = (d)
-
-/*
- * The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to
- * the NAND devices. The NDFC has command, address and data registers that
- * when accessed will set up the NAND flash pins appropriately. We'll use the
- * hwcontrol function to save the configuration in a global variable.
- * We can then use this information in the read and write functions to
- * determine which NDFC register to access.
- *
- * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
- */
-static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE )
- hwctl |= 0x1;
- else
- hwctl &= ~0x1;
- if ( ctrl & NAND_ALE )
- hwctl |= 0x2;
- else
- hwctl &= ~0x2;
- if ( (ctrl & NAND_NCE) != NAND_NCE)
- writeb(0x00, &(pdnb3_ndfc->term));
- }
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-
-static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
-{
- return readb(&(pdnb3_ndfc->data));
-}
-
-static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++) {
- if (hwctl & 0x1)
- writeb(buf[i], &(pdnb3_ndfc->cmd));
- else if (hwctl & 0x2)
- writeb(buf[i], &(pdnb3_ndfc->addr));
- else
- writeb(buf[i], &(pdnb3_ndfc->data));
- }
-}
-
-static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- buf[i] = readb(&(pdnb3_ndfc->data));
-}
-
-static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- if (buf[i] != readb(&(pdnb3_ndfc->data)))
- return i;
-
- return 0;
-}
-
-static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
-{
- /*
- * Blocking read to wait for NAND to be ready
- */
- readb(&(pdnb3_ndfc->wait));
-
- /*
- * Return always true
- */
- return 1;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
-
- nand->ecc.mode = NAND_ECC_SOFT;
-
- /* Set address of NAND IO lines (Using Linear Data Access Region) */
- nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
- nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
- /* Reference hardware control function */
- nand->cmd_ctrl = pdnb3_nand_hwcontrol;
- nand->read_byte = pdnb3_nand_read_byte;
- nand->write_buf = pdnb3_nand_write_buf;
- nand->read_buf = pdnb3_nand_read_buf;
- nand->verify_buf = pdnb3_nand_verify_buf;
- nand->dev_ready = pdnb3_nand_dev_ready;
- return 0;
-}
-#endif
diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c
deleted file mode 100644
index fa320da..0000000
--- a/board/prodrive/pdnb3/pdnb3.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* predefine these here for FPGA programming (before including fpga.c) */
-#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
-#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
-#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
-#define OLD_VAL old_val
-
-static unsigned long old_val = 0;
-
-/*
- * include common fpga code (for prodrive boards)
- */
-#include "../common/fpga.c"
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
-
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
-
- /*
- * Setup GPIO's for FPGA programming
- */
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
-
- /*
- * Setup GPIO's for interrupts
- */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
-
- /*
- * Setup GPIO's for 33MHz clock output
- */
- *IXP425_GPIO_GPCLKR = 0x01FF0000;
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
-
- /*
- * Setup other chip select's
- */
- *IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
-
- return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts("Board: PDNB3");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return (0);
-}
-
-int do_fpga_boot(unsigned char *fpgadata)
-{
- unsigned char *dst;
- int status;
- int index;
- int i;
- ulong len = CONFIG_SYS_MALLOC_LEN;
-
- /*
- * Setup GPIO's for FPGA programming
- */
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
-
- /*
- * Save value so no readback is required upon programming
- */
- old_val = *IXP425_GPIO_GPOUTR;
-
- /*
- * First try to decompress fpga image (gzip compressed?)
- */
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf("Error: Image has to be gzipp'ed!\n");
- return -1;
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=5; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc('\n');
-
- free(dst);
-
- /*
- * Reset FPGA
- */
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
- udelay(10);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
-
- return (0);
-}
-
-int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr;
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- addr = simple_strtoul(argv[1], NULL, 16);
-
- return do_fpga_boot((unsigned char *)addr);
-}
-
-U_BOOT_CMD(
- fpga, 2, 0, do_fpga,
- "boot FPGA",
- "address size\n - boot FPGA with gzipped image at <address>"
-);
-
-#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
-extern struct pci_controller hose;
-extern void pci_ixp_init(struct pci_controller * hose);
-
-void pci_init_board(void)
-{
- extern void pci_ixp_init (struct pci_controller *hose);
-
- pci_ixp_init(&hose);
-}
-#endif
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index c2fc5a6..57fedab 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -28,6 +28,8 @@
#include <cpsw.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -485,6 +487,10 @@ int board_init(void)
STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
#endif
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
+
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
diff --git a/board/udoo/Makefile b/board/udoo/Makefile
new file mode 100644
index 0000000..80efada
--- /dev/null
+++ b/board/udoo/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := udoo.o
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
new file mode 100644
index 0000000..e9d6375
--- /dev/null
+++ b/board/udoo/udoo.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define WDT_EN IMX_GPIO_NR(5, 4)
+#define WDT_TRG IMX_GPIO_NR(3, 19)
+
+int dram_init(void)
+{
+ gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D19__GPIO_3_19,
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+static void setup_iomux_wdog(void)
+{
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+ gpio_direction_output(WDT_TRG, 0);
+ gpio_direction_output(WDT_EN, 1);
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1; /* Always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg.max_bus_width = 4;
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_wdog();
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Udoo\n");
+
+ return 0;
+}
diff --git a/board/wandboard/README b/board/wandboard/README
index 498db2f..1f678e1 100644
--- a/board/wandboard/README
+++ b/board/wandboard/README
@@ -3,8 +3,8 @@ U-Boot for Wandboard
This file contains information for the port of U-Boot to the Wandboard.
-Wandboard is a development board that has two variants: one version based
-on mx6 dual lite and another one based on mx6 solo.
+Wandboard is a development board that has three variants based on the following
+SoCs: mx6 quad, mx6 dual lite and mx6 solo.
For more details about Wandboard, please refer to:
http://www.wandboard.org/