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-rw-r--r--board/atmel/at91cap9adk/nand.c37
-rw-r--r--board/atmel/at91sam9260ek/nand.c37
-rw-r--r--board/atmel/at91sam9261ek/nand.c37
-rw-r--r--board/atmel/at91sam9263ek/nand.c37
-rw-r--r--board/atmel/at91sam9rlek/nand.c37
-rw-r--r--board/freescale/m5373evb/nand.c64
-rw-r--r--board/quad100hd/nand.c36
-rw-r--r--board/socrates/nand.c84
8 files changed, 153 insertions, 216 deletions
diff --git a/board/atmel/at91cap9adk/nand.c b/board/atmel/at91cap9adk/nand.c
index 0432ef1..1dec558 100644
--- a/board/atmel/at91cap9adk/nand.c
+++ b/board/atmel/at91cap9adk/nand.c
@@ -37,36 +37,35 @@
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
- switch (cmd) {
- case NAND_CTL_SETCLE:
- IO_ADDR_W |= MASK_CLE;
- break;
- case NAND_CTL_SETALE:
- IO_ADDR_W |= MASK_ALE;
- break;
- case NAND_CTL_CLRNCE:
- at91_set_gpio_value(AT91_PIN_PD15, 1);
- break;
- case NAND_CTL_SETNCE:
- at91_set_gpio_value(AT91_PIN_PD15, 0);
- break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
}
- this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
int board_nand_init(struct nand_chip *nand)
{
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
- nand->hwcontrol = at91cap9adk_nand_hwcontrol;
+ nand->cmd_ctrl = at91cap9adk_nand_hwcontrol;
nand->chip_delay = 20;
return 0;
diff --git a/board/atmel/at91sam9260ek/nand.c b/board/atmel/at91sam9260ek/nand.c
index 9738f0f..665e35c 100644
--- a/board/atmel/at91sam9260ek/nand.c
+++ b/board/atmel/at91sam9260ek/nand.c
@@ -37,27 +37,26 @@
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
- switch (cmd) {
- case NAND_CTL_SETCLE:
- IO_ADDR_W |= MASK_CLE;
- break;
- case NAND_CTL_SETALE:
- IO_ADDR_W |= MASK_ALE;
- break;
- case NAND_CTL_CLRNCE:
- at91_set_gpio_value(AT91_PIN_PC14, 1);
- break;
- case NAND_CTL_SETNCE:
- at91_set_gpio_value(AT91_PIN_PC14, 0);
- break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
}
- this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
- nand->hwcontrol = at91sam9260ek_nand_hwcontrol;
+ nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol;
nand->dev_ready = at91sam9260ek_nand_ready;
nand->chip_delay = 20;
diff --git a/board/atmel/at91sam9261ek/nand.c b/board/atmel/at91sam9261ek/nand.c
index 35b26db..fccb9d7 100644
--- a/board/atmel/at91sam9261ek/nand.c
+++ b/board/atmel/at91sam9261ek/nand.c
@@ -37,27 +37,26 @@
#define MASK_ALE (1 << 22) /* our ALE is AD22 */
#define MASK_CLE (1 << 21) /* our CLE is AD21 */
-static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
- switch (cmd) {
- case NAND_CTL_SETCLE:
- IO_ADDR_W |= MASK_CLE;
- break;
- case NAND_CTL_SETALE:
- IO_ADDR_W |= MASK_ALE;
- break;
- case NAND_CTL_CLRNCE:
- at91_set_gpio_value(AT91_PIN_PC14, 1);
- break;
- case NAND_CTL_SETNCE:
- at91_set_gpio_value(AT91_PIN_PC14, 0);
- break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
}
- this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
- nand->hwcontrol = at91sam9261ek_nand_hwcontrol;
+ nand->cmd_ctrl = at91sam9261ek_nand_hwcontrol;
nand->dev_ready = at91sam9261ek_nand_ready;
nand->chip_delay = 20;
diff --git a/board/atmel/at91sam9263ek/nand.c b/board/atmel/at91sam9263ek/nand.c
index 5079972..250ec7f 100644
--- a/board/atmel/at91sam9263ek/nand.c
+++ b/board/atmel/at91sam9263ek/nand.c
@@ -37,27 +37,26 @@
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
- switch (cmd) {
- case NAND_CTL_SETCLE:
- IO_ADDR_W |= MASK_CLE;
- break;
- case NAND_CTL_SETALE:
- IO_ADDR_W |= MASK_ALE;
- break;
- case NAND_CTL_CLRNCE:
- at91_set_gpio_value(AT91_PIN_PD15, 1);
- break;
- case NAND_CTL_SETNCE:
- at91_set_gpio_value(AT91_PIN_PD15, 0);
- break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
}
- this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
- nand->hwcontrol = at91sam9263ek_nand_hwcontrol;
+ nand->cmd_ctrl = at91sam9263ek_nand_hwcontrol;
nand->dev_ready = at91sam9263ek_nand_ready;
nand->chip_delay = 20;
diff --git a/board/atmel/at91sam9rlek/nand.c b/board/atmel/at91sam9rlek/nand.c
index 5af1a31..eb342b8 100644
--- a/board/atmel/at91sam9rlek/nand.c
+++ b/board/atmel/at91sam9rlek/nand.c
@@ -37,27 +37,26 @@
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
- switch (cmd) {
- case NAND_CTL_SETCLE:
- IO_ADDR_W |= MASK_CLE;
- break;
- case NAND_CTL_SETALE:
- IO_ADDR_W |= MASK_ALE;
- break;
- case NAND_CTL_CLRNCE:
- at91_set_gpio_value(AT91_PIN_PB6, 1);
- break;
- case NAND_CTL_SETNCE:
- at91_set_gpio_value(AT91_PIN_PB6, 0);
- break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ at91_set_gpio_value(AT91_PIN_PB6, !(ctrl & NAND_NCE));
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
}
- this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
- nand->hwcontrol = at91sam9rlek_nand_hwcontrol;
+ nand->cmd_ctrl = at91sam9rlek_nand_hwcontrol;
nand->dev_ready = at91sam9rlek_nand_ready;
nand->chip_delay = 20;
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index 344a614..404a9c3 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -36,64 +36,39 @@ DECLARE_GLOBAL_DATA_PTR;
#include <linux/mtd/mtd.h>
#define SET_CLE 0x10
-#define CLR_CLE ~SET_CLE
#define SET_ALE 0x08
-#define CLR_ALE ~SET_ALE
-static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
u32 nand_baseaddr = (u32) this->IO_ADDR_W;
- switch (cmd) {
- case NAND_CTL_SETNCE:
- case NAND_CTL_CLRNCE:
- break;
- case NAND_CTL_SETCLE:
- nand_baseaddr |= SET_CLE;
- break;
- case NAND_CTL_CLRCLE:
- nand_baseaddr &= CLR_CLE;
- break;
- case NAND_CTL_SETALE:
- nand_baseaddr |= SET_ALE;
- break;
- case NAND_CTL_CLRALE:
- nand_baseaddr |= CLR_ALE;
- break;
- case NAND_CTL_SETWP:
- fbcs->csmr2 |= FBCS_CSMR_WP;
- break;
- case NAND_CTL_CLRWP:
- fbcs->csmr2 &= ~FBCS_CSMR_WP;
- break;
- }
- this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
-}
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ IO_ADDR_W &= ~(SET_ALE | SE_CLE);
-static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
- struct nand_chip *this = mtdinfo->priv;
- *((volatile u8 *)(this->IO_ADDR_W)) = byte;
-}
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= SET_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= SET_ALE;
-static u8 nand_read_byte(struct mtd_info *mtdinfo)
-{
- struct nand_chip *this = mtdinfo->priv;
- return (u8) (*((volatile u8 *)this->IO_ADDR_R));
-}
+ at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
+ this->IO_ADDR_W = (void *)IO_ADDR_W;
-static int nand_dev_ready(struct mtd_info *mtdinfo)
-{
- return 1;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
int board_nand_init(struct nand_chip *nand)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
*((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
+ fbcs->csmr2 &= ~FBCS_CSMR_WP;
/* set up pin configuration */
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
@@ -103,11 +78,8 @@ int board_nand_init(struct nand_chip *nand)
gpio->podr_timer = 0;
nand->chip_delay = 50;
- nand->eccmode = NAND_ECC_SOFT;
- nand->hwcontrol = nand_hwcontrol;
- nand->read_byte = nand_read_byte;
- nand->write_byte = nand_write_byte;
- nand->dev_ready = nand_dev_ready;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = nand_hwcontrol;
return 0;
}
diff --git a/board/quad100hd/nand.c b/board/quad100hd/nand.c
index a36b89d..766ee95 100644
--- a/board/quad100hd/nand.c
+++ b/board/quad100hd/nand.c
@@ -25,35 +25,25 @@
#include <config.h>
#if defined(CONFIG_CMD_NAND)
#include <asm/gpio.h>
+#include <asm/io.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
-static void quad100hd_hwcontrol(struct mtd_info *mtd, int cmd)
+static void quad100hd_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
{
- switch(cmd) {
- case NAND_CTL_SETCLE:
- gpio_write_bit(CFG_NAND_CLE, 1);
- break;
- case NAND_CTL_CLRCLE:
- gpio_write_bit(CFG_NAND_CLE, 0);
- break;
+ struct nand_chip *this = mtd->priv;
- case NAND_CTL_SETALE:
- gpio_write_bit(CFG_NAND_ALE, 1);
- break;
- case NAND_CTL_CLRALE:
- gpio_write_bit(CFG_NAND_ALE, 0);
- break;
-
- case NAND_CTL_SETNCE:
- gpio_write_bit(CFG_NAND_CE, 0);
- break;
- case NAND_CTL_CLRNCE:
- gpio_write_bit(CFG_NAND_CE, 1);
- break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ gpio_write_bit(CFG_NAND_CLE, !!(ctrl & NAND_CLE));
+ gpio_write_bit(CFG_NAND_ALE, !!(ctrl & NAND_ALE));
+ gpio_write_bit(CFG_NAND_CE, !(ctrl & NAND_NCE));
}
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
static int quad100hd_nand_ready(struct mtd_info *mtd)
@@ -67,9 +57,9 @@ static int quad100hd_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
/* Set address of hardware control function */
- nand->hwcontrol = quad100hd_hwcontrol;
+ nand->cmd_ctrl = quad100hd_hwcontrol;
nand->dev_ready = quad100hd_nand_ready;
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
/* 15 us command delay time */
nand->chip_delay = 20;
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index fc82ecb..6ec53f8 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -31,22 +31,20 @@
static int state;
static void nand_write_byte(struct mtd_info *mtd, u_char byte);
static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
-static void nand_write_word(struct mtd_info *mtd, u16 word);
static u_char nand_read_byte(struct mtd_info *mtd);
static u16 nand_read_word(struct mtd_info *mtd);
static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
static int nand_device_ready(struct mtd_info *mtdinfo);
-static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd);
#define FPGA_NAND_CMD_MASK (0x7 << 28)
-#define FPGA_NAND_CMD_COMMAND (0x0 << 28)
+#define FPGA_NAND_CMD_COMMAND (0x0 << 28)
#define FPGA_NAND_CMD_ADDR (0x1 << 28)
#define FPGA_NAND_CMD_READ (0x2 << 28)
#define FPGA_NAND_CMD_WRITE (0x3 << 28)
#define FPGA_NAND_BUSY (0x1 << 15)
#define FPGA_NAND_ENABLE (0x1 << 31)
-#define FPGA_NAND_DATA_SHIFT 16
+#define FPGA_NAND_DATA_SHIFT 16
/**
* nand_write_byte - write one byte to the chip
@@ -59,16 +57,6 @@ static void nand_write_byte(struct mtd_info *mtd, u_char byte)
}
/**
- * nand_write_word - write one word to the chip
- * @mtd: MTD device structure
- * @word: data word to write
- */
-static void nand_write_word(struct mtd_info *mtd, u16 word)
-{
- nand_write_buf(mtd, (const uchar *)&word, sizeof(word));
-}
-
-/**
* nand_write_buf - write buffer to chip
* @mtd: MTD device structure
* @buf: data buffer
@@ -78,18 +66,10 @@ static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
int i;
struct nand_chip *this = mtd->priv;
- long val;
-
- if ((state & FPGA_NAND_CMD_MASK) == FPGA_NAND_CMD_MASK) {
- /* Write data */
- val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_WRITE;
- } else {
- /* Write address or command */
- val = state;
- }
for (i = 0; i < len; i++) {
- out_be32(this->IO_ADDR_W, val | (buf[i] << FPGA_NAND_DATA_SHIFT));
+ out_be32(this->IO_ADDR_W,
+ state | (buf[i] << FPGA_NAND_DATA_SHIFT));
}
}
@@ -148,7 +128,7 @@ static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
for (i = 0; i < len; i++) {
if (buf[i] != nand_read_byte(mtd));
- return -EFAULT;
+ return -EFAULT;
}
return 0;
}
@@ -171,42 +151,42 @@ static int nand_device_ready(struct mtd_info *mtdinfo)
* @mtd: MTD device structure
* @cmd: Command
*/
-static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
+ if (ctrl & NAND_CTRL_CHANGE) {
+ state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE);
+
+ switch (ctrl & (NAND_ALE | NAND_CLE)) {
+ case 0:
+ state |= FPGA_NAND_CMD_WRITE;
+ break;
+
+ case NAND_ALE:
+ state |= FPGA_NAND_CMD_ADDR;
+ break;
- switch(cmd) {
- case NAND_CTL_CLRALE:
- state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */
- break;
- case NAND_CTL_CLRCLE:
- state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */
- break;
- case NAND_CTL_SETCLE:
- state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_COMMAND;
- break;
- case NAND_CTL_SETALE:
- state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_ADDR;
- break;
- case NAND_CTL_SETNCE:
- state |= FPGA_NAND_ENABLE;
- break;
- case NAND_CTL_CLRNCE:
- state &= ~FPGA_NAND_ENABLE;
- break;
- default:
- printf("%s: unknown cmd %#x\n", __FUNCTION__, cmd);
- break;
+ case NAND_CLE:
+ state |= FPGA_NAND_CMD_COMMAND;
+ break;
+
+ default:
+ printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
+ }
+
+ if (ctrl & NAND_NCE)
+ state |= FPGA_NAND_ENABLE;
}
+
+ if (cmd != NAND_CMD_NONE)
+ nand_write_byte(mtdinfo, cmd);
}
int board_nand_init(struct nand_chip *nand)
{
- nand->hwcontrol = nand_hwcontrol;
- nand->eccmode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = nand_hwcontrol;
+ nand->ecc.mode = NAND_ECC_SOFT;
nand->dev_ready = nand_device_ready;
- nand->write_byte = nand_write_byte;
nand->read_byte = nand_read_byte;
- nand->write_word = nand_write_word;
nand->read_word = nand_read_word;
nand->write_buf = nand_write_buf;
nand->read_buf = nand_read_buf;
generated by cgit v1.1 at 2024-11-01 13:58:06 +0000