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-rw-r--r--board/sunxi/Kconfig58
-rw-r--r--board/sunxi/MAINTAINERS32
-rw-r--r--board/sunxi/board.c254
-rw-r--r--board/sunxi/gmac.c22
4 files changed, 328 insertions, 38 deletions
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 2fcab60..88e3358 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -212,6 +212,25 @@ config MMC3_CD_PIN
---help---
See MMC0_CD_PIN help text.
+config MMC1_PINS
+ string "Pins for mmc1"
+ default ""
+ ---help---
+ Set the pins used for mmc1, when applicable. This takes a string in the
+ format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
+
+config MMC2_PINS
+ string "Pins for mmc2"
+ default ""
+ ---help---
+ See MMC1_PINS help text.
+
+config MMC3_PINS
+ string "Pins for mmc3"
+ default ""
+ ---help---
+ See MMC1_PINS help text.
+
config MMC_SUNXI_SLOT_EXTRA
int "mmc extra slot number"
default -1
@@ -229,7 +248,6 @@ config USB0_VBUS_PIN
config USB0_VBUS_DET
string "Vbus detect pin for usb0 (otg)"
- depends on USB_MUSB_SUNXI
default ""
---help---
Set the Vbus detect pin for usb0 (otg). This takes a string in the
@@ -251,6 +269,44 @@ config USB2_VBUS_PIN
---help---
See USB1_VBUS_PIN help text.
+config I2C0_ENABLE
+ bool "Enable I2C/TWI controller 0"
+ default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+ default n if MACH_SUN6I || MACH_SUN8I
+ ---help---
+ This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
+ its clock and setting up the bus. This is especially useful on devices
+ with slaves connected to the bus or with pins exposed through e.g. an
+ expansion port/header.
+
+config I2C1_ENABLE
+ bool "Enable I2C/TWI controller 1"
+ default n
+ ---help---
+ See I2C0_ENABLE help text.
+
+config I2C2_ENABLE
+ bool "Enable I2C/TWI controller 2"
+ default n
+ ---help---
+ See I2C0_ENABLE help text.
+
+if MACH_SUN6I || MACH_SUN7I
+config I2C3_ENABLE
+ bool "Enable I2C/TWI controller 3"
+ default n
+ ---help---
+ See I2C0_ENABLE help text.
+endif
+
+if MACH_SUN7I
+config I2C4_ENABLE
+ bool "Enable I2C/TWI controller 4"
+ default n
+ ---help---
+ See I2C0_ENABLE help text.
+endif
+
config VIDEO
boolean "Enable graphical uboot console on HDMI, LCD or VGA"
default y
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index be48213..75e8b5a 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -42,15 +42,18 @@ F: configs/Ippo_q8h_v1_2_defconfig
A20-OLINUXINO-LIME BOARD
M: FUKAUMI Naoki <naobsd@gmail.com>
S: Maintained
-F: board/sunxi/dram_a20_olinuxino_l.c
F: configs/A20-OLinuXino-Lime_defconfig
A20-OLINUXINO-LIME2 BOARD
M: Iain Paton <ipaton0@gmail.com>
S: Maintained
-F: board/sunxi/dram_a20_olinuxino_l2.c
F: configs/A20-OLinuXino-Lime2_defconfig
+AINOL AW1 BOARD
+M: Paul Kocialkowski <contact@paulk.fr>
+S: Maintained
+F: configs/Ainol_AW1_defconfig
+
AMPE A76 BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
@@ -84,11 +87,20 @@ M: Chen-Yu Tsai <wens@csie.org>
S: Maintained
F: configs/Hummingbird_A31_defconfig
-INET-86VS BOARD
+INET 3F BOARD
+M: Paul Kocialkowski <contact@paulk.fr>
+S: Maintained
+F: configs/iNet_3F_defconfig
+
+INET 3W BOARD
+M: Paul Kocialkowski <contact@paulk.fr>
+S: Maintained
+F: configs/iNet_3W_defconfig
+
+INET 86VS BOARD
M: Michal Suchanek <hramrach@gmail.com>
S: Maintained
-F: board/sunxi/dram_inet_86vs.c
-F: configs/Inet_86VS_defconfig
+F: configs/iNet_86VS_defconfig
IPPO-Q8H-V5 BOARD
M: Chen-Yu Tsai <wens@csie.org>
@@ -120,6 +132,11 @@ M: Ian Campbell <ijc@hellion.org.uk>
S: Maintained
F: configs/Mele_M5_defconfig
+MIXTILE-LOFTQ BOARD
+M: Phil Han <pengphei@sina.com>
+S: Maintained
+F: configs/mixtile_loftq_defconfig
+
MK808C BOARD
M: Marcus Cooper <codekipper@gmail.com>
S: Maintained
@@ -144,3 +161,8 @@ WEXLER-TAB7200 BOARD
M: Aleksei Mamlin <mamlinav@gmail.com>
S: Maintained
F: configs/Wexler_TAB7200_defconfig
+
+YONES TOPTECH BD1078 BOARD
+M: Paul Kocialkowski <contact@paulk.fr>
+S: Maintained
+F: configs/Yones_Toptech_BD1078_defconfig
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 808bf82..dda50b5 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -71,42 +71,163 @@ int dram_init(void)
static void mmc_pinmux_setup(int sdc)
{
unsigned int pin;
+ __maybe_unused int pins;
switch (sdc) {
case 0:
- /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
+ /* SDC0: PF0-PF5 */
for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
break;
case 1:
- /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */
+ pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+ if (pins == SUNXI_GPIO_H) {
+ /* SDC1: PH22-PH-27 */
+ for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ } else {
+ /* SDC1: PG0-PG5 */
+ for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ }
+#elif defined(CONFIG_MACH_SUN5I)
+ /* SDC1: PG3-PG8 */
for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1);
+ sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+#elif defined(CONFIG_MACH_SUN6I)
+ /* SDC1: PG0-PG5 */
+ for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#elif defined(CONFIG_MACH_SUN8I)
+ if (pins == SUNXI_GPIO_D) {
+ /* SDC1: PD2-PD7 */
+ for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ } else {
+ /* SDC1: PG0-PG5 */
+ for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ }
+#endif
break;
case 2:
- /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
+ pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+ /* SDC2: PC6-PC11 */
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+#elif defined(CONFIG_MACH_SUN5I)
+ if (pins == SUNXI_GPIO_E) {
+ /* SDC2: PE4-PE9 */
+ for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ } else {
+ /* SDC2: PC6-PC15 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ }
+#elif defined(CONFIG_MACH_SUN6I)
+ if (pins == SUNXI_GPIO_A) {
+ /* SDC2: PA9-PA14 */
+ for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ } else {
+ /* SDC2: PC6-PC15, PC24 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+ }
+#elif defined(CONFIG_MACH_SUN8I)
+ /* SDC2: PC5-PC6, PC8-PC16 */
+ for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+
+ for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#endif
break;
case 3:
- /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
+ pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+ /* SDC3: PI4-PI9 */
for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#elif defined(CONFIG_MACH_SUN6I)
+ if (pins == SUNXI_GPIO_A) {
+ /* SDC3: PA9-PA14 */
+ for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ } else {
+ /* SDC3: PC6-PC15, PC24 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
+ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+ }
+#endif
break;
default:
@@ -155,9 +276,82 @@ int board_mmc_init(bd_t *bis)
void i2c_init_board(void)
{
- sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
+#ifdef CONFIG_I2C0_ENABLE
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
+ clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUN6I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
+ clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUN8I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
clock_twi_onoff(0, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C1_ENABLE
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
+ clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN5I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
+ clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN6I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
+ clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN8I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
+ clock_twi_onoff(1, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C2_ENABLE
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
+ clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN5I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
+ clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN6I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
+ clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN8I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
+ clock_twi_onoff(2, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C3_ENABLE
+#if defined(CONFIG_MACH_SUN6I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
+ clock_twi_onoff(3, 1);
+#elif defined(CONFIG_MACH_SUN7I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
+ sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
+ clock_twi_onoff(3, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C4_ENABLE
+#if defined(CONFIG_MACH_SUN7I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
+ sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
+ clock_twi_onoff(4, 1);
+#endif
+#endif
+
#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
@@ -241,23 +435,41 @@ static struct musb_hdrc_platform_data musb_plat = {
};
#endif
+#ifdef CONFIG_USB_GADGET
+int g_dnl_board_usb_cable_connected(void)
+{
+ return sunxi_usbc_vbus_detect(0);
+}
+#endif
+
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
+ char serial_string[17] = { 0 };
unsigned int sid[4];
+ uint8_t mac_addr[6];
+ int ret;
+
+ ret = sunxi_get_sid(sid);
+ if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
+ if (!getenv("ethaddr")) {
+ /* Non OUI / registered MAC address */
+ mac_addr[0] = 0x02;
+ mac_addr[1] = (sid[0] >> 0) & 0xff;
+ mac_addr[2] = (sid[3] >> 24) & 0xff;
+ mac_addr[3] = (sid[3] >> 16) & 0xff;
+ mac_addr[4] = (sid[3] >> 8) & 0xff;
+ mac_addr[5] = (sid[3] >> 0) & 0xff;
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
- if (!getenv("ethaddr") && sunxi_get_sid(sid) == 0 &&
- sid[0] != 0 && sid[3] != 0) {
- uint8_t mac_addr[6];
-
- mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
- mac_addr[1] = (sid[0] >> 0) & 0xff;
- mac_addr[2] = (sid[3] >> 24) & 0xff;
- mac_addr[3] = (sid[3] >> 16) & 0xff;
- mac_addr[4] = (sid[3] >> 8) & 0xff;
- mac_addr[5] = (sid[3] >> 0) & 0xff;
+ if (!getenv("serial#")) {
+ snprintf(serial_string, sizeof(serial_string),
+ "%08x%08x", sid[0], sid[3]);
- eth_setenv_enetaddr("ethaddr", mac_addr);
+ setenv("serial#", serial_string);
+ }
}
#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 8849132..63a7360 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -39,45 +39,45 @@ int sunxi_gmac_initialize(bd_t *bis)
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
continue;
#endif
- sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
+ sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
#elif defined CONFIG_RGMII
/* Configure sun6i RGMII mode pin mux settings */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
#elif defined CONFIG_GMII
/* Configure sun6i GMII mode pin mux settings */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 2);
}
#else
/* Configure sun6i MII mode pin mux settings */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
- sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
#endif
#ifdef CONFIG_RGMII
generated by cgit v1.1 at 2024-11-14 04:21:10 +0000