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-rw-r--r--board/tqc/tqm85xx/sdram.c37
-rw-r--r--board/tqc/tqm85xx/tlb.c47
2 files changed, 0 insertions, 84 deletions
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index 260cd1c..b2d3185 100644
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -394,43 +394,6 @@ static phys_size_t sdram_setup(int casl)
return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
}
-phys_size_t initdram (int board_type)
-{
- phys_size_t dram_size = 0;
-
-#if defined(CONFIG_DDR_DLL)
- /*
- * This DLL-Override only used on TQM8540 and TQM8560
- */
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int i, x;
-
- x = 10;
-
- /*
- * Work around to stabilize DDR DLL
- */
- gur->ddrdllcr = 0x81000000;
- asm ("sync; isync; msync");
- udelay (200);
- while (gur->ddrdllcr != 0x81000100) {
- gur->devdisr = gur->devdisr | 0x00010000;
- asm ("sync; isync; msync");
- for (i = 0; i < x; i++)
- ;
- gur->devdisr = gur->devdisr & 0xfff7ffff;
- asm ("sync; isync; msync");
- x++;
- }
- }
-#endif
-
- dram_size = fixed_sdram();
-
- return dram_size;
-}
-
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index 75dd348..f9f8cc9 100644
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -120,36 +120,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
-
-#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE)
- /*
- * TLB 7+8: 2G DDR, cache enabled
- * 0x00000000 2G DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_1G, 1),
-
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-#else
- /*
- * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
- * 0x00000000 512M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 7, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 8, BOOKE_PAGESZ_256M, 1),
-#endif
#ifdef CONFIG_PCIE1
/*
* TLB 9: 16M Non-cacheable, guarded
@@ -228,23 +198,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 7, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 8+9: 512M DDR, cache disabled (needed for memory test)
- * 0x00000000 512M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 8, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 9, BOOKE_PAGESZ_256M, 1),
-
#ifdef CONFIG_PCIE1
/*
* TLB 10: 16M Non-cacheable, guarded