diff options
Diffstat (limited to 'board/ti')
| -rw-r--r-- | board/ti/ks2_evm/Makefile | 1 | ||||
| -rw-r--r-- | board/ti/ks2_evm/board.c | 3 | ||||
| -rw-r--r-- | board/ti/ks2_evm/board_k2g.c | 6 | ||||
| -rw-r--r-- | board/ti/ks2_evm/ddr3_k2g.c | 64 |
4 files changed, 70 insertions, 4 deletions
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index b7c5402..d60496e 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o obj-$(CONFIG_K2L_EVM) += board_k2l.o obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o obj-$(CONFIG_K2G_EVM) += board_k2g.o +obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index bee42bc..7a5509a 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -43,7 +43,8 @@ int dram_init(void) gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); - ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); + if (ddr3_size) + ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); return 0; } diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 2d4602f..81cef70 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -23,7 +23,7 @@ static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4}; static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4}; static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; -static struct pll_init_data ddr3_pll_config = {DDR3_PLL, 250, 3, 10}; +static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10}; struct pll_init_data *get_pll_init_data(int pll) { @@ -34,7 +34,7 @@ struct pll_init_data *get_pll_init_data(int pll) data = &main_pll_config; break; case TETRIS_PLL: - data = &tetris_pll_config[speed]; + data = &tetris_pll_config; break; case NSS_PLL: data = &nss_pll_config; @@ -43,7 +43,7 @@ struct pll_init_data *get_pll_init_data(int pll) data = &uart_pll_config; break; case DDR3_PLL: - data = &ddr_pll_config; + data = &ddr3_pll_config; break; default: data = NULL; diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c new file mode 100644 index 0000000..344961d --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2g.c @@ -0,0 +1,64 @@ +/* + * K2G: DDR3 initialization + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include "ddr3_cfg.h" +#include <asm/arch/ddr3.h> + +struct ddr3_phy_config ddr3phy_800_2g = { + .pllcr = 0x000DC000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, + .ptr3 = 0x06C30D40ul, + .ptr4 = 0x06413880ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x550F6644ul, + .dtpr1 = 0x328341E0ul, + .dtpr2 = 0x50022A00ul, + .mr0 = 0x00001430ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F03D09ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x00000F81ul, +}; + +struct ddr3_emif_config ddr3_800_2g = { + .sdcfg = 0x62005662ul, + .sdtim1 = 0x0A385033ul, + .sdtim2 = 0x00001CA5ul, + .sdtim3 = 0x21ADFF32ul, + .sdtim4 = 0x533F067Ful, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00000C34ul, +}; + +u32 ddr3_init(void) +{ + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g); + + return 0; +} + +inline int ddr3_get_size(void) +{ + return 2; +} |