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Diffstat (limited to 'board/jse/sdram.c')
-rw-r--r--board/jse/sdram.c36
1 files changed, 18 insertions, 18 deletions
diff --git a/board/jse/sdram.c b/board/jse/sdram.c
index bb6f85e..88fdd84 100644
--- a/board/jse/sdram.c
+++ b/board/jse/sdram.c
@@ -35,59 +35,59 @@ phys_size_t initdram (int board_type)
/* Configure the SDRAMS */
/* disable memory controller */
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
udelay (500);
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
- mtdcr (SDRAM0_CFGADDR, mem_besra);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
- mtdcr (SDRAM0_CFGADDR, mem_besrb);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Clear SDRAM0_ECCCFG (disable ECC) */
- mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
- mtdcr (SDRAM0_CFGADDR, mem_eccerr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
- mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, 0x010a4016);
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, 0x00084001);
/* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
mtdcr (SDRAM0_CFGDATA, 0x04084001);
/* Memory Bank 2 Config == BE=0 */
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* Memory Bank 3 Config == BE=0 */
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* refresh timer = 0x400 */
- mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, 0x04000000);
/* Power management idle timer set to the default. */
- mtdcr (SDRAM0_CFGADDR, mem_pmit);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
mtdcr (SDRAM0_CFGDATA, 0x07c00000);
udelay (500);
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, 0x80e00000);
return SDRAM_LEN;
@@ -108,7 +108,7 @@ int testdram (void)
#ifdef DEBUG
printf ("SDRAM Controller Registers --\n");
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_CFG : 0x%08x\n", val);
@@ -116,19 +116,19 @@ int testdram (void)
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_STATUS: 0x%08x\n", val);
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_B0CR : 0x%08x\n", val);
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_B1CR : 0x%08x\n", val);
- mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_TR : 0x%08x\n", val);
- mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_RTR : 0x%08x\n", val);
#endif