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-rw-r--r--board/isee/common/igep_common.h31
-rw-r--r--board/isee/igep0046/Makefile1
-rw-r--r--board/isee/igep0046/igep0046.c445
-rw-r--r--board/isee/igep0046/igep0046_eeprom.c62
-rw-r--r--board/isee/igep0046/igep0046_eeprom.h17
-rw-r--r--board/isee/igep0046/mx6dl_igep0046_4x512.cfg131
-rw-r--r--board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg204
7 files changed, 740 insertions, 151 deletions
diff --git a/board/isee/common/igep_common.h b/board/isee/common/igep_common.h
new file mode 100644
index 0000000..1d7e20d
--- /dev/null
+++ b/board/isee/common/igep_common.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * Common resources for igep boards
+ *
+ * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __COMMON_HEADER__
+#define __COMMON_HEADER__
+
+struct igep_mf_setup {
+ u32 magic_id; /* eeprom magic id */
+ u32 crc32; /* eeprom crc32 */
+ char board_uuid [37]; /* board identifier */
+ char board_pid [20]; /* product identifier */
+ char name [20]; /* board name */
+ char model [10]; /* board model */
+ char pcb_version [10]; /* board version */
+ char assembly_rev[10]; /* board revision */
+ char board_manufacturer[30]; /* board manufacturer */
+ char manf_of[10]; /* manufacturer order of fabrication */
+ char manf_timestamp[16]; /* manufacturer timestamp */
+ char bmac0[6]; /* MAC 0 - default */
+ char bmac1[6]; /* MAC 1 */
+}__attribute__((packet));
+
+#endif
+
diff --git a/board/isee/igep0046/Makefile b/board/isee/igep0046/Makefile
index cc50bc4..29e6362 100644
--- a/board/isee/igep0046/Makefile
+++ b/board/isee/igep0046/Makefile
@@ -6,5 +6,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_IGEP0046_CFG_EEPROM) += igep0046_eeprom.o
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
obj-y += igep0046.o
diff --git a/board/isee/igep0046/igep0046.c b/board/isee/igep0046/igep0046.c
index 9e01afa..40a3d5f 100644
--- a/board/isee/igep0046/igep0046.c
+++ b/board/isee/igep0046/igep0046.c
@@ -1,35 +1,41 @@
/*
- * Config file for IGEP0046board
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
- * Copyright (C) 2017, ISEE S.L - https://www.isee.biz/
+ * Source file for IGEP0046 board
*
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <linux/errno.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mx6-ddr.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
-#include <asm/gpio.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx6-ddr.h>
+#include <i2c.h>
#include <asm/io.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
-#include <i2c.h>
#include "pfuze.h"
+#include "igep0046_eeprom.h"
+#include "../common/igep_common.h"
+#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
-
-/* MUX defines */
+/* MACRO MUX defines */
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -42,20 +48,54 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST )
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS | \
+ PAD_CTL_PUE | PAD_CTL_PKE)
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
#ifdef CONFIG_SYS_I2C
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
#define I2C_PMIC 1
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
#endif
+#ifdef CONFIG_USB_EHCI_MX6
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#endif
+
+#define PCB_CFG_0 IMX_GPIO_NR(3, 22)
+#define PCB_CFG_1 IMX_GPIO_NR(3, 23)
+#define PCB_CFG_2 IMX_GPIO_NR(3, 29)
+#define PCB_CFG_3 IMX_GPIO_NR(6, 31)
+#define PCB_REV_A 1
+#define PCB_REV_B 2
+#define PCB_REV_C 3
+#define PCB_REV_D10 4
+
+
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
+/* UART MUX */
+
+static iomux_v3_cfg_t const uart1_pads[] =
+{
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
static iomux_v3_cfg_t const uart2_pads[] =
{
@@ -63,7 +103,53 @@ static iomux_v3_cfg_t const uart2_pads[] =
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-
+/* SDIO MUX */
+iomux_v3_cfg_t const usdhc1_pads[] =
+{
+ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
+ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+/* eMMC MUX */
+iomux_v3_cfg_t const usdhc3_pads[] =
+{
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+/* Ethernet MUX */
+iomux_v3_cfg_t const enet_pads[] =
+{
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* Marvell Alaska PHY Reset */
+ MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+/* GPIO MISC MUX */
static iomux_v3_cfg_t const init_pads[] =
{
/* PCB GPIO to Detect Module Version */
@@ -78,7 +164,35 @@ static iomux_v3_cfg_t const init_pads[] =
MX6_PAD_DI0_PIN15__GPIO4_IO17 | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
};
+#ifdef CONFIG_BASE0040
+/* GPIO USB BASE0040 MUX */
+static iomux_v3_cfg_t const init_pads[] =
+{
+ MX6_PAD_CSI0_DAT4__GPIO5_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB_HUB_RESET
+ MX6_PAD_CSI0_DAT5__GPIO5_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB_PWR1
+ MX6_PAD_CSI0_DAT6__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB_PWR2
+ MX6_PAD_CSI0_DAT7__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB_PWR3
+};
+#endif
+
+/* EEPROM CONFIGURATION */
+struct igep_mf_setup igep0046_eeprom_config = {
+ .magic_id = 12345678,
+ .crc32 = 0,
+ .board_uuid = "1234578",
+ .board_pid = "12345678",
+ .name = "IGEP0046",
+ .model = "full",
+ .pcb_version = "RD",
+ .assembly_rev = "10",
+ .board_manufacturer = "(c) ISEE (www.isee.biz)",
+ .manf_of = "12345678",
+ .manf_timestamp = "10:38 10/11/2014",
+ .bmac0 = "012345",
+ .bmac1 = "678901"
+};
+/* I2C MUX */
#ifdef CONFIG_SYS_I2C
static struct i2c_pads_info i2c_pad_info1 =
{
@@ -118,10 +232,189 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}
-int checkboard(void)
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] =
+{
+ MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+#ifdef CONFIG_BASE0040
+static void reset_usb_hub(void)
+{
+ /* Reset USB HUB Base0040 */
+ gpio_direction_output(IMX_GPIO_NR(5, 22) , 1);
+ udelay(100); // delay in usec
+ gpio_direction_output(IMX_GPIO_NR(5, 22) , 0);
+ udelay(100); // delay in usec
+ gpio_set_value(IMX_GPIO_NR(5, 22), 1);
+ /* Activate USB_PWRx */
+ gpio_direction_output(IMX_GPIO_NR(5, 23), 1);
+ gpio_direction_output(IMX_GPIO_NR(5, 24), 1);
+ gpio_direction_output(IMX_GPIO_NR(5, 25), 1);
+ return 0;
+}
+#endif
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] =
+{
+ {USDHC1_BASE_ADDR},
+ {USDHC3_BASE_ADDR},
+};
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base)
+ {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = 1; /* eMMC/uSDHC3 is always present */
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ int i;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 SD1 (external SDIO)
+ * mmc1 SD3 (internal eMMC)
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
+ {
+ switch (i)
+ {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+static int reset_enet_phy(struct mii_dev *bus)
+{
+ /* Reset Marvell Alaska PHY */
+ gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
+ udelay(500);
+ gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+ return 0;
+}
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
{
+ /*
+ uint8_t mac_addr[6];
+ mac_addr[0] = 0;
+ mac_addr[1] = 1;
+ mac_addr[2] = 2;
+ mac_addr[3] = 3;
+ mac_addr[4] = 4;
+ mac_addr[5] = 5;
+ eth_setenv_enetaddr("ethaddr",mac_addr);
+ */
+
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ setup_iomux_enet();
+ //reset_enet_phy();
- puts("Module: IGEP0046\n");
+#ifdef CONFIG_FEC_MXC
+ bus = fec_get_miibus(base, -1);
+ if (!bus)
+ return 0;
+ bus->reset = reset_enet_phy;
+ phydev = phy_find_by_mask(bus, CONFIG_FEC_MXC_PHYADDR, PHY_INTERFACE_MODE_RGMII);
+ if (!phydev) {
+ free(bus);
+ puts("no PHY found\n");
+ return 0;
+ }
+ ret = fec_probe(bis, -1, base, bus, phydev);
+ if (ret) {
+ printf("FEC MXC: %s:failed\n", __func__);
+ free(phydev);
+ free(bus);
+ }
+ printf("%x - %s\n", phydev->addr, phydev->drv->name);
+#endif
+ return 0;
+}
+
+
+int checkboard(void)
+{
return 0;
}
@@ -133,28 +426,140 @@ int board_early_init_f(void)
imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
/* configure LEDS */
- gpio_set_value(IMX_GPIO_NR(4, 18), 1);
- gpio_set_value(IMX_GPIO_NR(4, 19), 1);
- gpio_set_value(IMX_GPIO_NR(4, 20), 1);
- gpio_set_value(IMX_GPIO_NR(4, 17), 1);
+ gpio_direction_output(IMX_GPIO_NR(4, 18), 0);
+ gpio_direction_output(IMX_GPIO_NR(4, 19), 1);
+ gpio_direction_output(IMX_GPIO_NR(4, 20), 0);
+ gpio_direction_output(IMX_GPIO_NR(4, 17), 1);
return 0;
}
int board_init(void)
{
-
+ u32 crc_value = 0;
+ u32 crc_save_value = 0;
#ifdef CONFIG_SYS_I2C
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
#endif
+
+#ifdef CONFIG_IGEP0046_CFG_EEPROM
+ if(check_eeprom() != 0){
+ printf("eeprom not found\n");
+ }else{
+
+ // Write configuration struct into eeprom
+ /*
+ igep0046_eeprom_config.crc32 = crc32(0, (const unsigned char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup));
+ if(!eeprom46_write_setup (0, (char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup))){
+ printf("eeprom: writintg done\n");
+ }
+ */
+ // Read configuration from eeprom
+ if(eeprom46_read_setup(0, (char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup))){
+ printf("eeprom: read fail\n");
+ }
+ // Verify crc32
+ crc_save_value = igep0046_eeprom_config.crc32;
+ igep0046_eeprom_config.crc32 = 0;
+ crc_value = crc32(0, (const unsigned char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup));
+ if(crc_save_value != crc_value){
+ printf("eeprom crc32 check loading mac from environment\n");
+
+ }else{
+ printf("crc32 OK! Loading mac\n");
+ eth_setenv_enetaddr("ethaddr",igep0046_eeprom_config.bmac0)
+ }
+ }
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
+#ifdef CONFIG_BASE0040
+ reset_usb_hub();
+#endif
+
return 0;
}
+
+static inline unsigned int pcb_version(void)
+{
+ unsigned int pcb_version_bit0, pcb_version_bit1,
+ pcb_version_bit2, pcb_version_bit3;
+
+ pcb_version_bit0 = gpio_get_value(PCB_CFG_0);
+ pcb_version_bit1 = gpio_get_value(PCB_CFG_1);
+ pcb_version_bit2 = gpio_get_value(PCB_CFG_2);
+ pcb_version_bit3 = gpio_get_value(PCB_CFG_3);
+
+ if (pcb_version_bit0 && pcb_version_bit1 \
+ && pcb_version_bit2 && pcb_version_bit3)
+ /* RA revision: 0b1111*/
+ return PCB_REV_A;
+ else if (!(pcb_version_bit0 || pcb_version_bit1 \
+ || pcb_version_bit2 || pcb_version_bit3))
+ /* RB revision: 0b0000*/
+ return PCB_REV_B;
+ else if (!(!(pcb_version_bit0) || pcb_version_bit1 \
+ || pcb_version_bit2 || pcb_version_bit3))
+ /* RC revision: 0b0001*/
+ return PCB_REV_C;
+ else if (!(pcb_version_bit0 || pcb_version_bit1 \
+ || pcb_version_bit2 || !(pcb_version_bit3)))
+ /* RD10 revision: 0b1000*/
+ return PCB_REV_D10;
+ else
+ return 0;
+}
+
int board_late_init(void)
{
- puts("Hola Manel\n");
checkboard();
+ puts("\n");
+ switch (pcb_version()) {
+ case PCB_REV_A:
+ puts("Board: MX6-IGEP0046 Rev A\n");
+ #ifdef CONFIG_MX6Q
+ setenv("fdt_file", "imx6q-igep-base0040ra1.dtb");
+ #elif CONFIG_MX6DL
+ setenv("fdt_file", "imx6dl-igep-base0040ra1.dtb");
+ #endif
+ break;
+ case PCB_REV_B:
+ puts("Board: MX6-IGEP0046 Rev B\n");
+ #ifdef CONFIG_MX6Q
+ setenv("fdt_file", "imx6q-igep-base0040rb2.dtb");
+ #elif CONFIG_MX6DL
+ setenv("fdt_file", "imx6dl-igep-base0040rb2.dtb");
+ #endif
+ break;
+ case PCB_REV_C:
+ puts("Board: MX6-IGEP0046 Rev C/D\n");
+ #ifdef CONFIG_MX6Q
+ setenv("fdt_file", "imx6q-igep-base0040rc2.dtb");
+ #elif CONFIG_MX6DL
+ setenv("fdt_file", "imx6dl-igep-base0040rc2.dtb");
+ #endif
+ break;
+ case PCB_REV_D10:
+ puts("Board: MX6-IGEP0046 Rev D10\n");
+ #ifdef CONFIG_MX6Q
+ setenv("fdt_file", "imx6q-igep-base0040rd102.dtb");
+ #elif CONFIG_MX6DL
+ setenv("fdt_file", "imx6dl-igep-base0040rd102.dtb");
+ #endif
+ break;
+ default:
+ puts("Board: ERROR unknown PCB revision\n");
+ setenv("fdt_file", "");
+ break;
+ }
+
+ return 0;
+
return 0;
}
diff --git a/board/isee/igep0046/igep0046_eeprom.c b/board/isee/igep0046/igep0046_eeprom.c
new file mode 100644
index 0000000..5fac831
--- /dev/null
+++ b/board/isee/igep0046/igep0046_eeprom.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * EEPROM support source file for igep0046
+ *
+ * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/sys_proto.h>
+
+
+int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size)
+{
+ u32 i;
+ u32 remain = size % 32;
+ u32 blocks = size / 32;
+ for (i=0; i < blocks; i++){
+ if(i2c_write(CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
+ return -1;
+ }
+ udelay(5000);
+ }
+ if(remain > 0){
+ if(i2c_write(CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
+ return -1;
+ else
+ udelay(5000);
+ }
+ return 0;
+}
+
+int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size)
+{
+ u32 i;
+ u32 remain = size % 32;
+ u32 blocks = size / 32;
+ for (i=0; i < blocks; i++){
+ if(i2c_read(CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
+ return -1;
+ }
+ }
+ if(remain > 0)
+ if(i2c_read(CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
+ return -1;
+ return 0;
+}
+
+int check_eeprom (void)
+{
+ i2c_set_bus_num(CONFIG_SYS_I2C_IGEP0046_CFG_BUS_NUM);
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR)) {
+ debug("Could not probe the EEPROM at 0x%x\n",
+ CONFIG_SYS_I2C_IGEP0046_CFG_BUS_ADDR);
+ return -1;
+ }
+ return 0;
+}
diff --git a/board/isee/igep0046/igep0046_eeprom.h b/board/isee/igep0046/igep0046_eeprom.h
new file mode 100644
index 0000000..0ed4f37
--- /dev/null
+++ b/board/isee/igep0046/igep0046_eeprom.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * 0046 EEPROM Definitions
+ *
+ * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EEPROM_BOARD_HELPER__
+#define __EEPROM_BOARD_HELPER__
+
+int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size);
+int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size);
+int check_eeprom (void);
+#endif
diff --git a/board/isee/igep0046/mx6dl_igep0046_4x512.cfg b/board/isee/igep0046/mx6dl_igep0046_4x512.cfg
deleted file mode 100644
index db8e8e4..0000000
--- a/board/isee/igep0046/mx6dl_igep0046_4x512.cfg
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer docs/README.imxmage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x020e0774 0x000C0000
-DATA 4 0x020e0754 0x00000000
-DATA 4 0x020e04ac 0x00020030
-DATA 4 0x020e04b0 0x00020030
-DATA 4 0x020e0464 0x00020030
-DATA 4 0x020e0490 0x00020030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0494 0x00020030
-DATA 4 0x020e04a0 0x00000000
-DATA 4 0x020e04b4 0x00003030
-DATA 4 0x020e04b8 0x00003030
-DATA 4 0x020e076c 0x00000030
-DATA 4 0x020e0750 0x00020000
-DATA 4 0x020e04bc 0x00000030
-DATA 4 0x020e04c0 0x00000030
-DATA 4 0x020e04c4 0x00000030
-DATA 4 0x020e04c8 0x00000030
-DATA 4 0x020e04cc 0x00000030
-DATA 4 0x020e04d0 0x00000030
-DATA 4 0x020e04d4 0x00000030
-DATA 4 0x020e04d8 0x00000030
-DATA 4 0x020e0760 0x00020000
-DATA 4 0x020e0764 0x00000030
-DATA 4 0x020e0770 0x00000030
-DATA 4 0x020e0778 0x00000030
-DATA 4 0x020e077c 0x00000030
-DATA 4 0x020e0780 0x00000030
-DATA 4 0x020e0784 0x00000030
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e0470 0x00020030
-DATA 4 0x020e0474 0x00020030
-DATA 4 0x020e0478 0x00020030
-DATA 4 0x020e047c 0x00020030
-DATA 4 0x020e0480 0x00020030
-DATA 4 0x020e0484 0x00020030
-DATA 4 0x020e0488 0x00020030
-DATA 4 0x020e048c 0x00020030
-DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-DATA 4 0x021b480c 0x001F001F
-DATA 4 0x021b4810 0x001F001F
-DATA 4 0x021b083c 0x4220021F
-DATA 4 0x021b0840 0x0207017E
-DATA 4 0x021b483c 0x4201020C
-DATA 4 0x021b4840 0x01660172
-DATA 4 0x021b0848 0x4A4D4E4D
-DATA 4 0x021b4848 0x4A4F5049
-DATA 4 0x021b0850 0x3F3C3D31
-DATA 4 0x021b4850 0x3238372B
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-DATA 4 0x021b0004 0x0002002D
-DATA 4 0x021b0008 0x00333030
-DATA 4 0x021b000c 0x696C5323
-DATA 4 0x021b0010 0xB66E8B63
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b0018 0x00081740
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0030 0x006C1023
-DATA 4 0x021b0040 0x00000047
-DATA 4 0x021b0000 0x841A0000
-DATA 4 0x021b001c 0x04008032
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x00048031
-DATA 4 0x021b001c 0x13208030
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0020 0x00007800
-DATA 4 0x021b0818 0x00022227
-DATA 4 0x021b4818 0x00022227
-DATA 4 0x021b0004 0x0002556D
-DATA 4 0x021b0404 0x00011006
-DATA 4 0x021b001c 0x00000000
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
diff --git a/board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg b/board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg
new file mode 100644
index 0000000..21e319f
--- /dev/null
+++ b/board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+//=============================================================================
+// Enable all clocks (they are disabled by ROM code)
+//=============================================================================
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+//=============================================================================
+// IOMUX
+//=============================================================================
+//DDR IO TYPE:
+DATA 4 0x020e0774 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+DATA 4 0x020e0754 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+
+//CLOCK:
+DATA 4 0x020e04ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
+DATA 4 0x020e04b0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
+
+//ADDRESS:
+DATA 4 0x020e0464 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
+DATA 4 0x020e0490 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
+DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
+
+//Control:
+DATA 4 0x020e0494 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
+DATA 4 0x020e04a0 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
+DATA 4 0x020e04b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+DATA 4 0x020e04b8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
+DATA 4 0x020e076c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
+
+//Data Strobes:
+DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+DATA 4 0x020e04bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
+DATA 4 0x020e04c0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
+DATA 4 0x020e04c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
+DATA 4 0x020e04c8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
+DATA 4 0x020e04cc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
+DATA 4 0x020e04d0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
+DATA 4 0x020e04d4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
+DATA 4 0x020e04d8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
+
+//Data:
+DATA 4 0x020e0760 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
+DATA 4 0x020e0764 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS
+DATA 4 0x020e0770 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS
+DATA 4 0x020e0778 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS
+DATA 4 0x020e077c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS
+DATA 4 0x020e0780 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS
+DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS
+DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS
+DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS
+
+DATA 4 0x020e0470 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+DATA 4 0x020e0474 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+DATA 4 0x020e0478 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
+DATA 4 0x020e047c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
+DATA 4 0x020e0480 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
+DATA 4 0x020e0484 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
+DATA 4 0x020e0488 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
+DATA 4 0x020e048c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
+
+
+//=============================================================================
+// DDR Controller Registers
+//=============================================================================
+// Manufacturer: Samsung
+// Device Part Number: K4B4G1646D-BMK00CV
+// Clock Freq.: MHz
+// Density per CS in Gb: 16
+// Chip Selects used: 1
+// Number of Banks: 8
+// Row address: 15
+// Column address: 10
+// Data bus width 64
+//=============================================================================
+DATA 4 0x021b001c 0x00008000 MMDC0_MDSCR, set the Configuration request bit during MMDC set up
+
+//=============================================================================
+// Calibration setup.
+//=============================================================================
+DATA 4 0x021b0800 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
+
+// For target board, may need to run write leveling calibration to fine tune these settings.
+DATA 4 0x021b080c 0x00530056
+DATA 4 0x021b0810 0x00440053
+DATA 4 0x021b480c 0x002B002B
+DATA 4 0x021b4810 0x0028003F
+
+////Read DQS Gating calibration
+DATA 4 0x021b083c 0x021C021C // MPDGCTRL0 PHY0
+DATA 4 0x021b0840 0x02140214 // MPDGCTRL1 PHY0
+DATA 4 0x021b483c 0x0178017C // MPDGCTRL0 PHY1
+DATA 4 0x021b4840 0x016C0170 // MPDGCTRL1 PHY1
+
+//Read calibration
+DATA 4 0x021b0848 0x46484C48 // MPRDDLCTL PHY0
+DATA 4 0x021b4848 0x42424842 // MPRDDLCTL PHY1
+
+//Write calibration
+DATA 4 0x021b0850 0x3434302E // MPWRDLCTL PHY0
+DATA 4 0x021b4850 0x3A303830 // MPWRDLCTL PHY1
+
+//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)
+DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3
+DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3
+DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3
+DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3
+DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3
+DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3
+DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3
+DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3
+
+//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented
+//DATA 4 0x021b08c0 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
+//DATA 4 0x021b48c0 0x24911492
+
+// Complete calibration by forced measurement:
+DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
+DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
+//=============================================================================
+// Calibration setup end
+//=============================================================================
+
+//MMDC init:
+DATA 4 0x021b0004 0x0002002D // MMDC0_MDPDC
+DATA 4 0x021b0008 0x00333040 // MMDC0_MDOTC
+DATA 4 0x021b000c 0x676B52F3 // MMDC0_MDCFG0
+DATA 4 0x021b0010 0xB66D8B63 // MMDC0_MDCFG1
+DATA 4 0x021b0014 0x01FF00DB // MMDC0_MDCFG2
+
+//MDMISC: RALAT kept to the high level of 5.
+//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
+//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
+//b. Small performence improvment
+DATA 4 0x021b0018 0x00011740 // MMDC0_MDMISC
+DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up
+DATA 4 0x021b002c 0x000026D2 // MMDC0_MDRWD
+DATA 4 0x021b0030 0x006B1023 // MMDC0_MDOR
+DATA 4 0x021b0040 0x00000047 // Chan0 CS0_END
+DATA 4 0x021b0000 0x841A0000 // MMDC0_MDCTL
+
+//Mode register writes
+DATA 4 0x021b001c 0x02008032 // MMDC0_MDSCR, MR2 write, CS0
+DATA 4 0x021b001c 0x00008033 // MMDC0_MDSCR, MR3 write, CS0
+DATA 4 0x021b001c 0x00048031 // MMDC0_MDSCR, MR1 write, CS0
+DATA 4 0x021b001c 0x15208030 // MMDC0_MDSCR, MR0write, CS0
+DATA 4 0x021b001c 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0
+
+//DATA 4 0x021b001c 0x0200803A // MMDC0_MDSCR, MR2 write, CS1
+//DATA 4 0x021b001c 0x0000803B // MMDC0_MDSCR, MR3 write, CS1
+//DATA 4 0x021b001c 0x00048039 // MMDC0_MDSCR, MR1 write, CS1
+//DATA 4 0x021b001c 0x15208038 // MMDC0_MDSCR, MR0write, CS1
+//DATA 4 0x021b001c 0x04008048 // MMDC0_MDSCR, ZQ calibration command sent to device on CS1
+
+DATA 4 0x021b0020 0x00007800 // MMDC0_MDREF
+
+DATA 4 0x021b0818 0x00022227 // DDR_PHY_P0_MPODTCTRL
+DATA 4 0x021b4818 0x00022227 // DDR_PHY_P1_MPODTCTRL
+
+DATA 4 0x021b0004 0x0002556D // MMDC0_MDPDC now SDCTL power down enabled
+
+DATA 4 0x021b0404 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
+
+DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
+
generated by cgit v1.1 at 2024-11-05 09:49:47 +0000