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Diffstat (limited to 'board/isee/igep0146/mx6ul_igep0146_1x128_nt.cfg')
| -rw-r--r-- | board/isee/igep0146/mx6ul_igep0146_1x128_nt.cfg | 173 |
1 files changed, 173 insertions, 0 deletions
diff --git a/board/isee/igep0146/mx6ul_igep0146_1x128_nt.cfg b/board/isee/igep0146/mx6ul_igep0146_1x128_nt.cfg new file mode 100644 index 0000000..e36084c --- /dev/null +++ b/board/isee/igep0146/mx6ul_igep0146_1x128_nt.cfg @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* New DDR type MT41K64M16TW-107 */ + +//============================================================================= +// Enable all clocks (they are disabled by ROM code) +//============================================================================= + +DATA 4 0x020c4068 0xffffffff // CCM_CCGR0 +DATA 4 0x020c406c 0xffffffff // CCM_CCGR1 +DATA 4 0x020c4070 0xffffffff // CCM_CCGR2 +DATA 4 0x020c4074 0xffffffff // CCM_CCGR3 +DATA 4 0x020c4078 0xffffffff // CCM_CCGR4 +DATA 4 0x020c407c 0xffffffff // CCM_CCGR5 +DATA 4 0x020c4080 0xffffffff // CCM_CCGR6 + +//============================================================================= +// IOMUX IMX6UL - MCIMX6G3CV +//============================================================================= + +//DDR IO TYPE: +DATA 4 0x020E04B4 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE +DATA 4 0x020E04AC 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE + +//CLOCK: +DATA 4 0x020E027C 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P + +//ADDRESS: +DATA 4 0x020E0250 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B +DATA 4 0x020E024C 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B +DATA 4 0x020E0490 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS + +//Control: +DATA 4 0x020E0288 0x000C0030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET +DATA 4 0x020E0270 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 +DATA 4 0x020E0260 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 +DATA 4 0x020E0264 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 +DATA 4 0x020E04A0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS + +//Data Strobes: +DATA 4 0x020E0494 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL +DATA 4 0x020E0280 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P +DATA 4 0x020E0284 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P + +//Data: +DATA 4 0x020E04B0 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE +DATA 4 0x020E0498 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS +DATA 4 0x020E04A4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS + +DATA 4 0x020E0244 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 +DATA 4 0x020E0248 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 + +//============================================================================= +// DDR Controller Registers +//============================================================================= +// Manufacturer: Micron +// Device Part Number: MT41K64M16TW-107 +// Clock Freq.: 933 MHz IMX6UL ensures data capture margin up to 400 Mhz +// Density per CS in Gb: 1 Gb +// Chip Selects used: 1 +// Number of Banks: 8 +// Row address: 13 +// Column address: 10 +// Data bus width 16 +//============================================================================= + +DATA 4 0x021B001C 0x00008000 // MMDC0_MDSCR Set the Configuration request bit during MMDC set up + +//============================================================================= +// Calibration setup. REVISAR +//============================================================================= + +DATA 4 0x021B0800 0xA1390003 // MMDC_MPZQHWCTRL Enable both one-time & periodic HW ZQ calibration. + +// For target board, may need to run write leveling calibration to fine tune these settings. +DATA 4 0x021B080C 0x00000000 // MMDC_MPWLDECTRL0 + +// Read DQS Gating calibration +DATA 4 0x021B083C 0x415C015C // MMDC_MPDGCTRL0 + +// Read Calibration +DATA 4 0x021B0848 0x40404040 // MMDC_MPRDDLCTL 0x40404244 + +// Write Calibration +DATA 4 0x021B0850 0x40404040 // MMDC_MPWRDLCTL 0x40405A58 + +// Read Data bit delay +DATA 4 0x021B081C 0x33333333 // MMDC_MPRDDQBY0DL +DATA 4 0x021B0820 0x33333333 // MMDC_MPRDDQBY1DL +DATA 4 0x021B082C 0xf3333333 // MMDC_MPWRDQBY0DL +DATA 4 0x021B0830 0xf3333333 // MMDC_MPWRDQBY1DL + +// Control Duty Cicle DQS of and primary clock CK0 +DATA 4 0x021B08C0 0x24922492 // MMDC_MPDCCR 0x00921012 24922492 0x00921012 + +// Complete Calibration by Forced Measurement +DATA 4 0x021B08b8 0x00008000 // MMDC_MPMUR0 + +//============================================================================= +// Calibration setup end +//============================================================================= + +// MMCD Init +DATA 4 0x021B0004 0x00020036 // MMDC_MDPDC +DATA 4 0x021B0008 0x1B333030 // MMDC_MDOTC +DATA 4 0x021B000C 0x676B52F3 // MMDC_MDCFG0 +DATA 4 0x021B0010 0xB66D0B63 // MMDC_MDCFG1 +DATA 4 0x021B0014 0x01FF00DB // MMDC_MDCFG2 + +//MDMISC: RALAT kept to the high level of 5. +//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: +//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 +//b. Small performence improvment +DATA 4 0x021B0018 0x00201740 // MMDC_MDMISC +DATA 4 0x021B001C 0x00000800 // MMDC_MDSCR +DATA 4 0x021B002C 0x000026D2 // MMDC_MDRWD +DATA 4 0x021B0030 0x006B1023 // MMDC_MDOR +DATA 4 0x021B0040 0x0000004F // MMDC_MDASP Initial value 3f = 0 Mb, increments of 256 Mb +DATA 4 0x021B0000 0x82180000 // MMDC_MDCTL + +// ???? +DATA 4 0x021B0890 0x00400000 // MMDC_MPPDCMPR2 DDR2 Only ??? + +// Mode Register writes +// MT41K64M16TW-107 is a DDR3 memory so there is no need to configure CS1, CS1 only used for LPDDR2 ?? +DATA 4 0x021B001C 0x02008032 // MMDC0_MDSCR, MR2 write, CS0 +DATA 4 0x021B001C 0x00008033 // MMDC0_MDSCR, MR3 write, CS0 +DATA 4 0x021B001C 0x00048031 // MMDC0_MDSCR, MR1 write, CS0 +DATA 4 0x021B001C 0x15208030 // MMDC0_MDSCR, MR0write, CS0 +DATA 4 0x021B001C 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0 + + +DATA 4 0x021B0020 0x00000800 // MMDC0_MDREF + +DATA 4 0x021B0818 0x00000227 // DDR_PHY_P0_MPODTCTRL + +DATA 4 0x021B0004 0x0002552D // MMDC0_MDPDC + +DATA 4 0x021B0404 0x00011006 // MMDC0_MAPSR + +DATA 4 0x021B001C 0x00000000 // MMDC0_MDSCR |