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-rw-r--r--board/freescale/mx6qarm2/mx6qarm2.c8
-rw-r--r--board/freescale/mx6qsabreauto/mx6qsabreauto.c38
-rw-r--r--board/freescale/mx6sabresd/mx6sabresd.c191
-rw-r--r--board/freescale/mx6slevk/mx6slevk.c54
-rw-r--r--board/freescale/mx6sxsabreauto/mx6sxsabreauto.c27
-rw-r--r--board/freescale/mx6sxsabresd/mx6sxsabresd.c51
-rw-r--r--board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c37
7 files changed, 406 insertions, 0 deletions
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index db605c7..15471c2 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -306,3 +306,11 @@ int checkboard(void)
return 0;
}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+/* no external pmic, always ldo_enable */
+void ldo_mode_set(int ldo_bypass)
+{
+ return;
+}
+#endif
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index e0ff4fc..de68caf 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -785,6 +785,44 @@ int power_init_board(void)
return 0;
}
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+ unsigned int value;
+ struct pmic *p = pmic_get("PFUZE100");
+
+ if (!p) {
+ printf("No PMIC found!\n");
+ return;
+ }
+
+ /* increase VDDARM/VDDSOC to support 1.2G chip */
+ if (check_1_2G()) {
+ ldo_bypass = 0; /* ldo_enable on 1.2G chip */
+ printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+
+ if (is_mx6dqp()) {
+ /* increase VDDARM to 1.425V */
+ pmic_reg_read(p, PFUZE100_SW2VOL, &value);
+ value &= ~0x3f;
+ value |= 0x29;
+ pmic_reg_write(p, PFUZE100_SW2VOL, value);
+ } else {
+ /* increase VDDARM to 1.425V */
+ pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+ value &= ~0x3f;
+ value |= 0x2d;
+ pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+ }
+ /* increase VDDSOC to 1.425V */
+ pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+ value &= ~0x3f;
+ value |= 0x2d;
+ pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+ }
+}
+#endif
+
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index d0db0c6..c09c9d2 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -1076,6 +1076,197 @@ int power_init_board(void)
}
#endif
+#ifdef CONFIG_LDO_BYPASS_CHECK
+#ifdef CONFIG_POWER
+void ldo_mode_set(int ldo_bypass)
+{
+ unsigned int value;
+ int is_400M;
+ unsigned char vddarm;
+ struct pmic *p = pmic_get("PFUZE100");
+
+ if (!p) {
+ printf("No PMIC found!\n");
+ return;
+ }
+
+ /* increase VDDARM/VDDSOC to support 1.2G chip */
+ if (check_1_2G()) {
+ ldo_bypass = 0; /* ldo_enable on 1.2G chip */
+ printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+ if (is_mx6dqp()) {
+ /* increase VDDARM to 1.425V */
+ pmic_reg_read(p, PFUZE100_SW2VOL, &value);
+ value &= ~0x3f;
+ value |= 0x29;
+ pmic_reg_write(p, PFUZE100_SW2VOL, value);
+ } else {
+ /* increase VDDARM to 1.425V */
+ pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+ value &= ~0x3f;
+ value |= 0x2d;
+ pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+ }
+ /* increase VDDSOC to 1.425V */
+ pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+ value &= ~0x3f;
+ value |= 0x2d;
+ pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+ }
+ /* switch to ldo_bypass mode , boot on 800Mhz */
+ if (ldo_bypass) {
+ prep_anatop_bypass();
+ if (is_mx6dqp()) {
+ /* decrease VDDARM for 400Mhz DQP:1.1V*/
+ pmic_reg_read(p, PFUZE100_SW2VOL, &value);
+ value &= ~0x3f;
+ value |= 0x1c;
+ pmic_reg_write(p, PFUZE100_SW2VOL, value);
+ } else {
+ /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
+ pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+ value &= ~0x3f;
+ if (is_mx6dl())
+ value |= 0x27;
+ else
+ value |= 0x20;
+
+ pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+ }
+ /* increase VDDSOC to 1.3V */
+ pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+ value &= ~0x3f;
+ value |= 0x28;
+ pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+ /*
+ * MX6Q/DQP:
+ * VDDARM:1.15V@800M; VDDSOC:1.175V@800M
+ * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
+ * MX6DL:
+ * VDDARM:1.175V@800M; VDDSOC:1.175V@800M
+ * VDDARM:1.075V@400M; VDDSOC:1.175V@400M
+ */
+ is_400M = set_anatop_bypass(2);
+ if (is_mx6dqp()) {
+ pmic_reg_read(p, PFUZE100_SW2VOL, &value);
+ value &= ~0x3f;
+ if (is_400M)
+ value |= 0x17;
+ else
+ value |= 0x1e;
+ pmic_reg_write(p, PFUZE100_SW2VOL, value);
+ }
+
+ if (is_400M) {
+ if (is_mx6dl())
+ vddarm = 0x1f;
+ else
+ vddarm = 0x1b;
+ } else {
+ if (is_mx6dl())
+ vddarm = 0x23;
+ else
+ vddarm = 0x22;
+ }
+ pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+ value &= ~0x3f;
+ value |= vddarm;
+ pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+ /* decrease VDDSOC to 1.175V */
+ pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+ value &= ~0x3f;
+ value |= 0x23;
+ pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+ finish_anatop_bypass();
+ printf("switch to ldo_bypass mode!\n");
+ }
+}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+void ldo_mode_set(int ldo_bypass)
+{
+ int is_400M;
+ unsigned char vddarm;
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("pfuze100", &dev);
+ if (ret == -ENODEV) {
+ printf("No PMIC found!\n");
+ return;
+ }
+
+ /* increase VDDARM/VDDSOC to support 1.2G chip */
+ if (check_1_2G()) {
+ ldo_bypass = 0; /* ldo_enable on 1.2G chip */
+ printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+ if (is_mx6dqp()) {
+ /* increase VDDARM to 1.425V */
+ pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29);
+ } else {
+ /* increase VDDARM to 1.425V */
+ pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d);
+ }
+ /* increase VDDSOC to 1.425V */
+ pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d);
+ }
+ /* switch to ldo_bypass mode , boot on 800Mhz */
+ if (ldo_bypass) {
+ prep_anatop_bypass();
+ if (is_mx6dqp()) {
+ /* decrease VDDARM for 400Mhz DQP:1.1V*/
+ pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1c);
+ } else {
+ /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
+ if (is_mx6dl())
+ pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x27);
+ else
+ pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20);
+ }
+ /* increase VDDSOC to 1.3V */
+ pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x28);
+
+ /*
+ * MX6Q/DQP:
+ * VDDARM:1.15V@800M; VDDSOC:1.175V@800M
+ * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
+ * MX6DL:
+ * VDDARM:1.175V@800M; VDDSOC:1.175V@800M
+ * VDDARM:1.075V@400M; VDDSOC:1.175V@400M
+ */
+ is_400M = set_anatop_bypass(2);
+ if (is_mx6dqp()) {
+ if (is_400M)
+ pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x17);
+ else
+ pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1e);
+ }
+
+ if (is_400M) {
+ if (is_mx6dl())
+ vddarm = 0x1f;
+ else
+ vddarm = 0x1b;
+ } else {
+ if (is_mx6dl())
+ vddarm = 0x23;
+ else
+ vddarm = 0x22;
+ }
+ pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
+
+ /* decrease VDDSOC to 1.175V */
+ pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23);
+
+ finish_anatop_bypass();
+ printf("switch to ldo_bypass mode!\n");
+ }
+}
+#endif
+#endif
+
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 1e2f67b..76fc24e 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -400,6 +400,60 @@ int power_init_board(void)
return 0;
}
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+ u32 value;
+ int is_400M;
+ struct pmic *p = pmic_get("PFUZE100");
+
+ if (!p) {
+ printf("No pmic!\n");
+ return;
+ }
+
+ /* swith to ldo_bypass mode */
+ if (ldo_bypass) {
+ prep_anatop_bypass();
+
+ /* decrease VDDARM to 1.1V */
+ pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+ value &= ~0x3f;
+ value |= 0x20;
+ pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+ /* increase VDDSOC to 1.3V */
+ pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+ value &= ~0x3f;
+ value |= 0x28;
+ pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+ is_400M = set_anatop_bypass(0);
+
+ /*
+ * MX6SL: VDDARM:1.175V@800M; VDDSOC:1.175V@800M
+ * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
+ */
+ pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+ value &= ~0x3f;
+ if (is_400M)
+ value |= 0x1b;
+ else
+ value |= 0x23;
+ pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+ /* decrease VDDSOC to 1.175V */
+ pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+ value &= ~0x3f;
+ value |= 0x23;
+ pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+ finish_anatop_bypass();
+ printf("switch to ldo_bypass mode!\n");
+ }
+}
+#endif
+
#endif
#ifdef CONFIG_FEC_MXC
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
index 36c4c12..7fd74d9 100644
--- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@@ -181,6 +181,33 @@ int power_init_board(void)
return 0;
}
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("pfuze100", &dev);
+ if (ret == -ENODEV) {
+ printf("No PMIC found!\n");
+ return;
+ }
+
+ /* switch to ldo_bypass mode */
+ if (ldo_bypass) {
+ /* decrease VDDARM to 1.15V */
+ pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, SW1x_1_150V);
+
+ /* decrease VDDSOC to 1.15V */
+ pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, SW1x_1_150V);
+
+ set_anatop_bypass(1);
+
+ printf("switch to ldo_bypass mode!\n");
+ }
+}
+#endif
+
#ifdef CONFIG_USB_EHCI_MX6
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index d242072..ebb837b 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -329,6 +329,57 @@ int power_init_board(void)
return 0;
}
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+ unsigned int value;
+ int is_400M;
+ u32 vddarm;
+ struct pmic *p = pmic_get("PFUZE100");
+
+ if (!p) {
+ printf("No PMIC found!\n");
+ return;
+ }
+
+ /* switch to ldo_bypass mode */
+ if (ldo_bypass) {
+ prep_anatop_bypass();
+ /* decrease VDDARM to 1.275V */
+ pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+ value &= ~0x3f;
+ value |= PFUZE100_SW1ABC_SETP(12750);
+ pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+ /* decrease VDDSOC to 1.3V */
+ pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+ value &= ~0x3f;
+ value |= PFUZE100_SW1ABC_SETP(13000);
+ pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+ is_400M = set_anatop_bypass(1);
+ if (is_400M)
+ vddarm = PFUZE100_SW1ABC_SETP(10750);
+ else
+ vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+ pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+ value &= ~0x3f;
+ value |= vddarm;
+ pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+ pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+ value &= ~0x3f;
+ value |= PFUZE100_SW1ABC_SETP(11750);
+ pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+ finish_anatop_bypass();
+ printf("switch to ldo_bypass mode!\n");
+ }
+
+}
+#endif
+
#ifdef CONFIG_USB_EHCI_MX6
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 826d2c9..b34f818 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -217,6 +217,43 @@ int power_init_board(void)
return 0;
}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+ unsigned int value;
+ u32 vddarm;
+
+ struct pmic *p = pmic_get("PFUZE3000");
+
+ if (!p) {
+ printf("No PMIC found!\n");
+ return;
+ }
+
+ /* switch to ldo_bypass mode */
+ if (ldo_bypass) {
+ prep_anatop_bypass();
+ /* decrease VDDARM to 1.275V */
+ pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value);
+ value &= ~0x1f;
+ value |= PFUZE3000_SW1AB_SETP(1275);
+ pmic_reg_write(p, PFUZE3000_SW1BVOLT, value);
+
+ set_anatop_bypass(1);
+ vddarm = PFUZE3000_SW1AB_SETP(1175);
+
+ pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value);
+ value &= ~0x1f;
+ value |= vddarm;
+ pmic_reg_write(p, PFUZE3000_SW1BVOLT, value);
+
+ finish_anatop_bypass();
+
+ printf("switch to ldo_bypass mode!\n");
+ }
+}
+#endif
#endif
#endif
generated by cgit v1.1 at 2024-08-19 17:29:04 +0000