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-rw-r--r--board/freescale/mx6qsabreauto/mx6qp.cfg145
-rw-r--r--board/freescale/mx6qsabreauto/mx6qsabreauto.c40
-rw-r--r--board/freescale/mx6sabresd/mx6sabresd.c13
-rw-r--r--board/freescale/mx6sxsabresd/mx6sxsabresd.c3
-rw-r--r--board/freescale/mx6ul_14x14_evk/Kconfig15
-rw-r--r--board/freescale/mx6ul_14x14_evk/MAINTAINERS6
-rw-r--r--board/freescale/mx6ul_14x14_evk/Makefile6
-rw-r--r--board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c636
8 files changed, 856 insertions, 8 deletions
diff --git a/board/freescale/mx6qsabreauto/mx6qp.cfg b/board/freescale/mx6qsabreauto/mx6qp.cfg
new file mode 100644
index 0000000..2298c77
--- /dev/null
+++ b/board/freescale/mx6qsabreauto/mx6qp.cfg
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand: flash_offset: 0x0400
+ * sata: flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001b001e
+DATA 4 0x021b0810 0x002e0029
+DATA 4 0x021b480c 0x001b002a
+DATA 4 0x021b4810 0x0019002c
+DATA 4 0x021b083c 0x43240334
+DATA 4 0x021b0840 0x0324031a
+DATA 4 0x021b483c 0x43340344
+DATA 4 0x021b4840 0x03280276
+DATA 4 0x021b0848 0x44383A3E
+DATA 4 0x021b4848 0x3C3C3846
+DATA 4 0x021b0850 0x2e303230
+DATA 4 0x021b4850 0x38283E34
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08c0 0x24912492
+DATA 4 0x021b48c0 0x24912492
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x898E7955
+DATA 4 0x021b0010 0xFF328F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x008E1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0400 0x14420000
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x00bb0008 0x00000004
+DATA 4 0x00bb000c 0x2891E41A
+DATA 4 0x00bb0038 0x00000564
+DATA 4 0x00bb0014 0x00000040
+DATA 4 0x00bb0028 0x00000020
+DATA 4 0x00bb002c 0x00000020
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0xFFFFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, 0x020e0018, 0x77177717
+DATA 4, 0x020e001c, 0x77177717
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index b76e4eb..98602f8 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -354,9 +354,22 @@ int board_phy_config(struct phy_device *phydev)
return 0;
}
-int board_eth_init(bd_t *bis)
+static void setup_fec(void)
{
+ if (is_mx6dqp()) {
+ /*
+ * select ENET MAC0 TX clock from PLL
+ */
+ imx_iomux_set_gpr_register(5, 9, 1, 1);
+ enable_fec_anatop_clock(ENET_125MHZ);
+ }
+
setup_iomux_enet();
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_fec();
return cpu_eth_init(bis);
}
@@ -495,17 +508,21 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
int power_init_board(void)
{
struct pmic *p;
- unsigned int ret;
+ unsigned int value;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
- ret = pfuze_mode_init(p, APS_PFM);
- if (ret < 0)
- return ret;
+ if (is_mx6dqp()) {
+ /* set SW2 staby volatage 0.975V*/
+ pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+ value &= ~0x3f;
+ value |= 0x17;
+ pmic_reg_write(p, PFUZE100_SW2STBY, value);
+ }
- return 0;
+ return pfuze_mode_init(p, APS_PFM);
}
#ifdef CONFIG_CMD_BMODE
@@ -522,6 +539,17 @@ int board_late_init(void)
add_board_boot_modes(board_boot_modes);
#endif
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", "SABREAUTO");
+
+ if (is_mx6dqp())
+ setenv("board_rev", "MX6QP");
+ else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ setenv("board_rev", "MX6Q");
+ else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+ setenv("board_rev", "MX6DL");
+#endif
+
return 0;
}
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 23f8f6b..eb8a8b3 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -631,7 +631,8 @@ int board_init(void)
int power_init_board(void)
{
struct pmic *p;
- unsigned int reg, ret;
+ unsigned int reg;
+ int ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
@@ -679,6 +680,16 @@ int board_late_init(void)
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", "SABRESD");
+
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ setenv("board_rev", "MX6Q");
+ else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+ setenv("board_rev", "MX6DL");
+#endif
+
return 0;
}
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 2ff960e..d58a79a 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -199,7 +199,8 @@ static struct i2c_pads_info i2c_pad_info1 = {
int power_init_board(void)
{
struct pmic *p;
- unsigned int reg, ret;
+ unsigned int reg;
+ int ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig
new file mode 100644
index 0000000..393aca6
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX6UL_14X14_EVK
+
+config SYS_BOARD
+ default "mx6ul_14x14_evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "mx6ul_14x14_evk"
+
+endif
diff --git a/board/freescale/mx6ul_14x14_evk/MAINTAINERS b/board/freescale/mx6ul_14x14_evk/MAINTAINERS
new file mode 100644
index 0000000..611feca
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_evk/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6ULEVK BOARD
+M: Peng Fan <Peng.Fan@freescale.com>
+S: Maintained
+F: board/freescale/mx6ul_14x14_evk/
+F: include/configs/mx6ul_14x14_evk.h
+F: configs/mx6ul_14x14_evk_defconfig
diff --git a/board/freescale/mx6ul_14x14_evk/Makefile b/board/freescale/mx6ul_14x14_evk/Makefile
new file mode 100644
index 0000000..61f6778
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_evk/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6ul_14x14_evk.o
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
new file mode 100644
index 0000000..8f712cb
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -0,0 +1,636 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <usb.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+#define IOX_SDI IMX_GPIO_NR(5, 10)
+#define IOX_STCP IMX_GPIO_NR(5, 7)
+#define IOX_SHCP IMX_GPIO_NR(5, 11)
+#define IOX_OE IMX_GPIO_NR(5, 18)
+
+static iomux_v3_cfg_t const iox_pads[] = {
+ /* IOX_SDI */
+ MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOX_SHCP */
+ MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOX_STCP */
+ MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOX_nOE */
+ MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*
+ * HDMI_nRST --> Q0
+ * ENET1_nRST --> Q1
+ * ENET2_nRST --> Q2
+ * CAN1_2_STBY --> Q3
+ * BT_nPWD --> Q4
+ * CSI_RST --> Q5
+ * CSI_PWDN --> Q6
+ * LCD_nPWREN --> Q7
+ */
+enum qn {
+ HDMI_NRST,
+ ENET1_NRST,
+ ENET2_NRST,
+ CAN1_2_STBY,
+ BT_NPWD,
+ CSI_RST,
+ CSI_PWDN,
+ LCD_NPWREN,
+};
+
+enum qn_func {
+ qn_reset,
+ qn_enable,
+ qn_disable,
+};
+
+enum qn_level {
+ qn_low = 0,
+ qn_high = 1,
+};
+
+static enum qn_level seq[3][2] = {
+ {0, 1}, {1, 1}, {0, 0}
+};
+
+static enum qn_func qn_output[8] = {
+ qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
+ qn_disable, qn_enable
+};
+
+static void iox74lv_init(void)
+{
+ int i;
+
+ gpio_direction_output(IOX_OE, 0);
+
+ for (i = 7; i >= 0; i--) {
+ gpio_direction_output(IOX_SHCP, 0);
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
+ udelay(500);
+ gpio_direction_output(IOX_SHCP, 1);
+ udelay(500);
+ }
+
+ gpio_direction_output(IOX_STCP, 0);
+ udelay(500);
+ /*
+ * shift register will be output to pins
+ */
+ gpio_direction_output(IOX_STCP, 1);
+
+ for (i = 7; i >= 0; i--) {
+ gpio_direction_output(IOX_SHCP, 0);
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
+ udelay(500);
+ gpio_direction_output(IOX_SHCP, 1);
+ udelay(500);
+ }
+ gpio_direction_output(IOX_STCP, 0);
+ udelay(500);
+ /*
+ * shift register will be output to pins
+ */
+ gpio_direction_output(IOX_STCP, 1);
+
+ gpio_direction_output(IOX_OE, 1);
+};
+
+void iox74lv_set(int index)
+{
+ int i;
+
+ gpio_direction_output(IOX_OE, 0);
+
+ for (i = 7; i >= 0; i--) {
+ gpio_direction_output(IOX_SHCP, 0);
+
+ if (i == index)
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
+ else
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
+ udelay(500);
+ gpio_direction_output(IOX_SHCP, 1);
+ udelay(500);
+ }
+
+ gpio_direction_output(IOX_STCP, 0);
+ udelay(500);
+ /*
+ * shift register will be output to pins
+ */
+ gpio_direction_output(IOX_STCP, 1);
+
+ for (i = 7; i >= 0; i--) {
+ gpio_direction_output(IOX_SHCP, 0);
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
+ udelay(500);
+ gpio_direction_output(IOX_SHCP, 1);
+ udelay(500);
+ }
+
+ gpio_direction_output(IOX_STCP, 0);
+ udelay(500);
+ /*
+ * shift register will be output to pins
+ */
+ gpio_direction_output(IOX_STCP, 1);
+
+ gpio_direction_output(IOX_OE, 1);
+};
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC and EEPROM */
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
+ .gp = IMX_GPIO_NR(1, 28),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
+ .gp = IMX_GPIO_NR(1, 29),
+ },
+};
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* VSELECT */
+ MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* CD */
+ MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* RST_B */
+ MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*
+ * mx6ul_14x14_evk board default supports sd card. If want to use
+ * EMMC, need to do board rework for sd2.
+ * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
+ * emmc, need to define this macro.
+ */
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /*
+ * RST_B
+ */
+ MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#else
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
+ /*
+ * The evk board uses DAT3 to detect CD card plugin,
+ * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
+ */
+ MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
+ MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
+};
+#endif
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+ MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+ /* Set the iomux */
+ imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+ ARRAY_SIZE(quadspi_pads));
+ /* Set the clock */
+ enable_qspi_clk(0);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR, 0, 4},
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+ {USDHC2_BASE_ADDR, 0, 8},
+#else
+ {USDHC2_BASE_ADDR, 0, 4},
+#endif
+};
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
+#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC2_BASE_ADDR:
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+ ret = 1;
+#else
+ imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads,
+ ARRAY_SIZE(usdhc2_cd_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+
+ /*
+ * Since it is the DAT3 pin, this pin is pulled to
+ * low voltage if no card
+ */
+ ret = gpio_get_value(USDHC2_CD_GPIO);
+
+ imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads,
+ ARRAY_SIZE(usdhc2_dat3_pads));
+#endif
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+ imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
+ ARRAY_SIZE(usdhc2_emmc_pads));
+#else
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+#endif
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+#else
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ gpio_direction_output(USDHC1_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC1_PWR_GPIO, 1);
+ break;
+ case 1:
+#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
+#else
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+#endif
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* At default the 3v3 enables the MIC2026 for VBUS power */
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
+
+ iox74lv_init();
+
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+ board_qspi_init();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6UL 14x14 EVK\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000030,
+ .dram_odt1 = 0x00000030,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000008,
+ .dram_sdqs0 = 0x00000038,
+ .dram_sdqs1 = 0x00000030,
+ .dram_reset = 0x00000030,
+};
+
+const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00070007,
+ .p0_mpdgctrl0 = 0x41490145,
+ .p0_mprddlctl = 0x40404546,
+ .p0_mpwrdlctl = 0x4040524D,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ struct mx6_ddr_sysinfo sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ };
+
+ mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
+#endif