diff options
Diffstat (limited to 'board/freescale/mx7d_19x19_ddr3_arm2')
| -rw-r--r-- | board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg | 11 | ||||
| -rw-r--r-- | board/freescale/mx7d_19x19_ddr3_arm2/imximage_TO_1_0.cfg | 110 | ||||
| -rw-r--r-- | board/freescale/mx7d_19x19_ddr3_arm2/plugin.S | 56 |
3 files changed, 172 insertions, 5 deletions
diff --git a/board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg b/board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg index bb5cf95..6317055 100644 --- a/board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg +++ b/board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ * @@ -49,6 +49,8 @@ CSF CONFIG_CSF_SIZE * Address absolute address of the register * value value to be stored in the register */ +DATA 4 0x3038a080 0x15000000 +DATA 4 0x30389880 0x01000000 DATA 4 0x30340004 0x4F400005 @@ -85,7 +87,12 @@ DATA 4 0x30391000 0x00000000 DATA 4 0x30790000 0x17420f40 DATA 4 0x30790004 0x10210100 DATA 4 0x30790010 0x00060807 -DATA 4 0x3079009c 0x00000d6e +DATA 4 0x3079009c 0x00000dee +DATA 4 0x3079007c 0x18181818 +DATA 4 0x30790080 0x18181818 +DATA 4 0x30790084 0x40401818 +DATA 4 0x30790088 0x00000040 +DATA 4 0x3079006c 0x40404040 DATA 4 0x30790020 0x08080808 DATA 4 0x30790030 0x08080808 DATA 4 0x30790050 0x01000010 diff --git a/board/freescale/mx7d_19x19_ddr3_arm2/imximage_TO_1_0.cfg b/board/freescale/mx7d_19x19_ddr3_arm2/imximage_TO_1_0.cfg new file mode 100644 index 0000000..2d6c025 --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_arm2/imximage_TO_1_0.cfg @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_ddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x0040005e +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020001 +DATA 4 0x307a00d4 0x00010000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00090004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x0908120a +DATA 4 0x307a0104 0x0002020e +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020204 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x03030803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00171717 +DATA 4 0x307a0214 0x04040404 +DATA 4 0x307a0218 0x00040404 +DATA 4 0x307a0240 0x06000601 +DATA 4 0x307a0244 0x00001323 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x3079009c 0x00000d6e +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_19x19_ddr3_arm2/plugin.S b/board/freescale/mx7d_19x19_ddr3_arm2/plugin.S index caea322..2e221fe 100644 --- a/board/freescale/mx7d_19x19_ddr3_arm2/plugin.S +++ b/board/freescale/mx7d_19x19_ddr3_arm2/plugin.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,7 +7,58 @@ #include <config.h> /* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x18181818 + str r1, [r0, #0x7c] + ldr r1, =0x18181818 + str r1, [r0, #0x80] + ldr r1, =0x40401818 + str r1, [r0, #0x84] + ldr r1, =0x00000040 + str r1, [r0, #0x88] + ldr r1, =0x40404040 + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000d6e + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_ddr_freq_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne FREQ_DEFAULT_533 + + /* Change to 400Mhz for TO1.1 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x15000000 + ldr r2, =0xa080 + str r1, [r0, r2] + ldr r1, =0x01000000 + ldr r2, =0x9880 + str r1, [r0, r2] + +FREQ_DEFAULT_533: +.endm + .macro imx7d_19x19_ddr3_arm2_ddr_setting + imx7d_ddr_freq_setting + /* Configure ocram_epdc */ ldr r0, =IOMUXC_GPR_BASE_ADDR ldr r1, =0x4f400005 @@ -90,8 +141,7 @@ str r1, [r0, #0x4] ldr r1, =0x00060807 str r1, [r0, #0x10] - ldr r1, =0x00000d6e - str r1, [r0, #0x9c] + imx7d_ddrphy_latency_setting ldr r1, =0x08080808 str r1, [r0, #0x20] ldr r1, =0x08080808 |