diff options
Diffstat (limited to 'board/freescale/mx35_3stack')
| -rw-r--r-- | board/freescale/mx35_3stack/Makefile | 49 | ||||
| -rw-r--r-- | board/freescale/mx35_3stack/board-mx35_3stack.h | 107 | ||||
| -rw-r--r-- | board/freescale/mx35_3stack/config.mk | 1 | ||||
| -rw-r--r-- | board/freescale/mx35_3stack/lowlevel_init.S | 406 | ||||
| -rw-r--r-- | board/freescale/mx35_3stack/mx35_3stack.c | 189 | ||||
| -rw-r--r-- | board/freescale/mx35_3stack/u-boot.lds | 72 |
6 files changed, 824 insertions, 0 deletions
diff --git a/board/freescale/mx35_3stack/Makefile b/board/freescale/mx35_3stack/Makefile new file mode 100644 index 0000000..4c38a8b --- /dev/null +++ b/board/freescale/mx35_3stack/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx35_3stack.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx35_3stack/board-mx35_3stack.h b/board/freescale/mx35_3stack/board-mx35_3stack.h new file mode 100644 index 0000000..f9c3074 --- /dev/null +++ b/board/freescale/mx35_3stack/board-mx35_3stack.h @@ -0,0 +1,107 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BOARD_MX35_3STACK_H +#define __BOARD_MX35_3STACK_H + +#define UNALIGNED_ACCESS_ENABLE +#define LOW_INT_LATENCY_ENABLE +#define BRANCH_PREDICTION_ENABLE + +#define L2CC_AUX_CTL_CONFIG 0x00030024 + +#define AIPS_MPR_CONFIG 0x77777777 +#define AIPS_OPACR_CONFIG 0x00000000 + +/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_MPR_CONFIG 0x00302154 +/* SGPCR - always park on last master */ +#define MAX_SGPCR_CONFIG 0x00000010 +/* MGPCR - restore default values */ +#define MAX_MGPCR_CONFIG 0x00000000 + +/* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ +#define M3IF_CONFIG 0x00000040 + +#define DBG_BASE_ADDR WEIM_CTRL_CS5 +#define DBG_CSCR_U_CONFIG 0x0000D843 +#define DBG_CSCR_L_CONFIG 0x22252521 +#define DBG_CSCR_A_CONFIG 0x22220A00 + +#define CCM_CCMR_CONFIG 0x003F4208 +#define CCM_PDR0_CONFIG 0x00821000 + +#define PLL_BRM_OFFSET 31 +#define PLL_PD_OFFSET 26 +#define PLL_MFD_OFFSET 16 +#define PLL_MFI_OFFSET 10 + +#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET) +#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET) +#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET) +#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET) +#define _PLL_MFN(x) (x) +#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ + (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ + _PLL_MFN(mfn)) + +#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) +#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) +#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) + +/*MEMORY SETING*/ +#define ESDCTL_0x92220000 0x92220000 +#define ESDCTL_0xA2220000 0xA2220000 +#define ESDCTL_0xB2220000 0xB2220000 +#define ESDCTL_0x82228080 0x82228080 + +#define ESDCTL_PRECHARGE 0x00000400 + +#define ESDCTL_MDDR_CONFIG 0x007FFC3F +#define ESDCTL_MDDR_MR 0x00000033 +#define ESDCTL_MDDR_EMR 0x02000000 + +#define ESDCTL_DDR2_CONFIG 0x007FFC3F +#define ESDCTL_DDR2_EMR2 0x04000000 +#define ESDCTL_DDR2_EMR3 0x06000000 +#define ESDCTL_DDR2_EN_DLL 0x02000400 +#define ESDCTL_DDR2_RESET_DLL 0x00000333 +#define ESDCTL_DDR2_MR 0x00000233 +#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 + +#define ESDCTL_DELAY_LINE5 0x00F49F00 +#endif /* __BOARD_MX35_3STACK_H */ diff --git a/board/freescale/mx35_3stack/config.mk b/board/freescale/mx35_3stack/config.mk new file mode 100644 index 0000000..d34dc02 --- /dev/null +++ b/board/freescale/mx35_3stack/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x87f00000 diff --git a/board/freescale/mx35_3stack/lowlevel_init.S b/board/freescale/mx35_3stack/lowlevel_init.S new file mode 100644 index 0000000..84614fc --- /dev/null +++ b/board/freescale/mx35_3stack/lowlevel_init.S @@ -0,0 +1,406 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/mx35.h> +#include "board-mx35_3stack.h" + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* Disable L2 cache first */ + mov r0, #L2CC_BASE_ADDR + ldr r1, [r0, #L2_CACHE_CTL_REG] + bic r1, r1, #0x1 + str r1, [r0, #L2_CACHE_CTL_REG] + + /* + * Configure L2 Cache: + * - 128k size(16k way) + * - 8-way associativity + * - 0 ws TAG/VALID/DIRTY + * - 4 ws DATA R/W + */ + ldr r1, [r0, #L2_CACHE_AUX_CTL_REG] + and r1, r1, #0xFE000000 + ldr r2, =L2CC_AUX_CTL_CONFIG + orr r1, r1, r2 + str r1, [r0, #L2_CACHE_AUX_CTL_REG] + +/* Workaournd for DDR issue:WT*/ + ldr r1, [r0, #L2_CACHE_DBG_CTL_REG] + orr r1, r1, #2 + str r1, [r0, #L2_CACHE_DBG_CTL_REG] + + /* Invalidate L2 */ + mov r1, #0x000000FF + str r1, [r0, #L2_CACHE_INV_WAY_REG] +1: + /* Poll Invalidate By Way register */ + ldr r2, [r0, #L2_CACHE_INV_WAY_REG] + cmp r2, #0 + bne 1b +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_MPR_CONFIG + str r1, [r0, #0x00] + str r1, [r0, #0x04] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x00] + str r1, [r0, #0x04] + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_OPACR_CONFIG + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] +.endm /* init_aips */ + +/* MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max + ldr r0, =MAX_BASE_ADDR + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ + ldr r1, =MAX_MPR_CONFIG + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =MAX_SGPCR_CONFIG + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =MAX_MGPCR_CONFIG + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + str r1, [r0, #0xD00] /* for M5 */ +.endm /* init_max */ + +/* M3IF setup */ +.macro init_m3if + /* Configure M3IF registers */ + ldr r1, =M3IF_BASE_ADDR + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + ldr r0, =M3IF_CONFIG + str r0, [r1] /* M3IF control reg */ +.endm /* init_m3if */ + +/* To support 133MHz DDR */ +.macro init_drive_strength +/* + mov r0, #0x2 + ldr r1, =IOMUXC_BASE_ADDR + add r1, r1, #0x368 + add r2, r1, #0x4C8 - 0x368 +1: str r0, [r1], #4 + cmp r1, r2 + ble 1b +*/ +.endm /* init_drive_strength */ + +/* CPLD on CS5 setup */ +.macro init_debug_board + ldr r0, =DBG_BASE_ADDR + ldr r1, =DBG_CSCR_U_CONFIG + str r1, [r0, #0x00] + ldr r1, =DBG_CSCR_L_CONFIG + str r1, [r0, #0x04] + ldr r1, =DBG_CSCR_A_CONFIG + str r1, [r0, #0x08] +.endm /* init_debug_board */ + +/* clock setup */ +.macro init_clock + ldr r0, =CCM_BASE_ADDR + + /* default CLKO to 1/32 of the ARM core*/ + ldr r1, [r0, #CLKCTL_COSR] + bic r1, r1, #0x00000FF00 + bic r1, r1, #0x0000000FF + mov r2, #0x00006C00 + add r2, r2, #0x67 + orr r1, r1, r2 + str r1, [r0, #CLKCTL_COSR] + + ldr r2, =CCM_CCMR_CONFIG + str r2, [r0, #CLKCTL_CCMR] + + ldr r2, [r0, #CLKCTL_PDR0] + tst r2, #CLKMODE_CONSUMER + ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ + ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ + + str r3, [r0, #CLKCTL_MPCTL] + + ldr r1, =CCM_PPLL_300_HZ + str r1, [r0, #CLKCTL_PPCTL] + + ldr r1, [r0, #CLKCTL_PDR0] + orr r1, r1, #0x800000 + str r1, [r0, #CLKCTL_PDR0] + + ldr r1, =CCM_PDR0_CONFIG + str r1, [r0, #CLKCTL_PDR0] + + ldr r1, [r0, #CLKCTL_CGR0] + orr r1, r1, #0x00300000 + str r1, [r0, #CLKCTL_CGR0] + + ldr r1, [r0, #CLKCTL_CGR1] + orr r1, r1, #0x00000C00 + orr r1, r1, #0x00000003 + str r1, [r0, #CLKCTL_CGR1] +.endm /* init_clock */ + +.macro setup_sdram + ldr r0, =ESDCTL_BASE_ADDR + mov r3, #0x2000 + str r3, [r0, #0x0] + str r3, [r0, #0x8] + + /*ip(r12) has used to save lr register in upper calling*/ + mov fp, lr + + mov r5, #0x00 + mov r2, #0x00 + mov r1, #CSD0_BASE_ADDR + bl setup_sdram_bank + cmp r3, #0x0 + orreq r5, r5, #1 + eorne r2, r2, #0x1 + blne setup_sdram_bank + + mov lr, fp + + cmp r5, #0 + movne r3, #L2CC_BASE_ADDR + ldrne r4, [r3, #L2_CACHE_AUX_CTL_REG] + orrne r4, r4, #0x1000 + strne r4, [r3, #L2_CACHE_AUX_CTL_REG] + + ldr r3, =ESDCTL_DELAY_LINE5 + str r3, [r0, #0x30] +.endm /* setup_sdram */ + +.globl lowlevel_init +lowlevel_init: + /* Platform CHIP level init*/ +#ifdef TURN_OFF_IMPRECISE_ABORT + mrs r0, cpsr + bic r0, r0, #0x100 + msr cpsr, r0 +#endif + + mrc 15, 0, r1, c1, c0, 0 + +#ifndef BRANCH_PREDICTION_ENABLE + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #7 + mcr 15, 0, r0, c1, c0, 1 +#else + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #7 + mcr 15, 0, r0, c1, c0, 1 + orr r1, r1, #(1<<11) +#endif + +#ifdef UNALIGNED_ACCESS_ENABLE + orr r1, r1, #(1<<22) +#endif + +#ifdef LOW_INT_LATENCY_ENABLE + orr r1, r1, #(1<<21) +#endif + mcr 15, 0, r1, c1, c0, 0 + + mov r0, #0 +#ifdef BRANCH_PREDICTION_ENABLE + mcr 15, 0, r0, c15, c2, 4 +#endif + mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ + + init_l2cc + + /* initializes very early AIPS, what for? + * Then it also initializes Multi-Layer AHB Crossbar Switch, + * M3IF */ + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =0x40000015 /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + init_aips + + init_max + + init_m3if + + init_drive_strength + + cmp pc, #PHYS_SDRAM_1 + blo init_clock_start + cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) + blo skip_sdram_setup + +init_clock_start: + init_clock + init_debug_board + /*init_sdram*/ + setup_sdram +skip_sdram_setup: + mov pc, lr + +/* + * r0: ESDCTL control base, r1: sdram slot base + * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base + */ +setup_sdram_bank: + mov r3, #0xE /*0xA + 0x4*/ + tst r2, #0x1 + orreq r3, r3, #0x300 /*DDR2*/ + str r3, [r0, #0x10] + bic r3, r3, #0x00A + str r3, [r0, #0x10] + beq 2f + + mov r3, #0x20000 +1: subs r3, r3, #1 + bne 1b + +2: tst r2, #0x1 + ldreq r3, =ESDCTL_DDR2_CONFIG + ldrne r3, =ESDCTL_MDDR_CONFIG + cmp r1, #CSD1_BASE_ADDR + strlo r3, [r0, #0x4] + strhs r3, [r0, #0xC] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + + tst r2, #0x1 + bne skip_set_mode + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_DDR2_EMR2 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EMR3 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EN_DLL + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_RESET_DLL + strb r3, [r1, r4] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + +skip_set_mode: + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xA2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + strb r3, [r1] + strb r3, [r1] + + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + tst r2, #0x1 + ldreq r4, =ESDCTL_DDR2_MR + ldrne r4, =ESDCTL_MDDR_MR + mov r3, #0xDA + strb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT + streqb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_EN_DLL + ldrne r4, =ESDCTL_MDDR_EMR + strb r3, [r1, r4] + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0x82228080 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + + tst r2, #0x1 + moveq r4, #0x20000 + movne r4, #0x200 +1: subs r4, r4, #1 + bne 1b + + str r3, [r1, #0x100] + ldr r4, [r1, #0x100] + cmp r3, r4 + movne r3, #1 + moveq r3, #0 + + mov pc, lr diff --git a/board/freescale/mx35_3stack/mx35_3stack.c b/board/freescale/mx35_3stack/mx35_3stack.c new file mode 100644 index 0000000..f6d5641 --- /dev/null +++ b/board/freescale/mx35_3stack/mx35_3stack.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mx35.h> +#include <asm/arch/mx35_pins.h> +#include <asm/arch/iomux.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init(void) +{ + int pad; + + /* enable clocks */ + __REG(CCM_BASE_ADDR + CLKCTL_CGR0) |= 0x003F0000; + __REG(CCM_BASE_ADDR + CLKCTL_CGR1) |= 0x00030FFF; + + /* setup pins for I2C1 */ + mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); + + pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ + | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); + + mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); + mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); + + /* setup pins for FEC */ + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); + + pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \ + PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW); + + mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + + gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ + gd->bd->bi_boot_params = 0x80000100; /* address of boot parameters */ + + return 0; +} + +#ifdef BOARD_LATE_INIT +int board_late_init(void) +{ + u8 reg; + int i; + if (i2c_read(0x69, 0x20, 1, ®, 1) < 0) { + printf("board_late_init: read PMIC@0x20 fail\n"); + return 0; + } + + reg |= 0x4; + if (i2c_write(0x69, 0x20, 1, ®, 1) < 0) { + printf("board_late_init: write back PMIC@0x20 fail\n"); + return 0; + } + + for (i = 0; i < 1000; i++) + udelay(200); + + if (i2c_read(0x69, 0x1A, 1, ®, 1) < 0) { + printf("board_late_init: read PMIC@0x1A fail\n"); + return 0; + } + + reg &= 0x7F; + if (i2c_write(0x69, 0x1A, 1, ®, 1) < 0) { + printf("board_late_init: write back PMIC@0x1A fail\n"); + return 0; + } + for (i = 0; i < 1000; i++) + udelay(200); + + reg |= 0x80; + if (i2c_write(0x69, 0x1A, 1, ®, 1) < 0) { + printf("board_late_init: 2st write back PMIC@0x1A fail\n"); + return 0; + } + + return 0; +} +#endif + +int checkboard(void) +{ + printf("Board: MX35 3STACK ["); + switch (__REG(CCM_BASE_ADDR + CLKCTL_RCSR) & 0x0F) { + case 0x0000: + printf("POR"); + break; + case 0x0002: + printf("JTAG"); + break; + case 0x0004: + printf("RST"); + break; + case 0x0008: + printf("WDT"); + break; + default: + printf("unknown"); + } + printf("]\n"); + return 0; +} diff --git a/board/freescale/mx35_3stack/u-boot.lds b/board/freescale/mx35_3stack/u-boot.lds new file mode 100644 index 0000000..8a565e7 --- /dev/null +++ b/board/freescale/mx35_3stack/u-boot.lds @@ -0,0 +1,72 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/arm1136/start.o (.text) + board/freescale/mx35_3stack/libmx35_3stack.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} |