summaryrefslogtreecommitdiff
path: root/board/freescale/mx35_3stack/mx35_3stack.c
diff options
context:
space:
mode:
Diffstat (limited to 'board/freescale/mx35_3stack/mx35_3stack.c')
-rw-r--r--board/freescale/mx35_3stack/mx35_3stack.c175
1 files changed, 71 insertions, 104 deletions
diff --git a/board/freescale/mx35_3stack/mx35_3stack.c b/board/freescale/mx35_3stack/mx35_3stack.c
index f7fb96a..cbd0756 100644
--- a/board/freescale/mx35_3stack/mx35_3stack.c
+++ b/board/freescale/mx35_3stack/mx35_3stack.c
@@ -31,11 +31,7 @@
#include <i2c.h>
#include <linux/types.h>
-#ifdef CONFIG_MMC
-#include <asm/arch/sdhc.h>
-#endif
DECLARE_GLOBAL_DATA_PTR;
-volatile u32 *esdhc_base_pointer;
static u32 system_rev;
@@ -58,7 +54,6 @@ static inline void setup_soc_rev(void)
static inline void set_board_rev(int rev)
{
- int reg;
system_rev = (system_rev & ~(0xF << 8)) | (rev & 0xF) << 8;
}
@@ -276,129 +271,101 @@ int checkboard(void)
return 0;
}
+#if defined(CONFIG_SMC911X)
+extern int smc911x_initialize(u8 dev_num, int base_addr);
+#endif
+
int board_eth_init(bd_t *bis)
{
int rc = -ENODEV;
-#if defined(CONFIG_DRIVER_SMC911X)
- rc = smc911x_initialize(bis);
+#if defined(CONFIG_SMC911X)
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}
-#ifdef CONFIG_FSL_MMC
+#ifdef CONFIG_CMD_MMC
-int sdhc_init(void)
+u32 *imx_esdhc_base_addr;
+
+int esdhc_gpio_init(void)
{
u32 interface_esdhc = 0;
u32 pad_val = 0;
interface_esdhc = (readl(IIM_BASE_ADDR + 0x80c)) & (0x000000C0) >> 6;
- if (!is_soc_rev(CHIP_REV_1_0)) {
- pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
- PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
+ /* IOMUX PROGRAMMING */
+ switch (interface_esdhc) {
+ case 0:
+ imx_esdhc_base_addr = \
+ (u32 *)MMC_SDHC1_BASE_ADDR;
- switch (interface_esdhc) {
- case 0:
- debug("TO1 ESDHC1\n");
+ pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
+ PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
+ mxc_request_iomux(MX35_PIN_SD1_CLK,
+ MUX_CONFIG_FUNC | MUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX35_PIN_SD1_CLK, pad_val);
- esdhc_base_pointer = \
- (volatile u32 *)MMC_SDHC1_BASE_ADDR;
+ pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
+ PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
+ mxc_request_iomux(MX35_PIN_SD1_CMD,
+ MUX_CONFIG_FUNC | MUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX35_PIN_SD1_CMD, pad_val);
+ mxc_request_iomux(MX35_PIN_SD1_DATA0,
+ MUX_CONFIG_FUNC);
+ mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, pad_val);
+ mxc_request_iomux(MX35_PIN_SD1_DATA3,
+ MUX_CONFIG_FUNC);
+ mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val);
- mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val);
- break;
- case 1:
- debug("TO1 ESDHC2\n");
+ break;
+ case 1:
+ imx_esdhc_base_addr = \
+ (u32 *)MMC_SDHC2_BASE_ADDR;
+
+ mxc_request_iomux(MX35_PIN_SD2_CLK,
+ MUX_CONFIG_FUNC | MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_SD2_CMD,
+ MUX_CONFIG_FUNC | MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_SD2_DATA0,
+ MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD2_DATA3,
+ MUX_CONFIG_FUNC);
- esdhc_base_pointer = \
- (volatile u32 *)MMC_SDHC2_BASE_ADDR;
+ pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
+ PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
+ mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val);
- mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val);
- break;
- case 2:
- debug("TO1 ESDHC3\n");
+ pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
+ PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
+ mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val);
+ mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val);
+ mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val);
- esdhc_base_pointer = \
- (volatile u32 *)MMC_SDHC3_BASE_ADDR;
+ break;
+ case 2:
+ imx_esdhc_base_addr = \
+ (u32 *)MMC_SDHC3_BASE_ADDR;
- printf("TO1 ESDHC3 not supported!");
- break;
- default:
- break;
- }
- } else if (!is_soc_rev(CHIP_REV_2_0)) {
- /* IOMUX PROGRAMMING */
- switch (interface_esdhc) {
- case 0:
- debug("TO2 ESDHC1\n");
-
- esdhc_base_pointer = \
- (volatile u32 *)MMC_SDHC1_BASE_ADDR;
-
- pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
- PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
- mxc_request_iomux(MX35_PIN_SD1_CLK,
- MUX_CONFIG_FUNC | MUX_CONFIG_SION);
- mxc_iomux_set_pad(MX35_PIN_SD1_CLK, pad_val);
-
- pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
- PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
- mxc_request_iomux(MX35_PIN_SD1_CMD,
- MUX_CONFIG_FUNC | MUX_CONFIG_SION);
- mxc_iomux_set_pad(MX35_PIN_SD1_CMD, pad_val);
- mxc_request_iomux(MX35_PIN_SD1_DATA0,
- MUX_CONFIG_FUNC);
- mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, pad_val);
- mxc_request_iomux(MX35_PIN_SD1_DATA3,
- MUX_CONFIG_FUNC);
- mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val);
-
- break;
- case 1:
- debug("TO2 ESDHC2\n");
-
- esdhc_base_pointer = \
- (volatile u32 *)MMC_SDHC2_BASE_ADDR;
-
- mxc_request_iomux(MX35_PIN_SD2_CLK,
- MUX_CONFIG_FUNC | MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_SD2_CMD,
- MUX_CONFIG_FUNC | MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_SD2_DATA0,
- MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_SD2_DATA3,
- MUX_CONFIG_FUNC);
-
- pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
- PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
- mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val);
-
- pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
- PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
- mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val);
- mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val);
- mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val);
-
- break;
- case 2:
- debug("TO2 ESDHC3\n");
-
- esdhc_base_pointer = \
- (volatile u32 *)MMC_SDHC3_BASE_ADDR;
-
- printf("TO2 ESDHC3 not supported!");
- break;
- default:
- break;
- }
+ printf("TO2 ESDHC3 not supported!");
+ break;
+ default:
+ break;
}
return 0;
}
+int board_mmc_init(void)
+{
+ if (!esdhc_gpio_init())
+ return fsl_esdhc_mmc_init(gd->bd);
+ else
+ return -1;
+}
#endif
generated by cgit v1.1 at 2024-11-16 04:47:14 +0000