diff options
Diffstat (limited to 'board/freescale/ls2085ardb')
| -rw-r--r-- | board/freescale/ls2085ardb/Kconfig | 16 | ||||
| -rw-r--r-- | board/freescale/ls2085ardb/MAINTAINERS | 8 | ||||
| -rw-r--r-- | board/freescale/ls2085ardb/Makefile | 8 | ||||
| -rw-r--r-- | board/freescale/ls2085ardb/README | 120 | ||||
| -rw-r--r-- | board/freescale/ls2085ardb/ddr.c | 196 | ||||
| -rw-r--r-- | board/freescale/ls2085ardb/ddr.h | 92 | ||||
| -rw-r--r-- | board/freescale/ls2085ardb/eth_ls2085rdb.c | 147 | ||||
| -rw-r--r-- | board/freescale/ls2085ardb/ls2085ardb.c | 319 | ||||
| -rw-r--r-- | board/freescale/ls2085ardb/ls2085ardb_qixis.h | 20 |
9 files changed, 0 insertions, 926 deletions
diff --git a/board/freescale/ls2085ardb/Kconfig b/board/freescale/ls2085ardb/Kconfig deleted file mode 100644 index cb40db9..0000000 --- a/board/freescale/ls2085ardb/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ - -if TARGET_LS2085ARDB - -config SYS_BOARD - default "ls2085ardb" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls2085ardb" - -endif diff --git a/board/freescale/ls2085ardb/MAINTAINERS b/board/freescale/ls2085ardb/MAINTAINERS deleted file mode 100644 index d5cce40..0000000 --- a/board/freescale/ls2085ardb/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -LS2085A BOARD -M: Prabhakar Kushwaha <prabhakar@freescale.com> -S: Maintained -F: board/freescale/ls2085ardb/ -F: board/freescale/ls2085a/ls2085ardb.c -F: include/configs/ls2085ardb.h -F: configs/ls2085ardb_defconfig -F: configs/ls2085ardb_nand_defconfig diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2085ardb/Makefile deleted file mode 100644 index de383cc..0000000 --- a/board/freescale/ls2085ardb/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2015 Freescale Semiconductor -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ls2085ardb.o eth_ls2085rdb.o -obj-y += ddr.o diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2085ardb/README deleted file mode 100644 index 2f18243..0000000 --- a/board/freescale/ls2085ardb/README +++ /dev/null @@ -1,120 +0,0 @@ -Overview --------- -The LS2085A Reference Design (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2085A -Layerscape Architecture processor. - -LS2085A SoC Overview ------------------- -The LS2085A integrated multicore processor combines eight ARM Cortex-A57 -processor cores with high-performance data path acceleration logic and network -and peripheral bus interfaces required for networking, telecom/datacom, -wireless infrastructure, and mil/aerospace applications. - -The LS2085A SoC includes the following function and features: - - - Eight 64-bit ARM Cortex-A57 CPUs - - 1 MB platform cache with ECC - - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support - - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by - the AIOP - - Data path acceleration architecture (DPAA2) incorporating acceleration for - the following functions: - - Packet parsing, classification, and distribution (WRIOP) - - Queue and Hardware buffer management for scheduling, packet sequencing, and - congestion management, buffer allocation and de-allocation (QBMan) - - Cryptography acceleration (SEC) at up to 10 Gbps - - RegEx pattern matching acceleration (PME) at up to 10 Gbps - - Decompression/compression acceleration (DCE) at up to 20 Gbps - - Accelerated I/O processing (AIOP) at up to 20 Gbps - - QDMA engine - - 16 SerDes lanes at up to 10.3125 GHz - - Ethernet interfaces - - Up to eight 10 Gbps Ethernet MACs - - Up to eight 1 / 2.5 Gbps Ethernet MACs - - High-speed peripheral interfaces - - Four PCIe 3.0 controllers, one supporting SR-IOV - - Additional peripheral interfaces - - Two serial ATA (SATA 3.0) controllers - - Two high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Serial peripheral interface (SPI) controller - - Quad Serial Peripheral Interface (QSPI) Controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash - - Support for hardware virtualization and partitioning enforcement - - QorIQ platform's trust architecture 3.0 - - Service processor (SP) provides pre-boot initialization and secure-boot - capabilities - - LS2085ARDB board Overview - ----------------------- - - SERDES Connections, 16 lanes supporting: - - PCI Express - 3.0 - - SATA 3.0 - - XFI - - DDR Controller - - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four - chip-selects and two DIMM connectors. Support is up to 2133MT/s. - - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects - and two DIMM connectors. Support is up to 1600MT/s. - -IFC/Local Bus - - IFC rev. 2.0 implementation supporting Little Endian connection scheme. - - 128 MB NOR flash 16-bit data bus - - One 2 GB NAND flash with ECC support - - CPLD connection - - USB 3.0 - - Two high speed USB 3.0 ports - - First USB 3.0 port configured as Host with Type-A connector - - Second USB 3.0 port configured as OTG with micro-AB connector - - SDHC adapter - - SD Card Rev 2.0 and Rev 3.0 - - DSPI - - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz) - - 4 I2C controllers - - Two SATA onboard connectors - - UART - - ARM JTAG support - -Memory map from core's view ----------------------------- -0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom -0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR -0x00_1800_0000 .. 0x00_181F_FFFF OCRAM -0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 -0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 -0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 -0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 - -Other addresses are either reserved, or not used directly by u-boot. -This list should be updated when more addresses are used. - -IFC region map from core's view -------------------------------- -During boot i.e. IFC Region #1:- - 0x30000000 - 0x37ffffff : 128MB : NOR flash - 0x3C000000 - 0x40000000 : 64MB : CPLD - -After relocate to DDR i.e. IFC Region #2:- - 0x5_1000_0000..0x5_1fff_ffff Memory Hole - 0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB) - 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB - 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) - 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) - -Booting Options ---------------- -a) NOR boot -b) NAND boot - -Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) -------------------------------------------------------------------- -One needs to use appropriate bootargs to boot Linux flavors which do -not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown -below: - -=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram - earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m - hugepages=16 mem=2048M' - diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2085ardb/ddr.c deleted file mode 100644 index 8d71ae1..0000000 --- a/board/freescale/ls2085ardb/ddr.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - int slot; - - if (ctrl_num > 2) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - - for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) { - if (pdimm[slot].n_ranks) - break; - } - - if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(ctrl_num) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm[slot].n_ranks && - (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for data rate %lu MT/s\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); - - if (ctrl_num == CONFIG_DP_DDR_CTRL) { - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - popts->bstopre = 0; /* enable auto precharge */ - /* - * Layout optimization results byte mapping - * Byte 0 -> Byte ECC - * Byte 1 -> Byte 3 - * Byte 2 -> Byte 2 - * Byte 3 -> Byte 1 - * Byte ECC -> Byte 0 - */ - dq_mapping_0 = pdimm[slot].dq_mapping[0]; - dq_mapping_2 = pdimm[slot].dq_mapping[2]; - dq_mapping_3 = pdimm[slot].dq_mapping[3]; - pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8]; - pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9]; - pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6]; - pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7]; - pdimm[slot].dq_mapping[6] = dq_mapping_2; - pdimm[slot].dq_mapping[7] = dq_mapping_3; - pdimm[slot].dq_mapping[8] = dq_mapping_0; - pdimm[slot].dq_mapping[9] = 0; - pdimm[slot].dq_mapping[10] = 0; - pdimm[slot].dq_mapping[11] = 0; - pdimm[slot].dq_mapping[12] = 0; - pdimm[slot].dq_mapping[13] = 0; - pdimm[slot].dq_mapping[14] = 0; - pdimm[slot].dq_mapping[15] = 0; - pdimm[slot].dq_mapping[16] = 0; - pdimm[slot].dq_mapping[17] = 0; - } - /* To work at higher than 1333MT/s */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0x0; /* 32 clocks */ - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - if (ddr_freq < 2350) { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | - DDR_CDR2_VREF_RANGE_2; - } else { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) | - DDR_CDR2_VREF_RANGE_2; - } -} - -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size; - -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - return fsl_ddr_sdram_size(); -#else - puts("Initializing DDR....using SPD\n"); - - dram_size = fsl_ddr_sdram(); -#endif - - return dram_size; -} - -void dram_init_banksize(void) -{ -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - phys_size_t dp_ddr_size; -#endif - - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - } else { - gd->bd->bi_dram[0].size = gd->ram_size; - } - -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, - CONFIG_DP_DDR_CTRL, - CONFIG_DP_DDR_NUM_CTRLS, - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, - NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); - } -#endif -} diff --git a/board/freescale/ls2085ardb/ddr.h b/board/freescale/ls2085ardb/ddr.h deleted file mode 100644 index bda9d4a..0000000 --- a/board/freescale/ls2085ardb/ddr.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,}, - {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,}, - {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters udimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, - {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters rdimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, - udimm2, -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, - rdimm2, -}; - - -#endif diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2085ardb/eth_ls2085rdb.c deleted file mode 100644 index d578757..0000000 --- a/board/freescale/ls2085ardb/eth_ls2085rdb.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <malloc.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <fm_eth.h> -#include <asm/io.h> -#include <exports.h> -#include <asm/arch/fsl_serdes.h> -#include <fsl-mc/ldpaa_wriop.h> - -DECLARE_GLOBAL_DATA_PTR; - -int load_firmware_cortina(struct phy_device *phy_dev) -{ - if (phy_dev->drv->config) - return phy_dev->drv->config(phy_dev); - - return 0; -} - -void load_phy_firmware(void) -{ - int i; - u8 phy_addr; - struct phy_device *phy_dev; - struct mii_dev *dev; - phy_interface_t interface; - - /*Initialize and upload firmware for all the PHYs*/ - for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) { - interface = wriop_get_enet_if(i); - if (interface == PHY_INTERFACE_MODE_XGMII) { - dev = wriop_get_mdio(i); - phy_addr = wriop_get_phy_address(i); - phy_dev = phy_find_by_mask(dev, 1 << phy_addr, - interface); - if (!phy_dev) { - printf("No phydev for phyaddr %d\n", phy_addr); - continue; - } - - /*Flash firmware for All CS4340 PHYS */ - if (phy_dev->phy_id == PHY_UID_CS4340) - load_firmware_cortina(phy_dev); - } - } -} - -int board_eth_init(bd_t *bis) -{ -#if defined(CONFIG_FSL_MC_ENET) - int i, interface; - struct memac_mdio_info mdio_info; - struct mii_dev *dev; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - struct memac_mdio_controller *reg; - - srds_s1 = in_le32(&gur->rcwsr[28]) & - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; - - reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; - mdio_info.regs = reg; - mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; - - /* Register the EMI 1 */ - fm_memac_mdio_init(bis, &mdio_info); - - reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; - mdio_info.regs = reg; - mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; - - /* Register the EMI 2 */ - fm_memac_mdio_init(bis, &mdio_info); - - switch (srds_s1) { - case 0x2A: - wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); - wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); - wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); - wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); - wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1); - wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2); - wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3); - wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4); - - break; - default: - printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n", - srds_s1); - break; - } - - for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) { - interface = wriop_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); - wriop_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) { - switch (wriop_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); - wriop_set_mdio(i, dev); - break; - default: - break; - } - } - - /* Load CORTINA CS4340 PHY firmware */ - load_phy_firmware(); - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - return pci_eth_init(bis); -} diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c deleted file mode 100644 index 761d7c8..0000000 --- a/board/freescale/ls2085ardb/ls2085ardb.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <malloc.h> -#include <errno.h> -#include <netdev.h> -#include <fsl_ifc.h> -#include <fsl_ddr.h> -#include <asm/io.h> -#include <hwconfig.h> -#include <fdt_support.h> -#include <libfdt.h> -#include <fsl_debug_server.h> -#include <fsl-mc/fsl_mc.h> -#include <environment.h> -#include <i2c.h> -#include <asm/arch/soc.h> - -#include "../common/qixis.h" -#include "ls2085ardb_qixis.h" - -#define PIN_MUX_SEL_SDHC 0x00 -#define PIN_MUX_SEL_DSPI 0x0a - -#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) -DECLARE_GLOBAL_DATA_PTR; - -enum { - MUX_TYPE_SDHC, - MUX_TYPE_DSPI, -}; - -unsigned long long get_qixis_addr(void) -{ - unsigned long long addr; - - if (gd->flags & GD_FLG_RELOC) - addr = QIXIS_BASE_PHYS; - else - addr = QIXIS_BASE_PHYS_EARLY; - - /* - * IFC address under 256MB is mapped to 0x30000000, any address above - * is mapped to 0x5_10000000 up to 4GB. - */ - addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; - - return addr; -} - -int checkboard(void) -{ - u8 sw; - char buf[15]; - - cpu_name(buf); - printf("Board: %s-RDB, ", buf); - - sw = QIXIS_READ(arch); - printf("Board Arch: V%d, ", sw >> 4); - printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x9) - puts("NAND\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); - - printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); - - puts("SERDES1 Reference : "); - printf("Clock1 = 156.25MHz "); - printf("Clock2 = 156.25MHz"); - - puts("\nSERDES2 Reference : "); - printf("Clock1 = 100MHz "); - printf("Clock2 = 100MHz\n"); - - return 0; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} - -int select_i2c_ch_pca9547(u8 ch) -{ - int ret; - - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - -int config_board_mux(int ctrl_type) -{ - u8 reg5; - - reg5 = QIXIS_READ(brdcfg[5]); - - switch (ctrl_type) { - case MUX_TYPE_SDHC: - reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); - break; - case MUX_TYPE_DSPI: - reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); - break; - default: - printf("Wrong mux interface type\n"); - return -1; - } - - QIXIS_WRITE(brdcfg[5], reg5); - - return 0; -} - -int board_init(void) -{ - char *env_hwconfig; - u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; - u32 val; - - init_final_memctl_regs(); - - val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); - - env_hwconfig = getenv("hwconfig"); - - if (hwconfig_f("dspi", env_hwconfig) && - DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) - config_board_mux(MUX_TYPE_DSPI); - else - config_board_mux(MUX_TYPE_SDHC); - -#ifdef CONFIG_ENV_IS_NOWHERE - gd->env_addr = (ulong)&default_environment[0]; -#endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); - - QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); - - return 0; -} - -int board_early_init_f(void) -{ - fsl_lsch3_early_init_f(); - return 0; -} - -int misc_init_r(void) -{ - if (hwconfig("sdhc")) - config_board_mux(MUX_TYPE_SDHC); - - return 0; -} - -void detail_board_ddr_info(void) -{ - puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); - print_ddr_info(0); - if (gd->bd->bi_dram[2].size) { - puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); - print_ddr_info(CONFIG_DP_DDR_CTRL); - } -} - -int dram_init(void) -{ - gd->ram_size = initdram(0); - - return 0; -} - -#if defined(CONFIG_ARCH_MISC_INIT) -int arch_misc_init(void) -{ -#ifdef CONFIG_FSL_DEBUG_SERVER - debug_server_init(); -#endif - - return 0; -} -#endif - -unsigned long get_dram_size_to_hide(void) -{ - unsigned long dram_to_hide = 0; - -/* Carve the Debug Server private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_DEBUG_SERVER - dram_to_hide += debug_server_get_dram_block_size(); -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_MC_ENET - dram_to_hide += mc_get_dram_block_size(); -#endif - - return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); -} - -#ifdef CONFIG_FSL_MC_ENET -void fdt_fixup_board_enet(void *fdt) -{ - int offset; - - offset = fdt_path_offset(fdt, "/fsl-mc"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/fsl,dprc@0"); - - if (offset < 0) { - printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", - __func__, offset); - return; - } - - if (get_mc_boot_status() == 0) - fdt_status_okay(fdt, offset); - else - fdt_status_fail(fdt, offset); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - int err; - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - - ft_cpu_setup(blob, bd); - - /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - - fdt_fixup_memory_banks(blob, base, size, 2); - -#ifdef CONFIG_FSL_MC_ENET - fdt_fixup_board_enet(blob); - err = fsl_mc_ldpaa_exit(bd); - if (err) - return err; -#endif - - return 0; -} -#endif - -void qixis_dump_switch(void) -{ - int i, nr_of_cfgsw; - - QIXIS_WRITE(cms[0], 0x00); - nr_of_cfgsw = QIXIS_READ(cms[1]); - - puts("DIP switch settings dump:\n"); - for (i = 1; i <= nr_of_cfgsw; i++) { - QIXIS_WRITE(cms[0], i); - printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); - } -} - -/* - * Board rev C and earlier has duplicated I2C addresses for 2nd controller. - * Both slots has 0x54, resulting 2nd slot unusable. - */ -void update_spd_address(unsigned int ctrl_num, - unsigned int slot, - unsigned int *addr) -{ - u8 sw; - - sw = QIXIS_READ(arch); - if ((sw & 0xf) < 0x3) { - if (ctrl_num == 1 && slot == 0) - *addr = SPD_EEPROM_ADDRESS4; - else if (ctrl_num == 1 && slot == 1) - *addr = SPD_EEPROM_ADDRESS3; - } -} diff --git a/board/freescale/ls2085ardb/ls2085ardb_qixis.h b/board/freescale/ls2085ardb/ls2085ardb_qixis.h deleted file mode 100644 index cb60c00..0000000 --- a/board/freescale/ls2085ardb/ls2085ardb_qixis.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __LS2_RDB_QIXIS_H__ -#define __LS2_RDB_QIXIS_H__ - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 - -#endif /*__LS2_RDB_QIXIS_H__*/ |