diff options
Diffstat (limited to 'board/esd')
| -rw-r--r-- | board/esd/common/auto_update.c | 12 | ||||
| -rw-r--r-- | board/esd/common/esd405ep_nand.c | 42 |
2 files changed, 26 insertions, 28 deletions
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 7e6eea0..a1e0ce5 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -27,7 +27,7 @@ #include <command.h> #include <image.h> #include <asm/byteorder.h> -#if defined(CFG_NAND_LEGACY) +#if defined(CONFIG_NAND_LEGACY) #include <linux/mtd/nand_legacy.h> #endif #include <fat.h> @@ -58,7 +58,7 @@ extern int flash_sect_erase(ulong, ulong); extern int flash_sect_protect (int, ulong, ulong); extern int flash_write (char *, ulong, ulong); -#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY) /* references to names in cmd_nand.c */ #define NANDRW_READ 0x01 #define NANDRW_WRITE 0x00 @@ -158,7 +158,7 @@ int au_do_update(int i, long sz) int off, rc; uint nbytes; int k; -#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY) int total; #endif @@ -241,7 +241,7 @@ int au_do_update(int i, long sz) debug ("flash_sect_erase(%lx, %lx);\n", start, end); flash_sect_erase (start, end); } else { -#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY) printf ("Updating NAND FLASH with image %s\n", au_image[i].name); debug ("nand_legacy_erase(%lx, %lx);\n", start, end); @@ -273,7 +273,7 @@ int au_do_update(int i, long sz) rc = flash_write ((char *)addr, start, (nbytes + 1) & ~1); } else { -#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY) debug ("nand_legacy_rw(%p, %lx, %x)\n", addr, start, nbytes); rc = nand_legacy_rw (nand_dev_desc, @@ -298,7 +298,7 @@ int au_do_update(int i, long sz) rc = crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)); } else { -#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY) rc = nand_legacy_rw (nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c index 7bf6847..40d1efb 100644 --- a/board/esd/common/esd405ep_nand.c +++ b/board/esd/common/esd405ep_nand.c @@ -30,28 +30,26 @@ /* * hardware specific access to control-lines */ -static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) +static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - switch(cmd) { - case NAND_CTL_SETCLE: - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE); - break; - case NAND_CTL_CLRCLE: - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE); - break; - case NAND_CTL_SETALE: - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE); - break; - case NAND_CTL_CLRALE: - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE); - break; - case NAND_CTL_SETNCE: - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE); - break; - case NAND_CTL_CLRNCE: - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); - break; + struct nand_chip *this = mtd->priv; + if (ctrl & NAND_CTRL_CHANGE) { + if ( ctrl & NAND_CLE ) + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE); + else + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE); + if ( ctrl & NAND_ALE ) + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE); + else + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE); + if ( ctrl & NAND_NCE ) + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE); + else + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); } @@ -77,9 +75,9 @@ int board_nand_init(struct nand_chip *nand) /* * Initialize nand_chip structure */ - nand->hwcontrol = esd405ep_nand_hwcontrol; + nand->cmd_ctrl = esd405ep_nand_hwcontrol; nand->dev_ready = esd405ep_nand_device_ready; - nand->eccmode = NAND_ECC_SOFT; + nand->ecc.mode = NAND_ECC_SOFT; nand->chip_delay = NAND_BIG_DELAY_US; nand->options = NAND_SAMSUNG_LP_OPTIONS; return 0; |