diff options
Diffstat (limited to 'board/esd/cpci405/cpci405.c')
| -rw-r--r-- | board/esd/cpci405/cpci405.c | 134 |
1 files changed, 74 insertions, 60 deletions
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index f803610..69cb8ce 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -23,13 +23,15 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <command.h> #include <malloc.h> #include <net.h> +#include <pci.h> DECLARE_GLOBAL_DATA_PTR; -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ #if 0 #define FPGA_DEBUG #endif @@ -52,8 +54,6 @@ const unsigned char fpgadata[] = * include common fpga code (for esd boards) */ #include "../common/fpga.c" - - #include "../common/auto_update.h" #ifdef CONFIG_CPCI405AB @@ -86,13 +86,11 @@ au_image_t au_image[] = { int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); - /* Prototypes */ int cpci405_version(void); int gunzip(void *, int, unsigned char *, unsigned long *); void lxt971_no_sleep(void); - int board_early_init_f (void) { #ifndef CONFIG_CPCI405_VER2 @@ -111,10 +109,10 @@ int board_early_init_f (void) /* * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ + out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ - out32(GPIO0_OR, 0); /* pull prg low */ + out32(GPIO0_OR, 0); /* pull prg low */ /* * Boot onboard FPGA @@ -176,47 +174,48 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ +#ifdef CONFIG_CPCI405_6U if (cpci405_version() == 3) { - mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ + mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ } else { - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ } - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ +#else + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ +#endif + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ return 0; } - /* ------------------------------------------------------------------------- */ int ctermm2(void) { #ifdef CONFIG_CPCI405_VER2 - return 0; /* no, board is cpci405 */ + return 0; /* no, board is cpci405 */ #else if ((*(unsigned char *)0xf0000400 == 0x00) && (*(unsigned char *)0xf0000401 == 0x01)) - return 0; /* no, board is cpci405 */ + return 0; /* no, board is cpci405 */ else - return -1; /* yes, board is cterm-m2 */ + return -1; /* yes, board is cterm-m2 */ #endif } - int cpci405_host(void) { if (mfdcr(strap) & PSR_PCI_ARBIT_EN) - return -1; /* yes, board is cpci405 host */ + return -1; /* yes, board is cpci405 host */ else - return 0; /* no, board is cpci405 adapter */ + return 0; /* no, board is cpci405 adapter */ } - int cpci405_version(void) { unsigned long cntrl0Reg; @@ -227,10 +226,10 @@ int cpci405_version(void) */ cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x03000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); - udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ + out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); + udelay(1000); /* wait some time before reading input */ + value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ /* * Restore GPIO settings @@ -245,7 +244,7 @@ int cpci405_version(void) /* CS2==0 && CS3==1 -> version 2 */ return 2; case 0x00100000: - /* CS2==1 && CS3==0 -> version 3 */ + /* CS2==1 && CS3==0 -> version 3 or 6U board */ return 3; case 0x00000000: /* CS2==0 && CS3==0 -> version 4 */ @@ -256,13 +255,11 @@ int cpci405_version(void) } } - int misc_init_f (void) { return 0; /* dummy implementation */ } - int misc_init_r (void) { unsigned long cntrl0Reg; @@ -283,7 +280,6 @@ int misc_init_r (void) * On CPCI-405 version 2 the environment is saved in eeprom! * FPGA can be gzip compressed (malloc) and booted this late. */ - if (cpci405_version() >= 2) { /* * Setup GPIO pins (CS6+CS7 as GPIO) @@ -354,6 +350,7 @@ int misc_init_r (void) SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ +#ifdef CONFIG_CPCI405_6U if (cpci405_version() == 3) { volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR; volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR; @@ -375,6 +372,7 @@ int misc_init_r (void) udelay(100); *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET); } +#endif } else { puts("\n*** U-Boot Version does not match Board Version!\n"); @@ -425,7 +423,6 @@ int misc_init_r (void) return (0); } - /* * Check Board Identity: */ @@ -481,7 +478,7 @@ int checkboard (void) } #ifndef CONFIG_CPCI405_VER2 - puts ("\nFPGA: "); + puts ("\nFPGA: "); /* display infos on fpgaimage */ index = 15; @@ -493,12 +490,6 @@ int checkboard (void) #endif putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - return 0; } @@ -511,22 +502,18 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -/* ------------------------------------------------------------------------- */ - -int testdram (void) +void reset_phy(void) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); +#ifdef CONFIG_LXT971_NO_SLEEP - return (0); + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif } /* ------------------------------------------------------------------------- */ @@ -551,14 +538,47 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ #endif /* CONFIG_CPCI405_VER2 */ +#if defined(CONFIG_PCI) +void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char int_line = 0xff; + + /* + * Write pci interrupt line register (cpci405 specific) + */ + switch (PCI_DEV(dev) & 0x03) { + case 0: + int_line = 27 + 2; + break; + case 1: + int_line = 27 + 3; + break; + case 2: + int_line = 27 + 0; + break; + case 3: + int_line = 27 + 1; + break; + } + + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); +} + +int pci_pre_init(struct pci_controller *hose) +{ + hose->fixup_irq = cpci405_pci_fixup_irq; + return 1; +} +#endif /* defined(CONFIG_PCI) */ + #ifdef CONFIG_CPCI405AB -#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ +#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ |= CFG_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ +#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ &= ~CFG_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \ +#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \ & CFG_FPGA_MODE_1WIRE) /* @@ -581,7 +601,6 @@ int OWTouchReset(void) return result; } - /* * Send 1 a 1-wire write bit. * Provide 10us recovery time. @@ -607,7 +626,6 @@ void OWWriteBit(int bit) } } - /* * Read a bit from the 1-wire bus and return it. * Provide 10us recovery time. @@ -627,7 +645,6 @@ int OWReadBit(void) return result; } - void OWWriteByte(int data) { int loop; @@ -638,7 +655,6 @@ void OWWriteByte(int data) } } - int OWReadByte(void) { int loop, result = 0; @@ -653,7 +669,6 @@ int OWReadByte(void) return result; } - int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { volatile unsigned short val; @@ -694,7 +709,6 @@ U_BOOT_CMD( NULL ); - #define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ #define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ |