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Diffstat (limited to 'board/amcc/ocotea')
| -rw-r--r-- | board/amcc/ocotea/README.ocotea | 73 | ||||
| -rw-r--r-- | board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot | 99 |
2 files changed, 172 insertions, 0 deletions
diff --git a/board/amcc/ocotea/README.ocotea b/board/amcc/ocotea/README.ocotea new file mode 100644 index 0000000..be79b03 --- /dev/null +++ b/board/amcc/ocotea/README.ocotea @@ -0,0 +1,73 @@ + AMCC Ocotea Board + + Last Update: March 2, 2004 +======================================================================= + +This file contains some handy info regarding U-Boot and the AMCC +Ocotea 440gx evaluation board. See the README.ppc440 for additional +information. + + +SWITCH SETTINGS & JUMPERS +========================== + +Here's what I've been using successfully. If you feel inclined to +change things ... please read the docs! + +DIPSW U46 U80 +------------------------ +SW 1 off off +SW 2 on off +SW 3 off off +SW 4 off off +SW 5 off off +SW 6 on on +SW 7 on off +SW 8 on off + +J41: strapped +J42: open + +All others are factory default. + + +I2C Information +===================== + +See README.ebony for information. + +PCI +=========================== + +Untested at the time of writing. + +PPC440GX Ethernet EMACs +=========================== + +All EMAC ports have been tested and are known to work +with EPS Group 4. + +Special note about the Cicada CIS8201: + The CIS8201 Gigabit PHY comes up in GMII mode by default. + One must hit an extended register to allow use of RGMII mode. + This has been done in the 440gx_enet.c file with a #ifdef/endif + pair. + +AMCC does not store the EMAC ethernet addresses within their PIBS bootloader. +The addresses contained in the config header file are from my particular +board and you _*should*_ change them to reflect your board either in the +config file and/or in your environment variables. I found the addresses on +labels on the bottom side of the board. + + +BDI2k or JTAG Debugging +=========================== + +For ease of debugging you can swap the small boot flash and external SRAM +by changing U46:3 to on. You can then use the sram as your boot flash by +loading the sram via the jtag debugger. + + +Regards, +--Travis +<tsawyer@sandburst.com> diff --git a/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot b/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot new file mode 100644 index 0000000..25dd2a2 --- /dev/null +++ b/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot @@ -0,0 +1,99 @@ +------------------------------------------ +Installation of U-Boot using PIBS firmware +------------------------------------------ + +This document describes how to install U-Boot on the Ocotea PPC440GX +Evaluation Board. We do not erase the PIBS firmware but install U-Boot in the +soldered FLASH. After this you should be able to switch between PIBS and +U-Boot via the switch U46 SW1. Please check that SW1 is off (= open) before +continuing. + +Connect to the serial port 0 (J11 lower) of the Ocotea board using the cu +program. See the hints for configuring cu above. Make sure you can +communicate with the PIBS firmware: reset the board and hit ENTER a couple of +times until you see the PIBS prompt (PIBS $). Then proceed as follows: + + +Read MAC Addresses from PIBS +---------------------------- + +To read the configured MAC addresses available on your Ocotea board please use +the following commands: + +PIBS $ echo $hwdaddr0 +000173017FE3 +PIBS $ echo $hwdaddr1 +000173017FE4 +PIBS $ echo $hwdaddr2 +000173017FE1 +PIBS $ echo $hwdaddr3 +000173017FE2 + +In U-Boot this is stored in the following environment variables: + +* Ethernet Address 0: ethaddr = 000173017FE3 (==> 00:01:73:01:7F:E3) +* Ethernet Address 1: eth1addr = 000173017FE4 (==> 00:01:73:01:7F:E4) +* Ethernet Address 2: eth2addr = 000173017FE1 (==> 00:01:73:01:7F:E1) +* Ethernet Address 3: eth3addr = 000173017FE2 (==> 00:01:73:01:7F:E2) + + +Configure the network interface (ent0 == emac0) +----------------------------------------------- + +To download the U-Boot image we need to configure the ethernet interface with +the following commands: + +PIBS $ ifconfig ent0 192.168.160.142 netmask 255.255.0.0 up +PIBS $ set ipdstaddr0=192.168.1.1 +status: writing PIBS variable value to FLASH +PIBS $ set bootfilename=/tftpboot/ocotea/u-boot.bin +status: writing PIBS variable value to FLASH + +Please insert correct parameters for your configuration (ip-addresses and +file-location). + + +Program U-Boot into soldered User-FLASH +--------------------------------------- + +Please make sure to use a newer version of U-Boot (at least 1.1.3), since +older versions don't support running from user-FLASH. + +To program U-Boot into the soldered user-FLASH use the following command: + +PIBS $ storefile bin eth 0xffbc0000 + +This commands loads the file vis ethernet into ram and copies it into the +user-FLASH. + + +Switch to U-Boot +---------------- + +Now you can turn your board off and switch SW1 (U46) to on (= closed). After +powering the board you should see the following message: + +U-Boot 1.1.3 (Apr 5 2005 - 22:59:57) + +AMCC PowerPC 440 GX Rev. C +Board: AMCC 440GX Evaluation Board + VCO: 1066 MHz + CPU: 533 MHz + PLB: 152 MHz + OPB: 76 MHz + EPB: 76 MHz +I2C: ready +DRAM: 256 MB +FLASH: 5 MB +PCI: Bus Dev VenId DevId Class Int +In: serial +Out: serial +Err: serial +KGDB: kgdb ready +ready +Net: ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3 +BEDBUG:ready +=> + + +April 06 2005, Stefan Roese <sr@denx.de> |