summaryrefslogtreecommitdiff
path: root/board/BuR
diff options
context:
space:
mode:
Diffstat (limited to 'board/BuR')
-rw-r--r--board/BuR/kwb/Makefile12
-rw-r--r--board/BuR/kwb/board.c240
-rw-r--r--board/BuR/kwb/mux.c195
3 files changed, 447 insertions, 0 deletions
diff --git a/board/BuR/kwb/Makefile b/board/BuR/kwb/Makefile
new file mode 100644
index 0000000..7b04b26
--- /dev/null
+++ b/board/BuR/kwb/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile
+#
+# Copyright (C) 2014 Hannes Petermaier <oe5hpm@oevsv.at> -
+# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-y += ../common/common.o
+obj-y += board.o
diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c
new file mode 100644
index 0000000..8aa16bc
--- /dev/null
+++ b/board/BuR/kwb/board.c
@@ -0,0 +1,240 @@
+/*
+ * board.c
+ *
+ * Board functions for B&R KWB Board
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+
+/* -------------------------------------------------------------------------*/
+/* -- defines for used GPIO Hardware -- */
+#define KEY (0+4)
+#define LCD_PWR (0+5)
+#define PUSH_KEY (0+31)
+#define USB2SD_NRST (32+29)
+#define USB2SD_PWR (96+13)
+/* -------------------------------------------------------------------------*/
+/* -- PSOC Resetcontroller Register defines -- */
+
+/* I2C Address of controller */
+#define RSTCTRL_ADDR 0x75
+/* Register for CTRL-word */
+#define RSTCTRL_CTRLREG 0x01
+/* Register for giving some information to VxWorks OS */
+#define RSTCTRL_SCRATCHREG 0x04
+
+/* -- defines for RSTCTRL_CTRLREG -- */
+#define RSTCTRL_FORCE_PWR_NEN 0x0404
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ unsigned int oldspeed;
+ unsigned short buf;
+
+ struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+ struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+ /*
+ * enable additional clocks of modules which are accessed later from
+ * VxWorks OS
+ */
+ u32 *const clk_domains[] = { 0 };
+
+ u32 *const clk_modules_kwbspecific[] = {
+ &cmwkup->wkup_adctscctrl,
+ &cmper->spi1clkctrl,
+ &cmper->dcan0clkctrl,
+ &cmper->dcan1clkctrl,
+ &cmper->epwmss0clkctrl,
+ &cmper->epwmss1clkctrl,
+ &cmper->epwmss2clkctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
+
+ /* power-OFF LCD-Display */
+ gpio_direction_output(LCD_PWR, 0);
+
+ /* setup I2C */
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ /* power-ON 3V3 via Resetcontroller */
+ oldspeed = i2c_get_bus_speed();
+ if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
+ buf = RSTCTRL_FORCE_PWR_NEN;
+ i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
+ (uint8_t *)&buf, sizeof(buf));
+ i2c_set_bus_speed(oldspeed);
+ } else {
+ puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
+ }
+
+#if defined(CONFIG_AM335X_USB0)
+ /* power on USB2SD Controller */
+ gpio_direction_output(USB2SD_PWR, 1);
+ mdelay(1);
+ /* give a reset Pulse to USB2SD Controller */
+ gpio_direction_output(USB2SD_NRST, 0);
+ mdelay(1);
+ gpio_set_value(USB2SD_NRST, 1);
+#endif
+ pmicsetup(0);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+ config_ddr(400, &ddr3_ioregs,
+ &ddr3_data,
+ &ddr3_cmd_ctrl_data,
+ &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ gpmc_init();
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ const unsigned int ton = 250;
+ const unsigned int toff = 1000;
+ unsigned int cnt = 3;
+ unsigned short buf = 0xAAAA;
+ unsigned int oldspeed;
+
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */
+
+ if (gpio_get_value(KEY)) {
+ do {
+ /* turn on light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x09, 0xFF);
+ mdelay(ton);
+ /* turn off light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x01, 0xFF);
+ mdelay(toff);
+ cnt--;
+ if (!gpio_get_value(KEY) &&
+ gpio_get_value(PUSH_KEY) && 1 == cnt) {
+ puts("updating from USB ...\n");
+ setenv("bootcmd", "run usbupdate");
+ break;
+ } else if (!gpio_get_value(KEY)) {
+ break;
+ }
+ } while (cnt);
+ }
+
+ switch (cnt) {
+ case 0:
+ puts("3 blinks ... entering BOOT mode.\n");
+ buf = 0x0000;
+ break;
+ case 1:
+ puts("2 blinks ... entering DIAGNOSE mode.\n");
+ buf = 0x0F0F;
+ break;
+ case 2:
+ puts("1 blinks ... entering SERVICE mode.\n");
+ buf = 0xB4B4;
+ break;
+ case 3:
+ puts("0 blinks ... entering RUN mode.\n");
+ buf = 0x0404;
+ break;
+ }
+ mdelay(ton);
+ /* turn on light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x09, 0xFF);
+ /* write bootinfo into scratchregister of resetcontroller */
+ oldspeed = i2c_get_bus_speed();
+ if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
+ i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
+ (uint8_t *)&buf, sizeof(buf));
+ i2c_set_bus_speed(oldspeed);
+ } else {
+ puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
+ }
+ /*
+ * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
+ * expect that vectors are there, original u-boot moves them to _start
+ */
+ __asm__("ldr r0,=0x20000");
+ __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
+
+ return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c
new file mode 100644
index 0000000..1a5ffd5
--- /dev/null
+++ b/board/BuR/kwb/mux.c
@@ -0,0 +1,195 @@
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux usb0_pin_mux[] = {
+ {OFFSET(usb0_id), (MODE(0) | RXACTIVE)},
+ /* USB0 DrvBus Receiver disable (from romcode 0x20) */
+ {OFFSET(usb0_drvvbus), (MODE(0))},
+ /* USB1 DrvBus as GPIO due to HW-Workaround */
+ {OFFSET(usb1_drvvbus), (MODE(7))},
+ {-1},
+};
+static struct module_pin_mux spi1_pin_mux[] = {
+ /* SPI1_SCLK */
+ {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_D0 */
+ {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_D1 */
+ {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_CS0 */
+ {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux dcan0_pin_mux[] = {
+ /* DCAN0 TX */
+ {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
+ /* DCAN0 RX */
+ {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux dcan1_pin_mux[] = {
+ /* DCAN1 TX */
+ {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
+ /* DCAN1 RX */
+ {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux gpios[] = {
+ /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+ {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
+ /* GPIO0_4 (SPI D1) - TA602 */
+ {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */
+ {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},
+ /* GPIO0_7 (PWW0 OUT) - CAN TERM */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */
+ {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)},
+ /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */
+ {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)},
+ /* GPIO0_30 (GPMC_WAIT0) - TA601 */
+ {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
+ {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
+ /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
+ {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+ /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO2_4 (GPMC_nWE) - TST_BAST */
+ {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
+ /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
+ {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
+ {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
+ {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
+ {-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ /* UART0_CTS */
+ {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_RXD */
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_TXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ /* I2C_DATA */
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ /* I2C_SCLK */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+
+ {-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+ {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
+ {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
+ {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
+ {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
+ {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
+ {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
+ {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
+ {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
+ {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
+ {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
+ {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
+ {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
+ {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
+ {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
+ {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
+ {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
+
+ {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
+ {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
+ {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
+ {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
+ {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
+ {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
+ {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
+ {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
+
+ {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
+ {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
+ {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+ {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
+
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(usb0_pin_mux);
+ configure_module_pin_mux(spi1_pin_mux);
+ configure_module_pin_mux(dcan0_pin_mux);
+ configure_module_pin_mux(dcan1_pin_mux);
+ configure_module_pin_mux(mmc1_pin_mux);
+ configure_module_pin_mux(lcd_pin_mux);
+ configure_module_pin_mux(gpios);
+}
generated by cgit v1.1 at 2024-11-27 11:49:16 +0000