diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/Kconfig | 10 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/ks8695/Makefile | 9 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 189 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/ks8695/timer.c | 77 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-ks8695/platform.h | 294 |
6 files changed, 0 insertions, 580 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0bed390..db31be9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -88,14 +88,6 @@ config TARGET_SCB9328 bool "Support scb9328" select CPU_ARM920T -config TARGET_CM4008 - bool "Support cm4008" - select CPU_ARM920T - -config TARGET_CM41XX - bool "Support cm41xx" - select CPU_ARM920T - config TARGET_VCMA9 bool "Support VCMA9" select CPU_ARM920T @@ -769,8 +761,6 @@ source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" source "board/cirrus/edb93xx/Kconfig" -source "board/cm4008/Kconfig" -source "board/cm41xx/Kconfig" source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_fx6/Kconfig" source "board/congatec/cgtqmx6eval/Kconfig" diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index a16838b..29a350c 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -13,5 +13,4 @@ obj-$(CONFIG_USE_IRQ) += interrupts.o obj-$(if $(filter a320,$(SOC)),y) += a320/ obj-$(CONFIG_EP93XX) += ep93xx/ obj-$(CONFIG_IMX) += imx/ -obj-$(CONFIG_KS8695) += ks8695/ obj-$(CONFIG_S3C24X0) += s3c24x0/ diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile deleted file mode 100644 index 400aa89..0000000 --- a/arch/arm/cpu/arm920t/ks8695/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = lowlevel_init.o -obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S deleted file mode 100644 index a2a07f2..0000000 --- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +++ /dev/null @@ -1,189 +0,0 @@ -/* - * lowlevel_init.S - basic hardware initialization for the KS8695 CPU - * - * Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/platform.h> - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - -/* - ************************************************************************* - * - * Handy dandy macros - * - ************************************************************************* - */ - -/* Delay a bit */ -.macro DELAY_FOR cycles, reg0 - ldr \reg0, =\cycles - subs \reg0, \reg0, #1 - subne pc, pc, #0xc -.endm - -/* - ************************************************************************* - * - * Some local storage. - * - ************************************************************************* - */ - -/* Should we boot with an interactive console or not */ -.globl serial_console - -/* - ************************************************************************* - * - * Raw hardware initialization code. The important thing is to get - * SDRAM setup and running. We do some other basic things here too, - * like getting the PLL set for high speed, and init the LEDs. - * - ************************************************************************* - */ - -.globl lowlevel_init -lowlevel_init: - -#if DEBUG - /* - * enable UART for early debug trace - */ - ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR) - mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE) - str r2, [r1] - ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL) - mov r2, #KS8695_UART_LINEC_WLEN8 - str r2, [r1] /* 8 data bits, no parity, 1 stop */ - ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) - mov r2, #0x41 - str r2, [r1] /* write 'A' */ -#endif -#if DEBUG - ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) - mov r2, #0x42 - str r2, [r1] -#endif - - /* - * remap the memory and flash regions. we want to end up with - * ram from address 0, and flash at 32MB. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0) - ldr r2, =0xbfc00040 - str r2, [r1] /* large flash map */ - ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */ -highflash: - ldr r2, =0x8fe00040 - str r2, [r1] /* remap flash range */ - - /* - * remap the second select region to the 4MB immediately after - * the first region. This way if you have a larger flash (say 8Mb) - * then you can have it all mapped nicely. Has no effect if you - * only have a 4Mb or smaller flash. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1) - ldr r2, =0x9fe40040 - str r2, [r1] /* remap flash2 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL) - ldr r2, =0x30000005 - str r2, [r1] /* enable both flash selects */ - -#ifdef CONFIG_CM41xx - /* - * map the second flash chip, using the external IO lines. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0) - ldr r2, =0xafe80b6d - str r2, [r1] /* remap io0 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1) - ldr r2, =0xbfec0b6d - str r2, [r1] /* remap io1 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL) - ldr r2, =0x30050005 - str r2, [r1] /* enable second flash */ -#endif - - /* - * before relocating, we have to setup RAM timing - */ - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0) -#if (PHYS_SDRAM_1_SIZE == 0x02000000) - ldr r2, =0x7fc0000e /* 32MB */ -#else - ldr r2, =0x3fc0000e /* 16MB */ -#endif - str r2, [r1] /* configure sdram bank0 setup */ - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1) - mov r2, #0 - str r2, [r1] /* configure sdram bank1 setup */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL) - ldr r2, =0x0000000a - str r2, [r1] /* set RAS/CAS timing */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER) - ldr r2, =0x00030000 - str r2, [r1] /* send NOP command */ - DELAY_FOR 0x100, r0 - ldr r2, =0x00010000 - str r2, [r1] /* send PRECHARGE-ALL */ - DELAY_FOR 0x100, r0 - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH) - ldr r2, =0x00000020 - str r2, [r1] /* set for fast refresh */ - DELAY_FOR 0x100, r0 - ldr r2, =0x00000190 - str r2, [r1] /* set normal refresh timing */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER) - ldr r2, =0x00020033 - str r2, [r1] /* send mode command */ - DELAY_FOR 0x100, r0 - ldr r2, =0x01f00000 - str r2, [r1] /* enable sdram fifos */ - - /* - * set pll to top speed - */ - ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK) - mov r2, #0 - str r2, [r1] /* set pll clock to 166MHz */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0) - ldr r2, [r1] /* Get switch ctrl0 register */ - and r2, r2, #0x0fc00000 /* Mask out LED control bits */ - orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */ - str r2, [r1] - -#ifdef CONFIG_CM4008 - ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE) - ldr r2, =0x0000fe30 - str r2, [r1] /* enable LED's as outputs */ - ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA) - ldr r2, =0x0000fe20 - str r2, [r1] /* turn on power LED */ -#endif -#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx) - ldr r2, [r1] /* get current GPIO input data */ - tst r2, #0x8 /* check if "erase" depressed */ - beq nobutton - mov r2, #0 /* be quiet on boot, no console */ - ldr r1, =serial_console - str r2, [r1] -nobutton: -#endif - - add lr, lr, #0x02000000 /* flash is now mapped high */ - add ip, ip, #0x02000000 /* this is a hack */ - mov pc, lr /* all done, return */ - -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/arch/arm/cpu/arm920t/ks8695/timer.c b/arch/arm/cpu/arm920t/ks8695/timer.c deleted file mode 100644 index 23db557..0000000 --- a/arch/arm/cpu/arm920t/ks8695/timer.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/platform.h> - -/* - * Initial timer set constants. Nothing complicated, just set for a 1ms - * tick. - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1) -#define TIMER_COUNT (TIMER_INTERVAL / 2) -#define TIMER_PULSE TIMER_COUNT - -/* - * Handy KS8695 register access functions. - */ -#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a))) -#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v) - -ulong timer_ticks; - -int timer_init (void) -{ - /* Set the hadware timer for 1ms */ - ks8695_write(KS8695_TIMER1, TIMER_COUNT); - ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE); - ks8695_write(KS8695_TIMER_CTRL, 0x2); - timer_ticks = 0; - - return 0; -} - -ulong get_timer_masked(void) -{ - /* Check for timer wrap */ - if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) { - /* Clear interrupt condition */ - ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1); - timer_ticks++; - } - return timer_ticks; -} - -ulong get_timer(ulong base) -{ - return (get_timer_masked() - base); -} - -void __udelay(ulong usec) -{ - ulong start = get_timer_masked(); - ulong end; - - /* Only 1ms resolution :-( */ - end = usec / 1000; - while (get_timer(start) < end) - ; -} - -void reset_cpu (ulong ignored) -{ - ulong tc; - - /* Set timer0 to watchdog, and let it timeout */ - tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2; - ks8695_write(KS8695_TIMER_CTRL, tc); - ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff)); - ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1)); - - /* Should only wait here till watchdog resets */ - for (;;) - ; -} diff --git a/arch/arm/include/asm/arch-ks8695/platform.h b/arch/arm/include/asm/arch-ks8695/platform.h deleted file mode 100644 index 02f6049..0000000 --- a/arch/arm/include/asm/arch-ks8695/platform.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __address_h -#define __address_h 1 - -#define KS8695_SDRAM_START 0x00000000 -#define KS8695_SDRAM_SIZE 0x01000000 -#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE -#define KS8695_MEM_START KS8695_SDRAM_START - -#define KS8695_PCMCIA_IO_BASE 0x03800000 -#define KS8695_PCMCIA_IO_SIZE 0x00040000 - -#define KS8695_IO_BASE 0x03FF0000 -#define KS8695_IO_SIZE 0x00010000 - -#define KS8695_SYSTEN_CONFIG 0x00 -#define KS8695_SYSTEN_BUS_CLOCK 0x04 - -#define KS8695_FLASH_START 0x02800000 -#define KS8695_FLASH_SIZE 0x00400000 - -/*i/o control registers offset difinitions*/ -#define KS8695_IO_CTRL0 0x4000 -#define KS8695_IO_CTRL1 0x4004 -#define KS8695_IO_CTRL2 0x4008 -#define KS8695_IO_CTRL3 0x400C - -/*memory control registers offset difinitions*/ -#define KS8695_MEM_CTRL0 0x4010 -#define KS8695_MEM_CTRL1 0x4014 -#define KS8695_MEM_CTRL2 0x4018 -#define KS8695_MEM_CTRL3 0x401C -#define KS8695_MEM_GENERAL 0x4020 -#define KS8695_SDRAM_CTRL0 0x4030 -#define KS8695_SDRAM_CTRL1 0x4034 -#define KS8695_SDRAM_GENERAL 0x4038 -#define KS8695_SDRAM_BUFFER 0x403C -#define KS8695_SDRAM_REFRESH 0x4040 - -/*WAN control registers offset difinitions*/ -#define KS8695_WAN_DMA_TX 0x6000 -#define KS8695_WAN_DMA_RX 0x6004 -#define KS8695_WAN_DMA_TX_START 0x6008 -#define KS8695_WAN_DMA_RX_START 0x600C -#define KS8695_WAN_TX_LIST 0x6010 -#define KS8695_WAN_RX_LIST 0x6014 -#define KS8695_WAN_MAC_LOW 0x6018 -#define KS8695_WAN_MAC_HIGH 0x601C -#define KS8695_WAN_MAC_ELOW 0x6080 -#define KS8695_WAN_MAC_EHIGH 0x6084 - -/*LAN control registers offset difinitions*/ -#define KS8695_LAN_DMA_TX 0x8000 -#define KS8695_LAN_DMA_RX 0x8004 -#define KS8695_LAN_DMA_TX_START 0x8008 -#define KS8695_LAN_DMA_RX_START 0x800C -#define KS8695_LAN_TX_LIST 0x8010 -#define KS8695_LAN_RX_LIST 0x8014 -#define KS8695_LAN_MAC_LOW 0x8018 -#define KS8695_LAN_MAC_HIGH 0x801C -#define KS8695_LAN_MAC_ELOW 0X8080 -#define KS8695_LAN_MAC_EHIGH 0X8084 - -/*HPNA control registers offset difinitions*/ -#define KS8695_HPNA_DMA_TX 0xA000 -#define KS8695_HPNA_DMA_RX 0xA004 -#define KS8695_HPNA_DMA_TX_START 0xA008 -#define KS8695_HPNA_DMA_RX_START 0xA00C -#define KS8695_HPNA_TX_LIST 0xA010 -#define KS8695_HPNA_RX_LIST 0xA014 -#define KS8695_HPNA_MAC_LOW 0xA018 -#define KS8695_HPNA_MAC_HIGH 0xA01C -#define KS8695_HPNA_MAC_ELOW 0xA080 -#define KS8695_HPNA_MAC_EHIGH 0xA084 - -/*UART control registers offset difinitions*/ -#define KS8695_UART_RX_BUFFER 0xE000 -#define KS8695_UART_TX_HOLDING 0xE004 - -#define KS8695_UART_FIFO_CTRL 0xE008 -#define KS8695_UART_FIFO_TRIG01 0x00 -#define KS8695_UART_FIFO_TRIG04 0x80 -#define KS8695_UART_FIFO_TXRST 0x03 -#define KS8695_UART_FIFO_RXRST 0x02 -#define KS8695_UART_FIFO_FEN 0x01 - -#define KS8695_UART_LINE_CTRL 0xE00C -#define KS8695_UART_LINEC_BRK 0x40 -#define KS8695_UART_LINEC_EPS 0x10 -#define KS8695_UART_LINEC_PEN 0x08 -#define KS8695_UART_LINEC_STP2 0x04 -#define KS8695_UART_LINEC_WLEN8 0x03 -#define KS8695_UART_LINEC_WLEN7 0x02 -#define KS8695_UART_LINEC_WLEN6 0x01 -#define KS8695_UART_LINEC_WLEN5 0x00 - -#define KS8695_UART_MODEM_CTRL 0xE010 -#define KS8695_UART_MODEMC_RTS 0x02 -#define KS8695_UART_MODEMC_DTR 0x01 - -#define KS8695_UART_LINE_STATUS 0xE014 -#define KS8695_UART_LINES_TXFE 0x20 -#define KS8695_UART_LINES_BE 0x10 -#define KS8695_UART_LINES_FE 0x08 -#define KS8695_UART_LINES_PE 0x04 -#define KS8695_UART_LINES_OE 0x02 -#define KS8695_UART_LINES_RXFE 0x01 -#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE) - -#define KS8695_UART_MODEM_STATUS 0xE018 -#define KS8695_UART_MODEM_DCD 0x80 -#define KS8695_UART_MODEM_DSR 0x20 -#define KS8695_UART_MODEM_CTS 0x10 -#define KS8695_UART_MODEM_DDCD 0x08 -#define KS8695_UART_MODEM_DDSR 0x02 -#define KS8695_UART_MODEM_DCTS 0x01 -#define UART8695_MODEM_ANY 0xFF - -#define KS8695_UART_DIVISOR 0xE01C -#define KS8695_UART_STATUS 0xE020 - -/*Interrupt controlller registers offset difinitions*/ -#define KS8695_INT_CONTL 0xE200 -#define KS8695_INT_ENABLE 0xE204 -#define KS8695_INT_ENABLE_MODEM 0x0800 -#define KS8695_INT_ENABLE_ERR 0x0400 -#define KS8695_INT_ENABLE_RX 0x0200 -#define KS8695_INT_ENABLE_TX 0x0100 - -#define KS8695_INT_STATUS 0xE208 -#define KS8695_INT_WAN_PRIORITY 0xE20C -#define KS8695_INT_HPNA_PRIORITY 0xE210 -#define KS8695_INT_LAN_PRIORITY 0xE214 -#define KS8695_INT_TIMER_PRIORITY 0xE218 -#define KS8695_INT_UART_PRIORITY 0xE21C -#define KS8695_INT_EXT_PRIORITY 0xE220 -#define KS8695_INT_CHAN_PRIORITY 0xE224 -#define KS8695_INT_BUSERROR_PRO 0xE228 -#define KS8695_INT_MASK_STATUS 0xE22C -#define KS8695_FIQ_PEND_PRIORITY 0xE230 -#define KS8695_IRQ_PEND_PRIORITY 0xE234 - -/*timer registers offset difinitions*/ -#define KS8695_TIMER_CTRL 0xE400 -#define KS8695_TIMER1 0xE404 -#define KS8695_TIMER0 0xE408 -#define KS8695_TIMER1_PCOUNT 0xE40C -#define KS8695_TIMER0_PCOUNT 0xE410 - -/*GPIO registers offset difinitions*/ -#define KS8695_GPIO_MODE 0xE600 -#define KS8695_GPIO_CTRL 0xE604 -#define KS8695_GPIO_DATA 0xE608 - -/*SWITCH registers offset difinitions*/ -#define KS8695_SWITCH_CTRL0 0xE800 -#define KS8695_SWITCH_CTRL1 0xE804 -#define KS8695_SWITCH_PORT1 0xE808 -#define KS8695_SWITCH_PORT2 0xE80C -#define KS8695_SWITCH_PORT3 0xE810 -#define KS8695_SWITCH_PORT4 0xE814 -#define KS8695_SWITCH_PORT5 0xE818 -#define KS8695_SWITCH_AUTO0 0xE81C -#define KS8695_SWITCH_AUTO1 0xE820 -#define KS8695_SWITCH_LUE_CTRL 0xE824 -#define KS8695_SWITCH_LUE_HIGH 0xE828 -#define KS8695_SWITCH_LUE_LOW 0xE82C -#define KS8695_SWITCH_ADVANCED 0xE830 - -#define KS8695_SWITCH_LPPM12 0xE874 -#define KS8695_SWITCH_LPPM34 0xE878 - -/*host communication registers difinitions*/ -#define KS8695_DSCP_HIGH 0xE834 -#define KS8695_DSCP_LOW 0xE838 -#define KS8695_SWITCH_MAC_HIGH 0xE83C -#define KS8695_SWITCH_MAC_LOW 0xE840 - -/*miscellaneours registers difinitions*/ -#define KS8695_MANAGE_COUNTER 0xE844 -#define KS8695_MANAGE_DATA 0xE848 -#define KS8695_LAN12_POWERMAGR 0xE84C -#define KS8695_LAN34_POWERMAGR 0xE850 - -#define KS8695_DEVICE_ID 0xEA00 -#define KS8695_REVISION_ID 0xEA04 - -#define KS8695_MISC_CONTROL 0xEA08 -#define KS8695_WAN_CONTROL 0xEA0C -#define KS8695_WAN_POWERMAGR 0xEA10 -#define KS8695_WAN_PHY_CONTROL 0xEA14 -#define KS8695_WAN_PHY_STATUS 0xEA18 - -/* bus clock definitions*/ -#define KS8695_BUS_CLOCK_125MHZ 0x0 -#define KS8695_BUS_CLOCK_100MHZ 0x1 -#define KS8695_BUS_CLOCK_62MHZ 0x2 -#define KS8695_BUS_CLOCK_50MHZ 0x3 -#define KS8695_BUS_CLOCK_41MHZ 0x4 -#define KS8695_BUS_CLOCK_33MHZ 0x5 -#define KS8695_BUS_CLOCK_31MHZ 0x6 -#define KS8695_BUS_CLOCK_25MHZ 0x7 - -/* ------------------------------------------------------------------------------- - * definations for IRQ - * -------------------------------------------------------------------------------*/ - -#define KS8695_INT_EXT_INT0 2 -#define KS8695_INT_EXT_INT1 3 -#define KS8695_INT_EXT_INT2 4 -#define KS8695_INT_EXT_INT3 5 -#define KS8695_INT_TIMERINT0 6 -#define KS8695_INT_TIMERINT1 7 -#define KS8695_INT_UART_TX 8 -#define KS8695_INT_UART_RX 9 -#define KS8695_INT_UART_LINE_ERR 10 -#define KS8695_INT_UART_MODEMS 11 -#define KS8695_INT_LAN_STOP_RX 12 -#define KS8695_INT_LAN_STOP_TX 13 -#define KS8695_INT_LAN_BUF_RX_STATUS 14 -#define KS8695_INT_LAN_BUF_TX_STATUS 15 -#define KS8695_INT_LAN_RX_STATUS 16 -#define KS8695_INT_LAN_TX_STATUS 17 -#define KS8695_INT_HPAN_STOP_RX 18 -#define KS8695_INT_HPNA_STOP_TX 19 -#define KS8695_INT_HPNA_BUF_RX_STATUS 20 -#define KS8695_INT_HPNA_BUF_TX_STATUS 21 -#define KS8695_INT_HPNA_RX_STATUS 22 -#define KS8695_INT_HPNA_TX_STATUS 23 -#define KS8695_INT_BUS_ERROR 24 -#define KS8695_INT_WAN_STOP_RX 25 -#define KS8695_INT_WAN_STOP_TX 26 -#define KS8695_INT_WAN_BUF_RX_STATUS 27 -#define KS8695_INT_WAN_BUF_TX_STATUS 28 -#define KS8695_INT_WAN_RX_STATUS 29 -#define KS8695_INT_WAN_TX_STATUS 30 - -#define KS8695_INT_UART KS8695_INT_UART_TX - -/* ------------------------------------------------------------------------------- - * Interrupt bit positions - * - * ------------------------------------------------------------------------------- - */ - -#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 ) -#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 ) -#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 ) -#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 ) -#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 ) -#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 ) -#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX ) -#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX ) -#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR ) -#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS ) -#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX ) -#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX ) -#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS ) -#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS ) -#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) -#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) -#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX ) -#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX ) -#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS ) -#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS -#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS ) -#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS ) -#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR ) -#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX ) -#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX ) -#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS ) -#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS ) -#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS ) -#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS ) - -#define KS8695_SC_VALID_INT 0xFFFFFFFF -#define MAXIRQNUM 31 - -/* - * Timer definitions - * - * Use timer 1 & 2 - * (both run at 25MHz). - * - */ -#define TICKS_PER_uSEC 25 -#define mSEC_1 1000 -#define mSEC_10 (mSEC_1 * 10) - -#endif - -/* END */ |