diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 71b9c89..8897f2c 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -418,6 +418,40 @@ static void set_uart_from_osc(void) writel(reg, CCM_BASE_ADDR + 0x24); } +static void imx_set_vddpu_power_down(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + u32 val; + + /* need to power down xPU in GPC before turn off PU LDO */ + val = readl(GPC_BASE_ADDR + 0x260); + writel(val | 0x1, GPC_BASE_ADDR + 0x260); + + val = readl(GPC_BASE_ADDR + 0x0); + writel(val | 0x1, GPC_BASE_ADDR + 0x0); + while (readl(GPC_BASE_ADDR + 0x0) & 0x1) + ; + + /* disable VDDPU */ + val = 0x3e00; + writel(val, &anatop->reg_core_clr); +} + +static void imx_set_pcie_phy_power_down(void) +{ + u32 val; + + if (!is_cpu_type(MXC_CPU_MX6SX)) { + val = readl(IOMUXC_BASE_ADDR + 0x4); + val |= 0x1 << 18; + writel(val, IOMUXC_BASE_ADDR + 0x4); + } else { + val = readl(IOMUXC_GPR_BASE_ADDR + 0x30); + val |= 0x1 << 30; + writel(val, IOMUXC_GPR_BASE_ADDR + 0x30); + } +} + int arch_cpu_init(void) { init_aips(); @@ -492,6 +526,14 @@ int arch_cpu_init(void) imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ + if (!is_mx6sl() && !is_mx6ul() && + !is_mx6ull() && !is_mx6sll()) + imx_set_pcie_phy_power_down(); + + if (!is_mx6dqp() && !is_mx6ul() && + !is_mx6ull() && !is_mx6sll()) + imx_set_vddpu_power_down(); + #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ mxs_dma_init(); |