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-rw-r--r--arch/arm/cpu/armv7/exynos/Kconfig4
-rw-r--r--arch/arm/dts/Makefile3
-rw-r--r--arch/arm/dts/exynos5422-odroidxu3.dts45
3 files changed, 51 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index f3eadb4..7fcb5d2 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -24,6 +24,10 @@ config TARGET_TRATS2
config TARGET_ODROID
bool "Exynos4412 Odroid board"
+config TARGET_ODROID_XU3
+ bool "Exynos5422 Odroid board"
+ select OF_CONTROL
+
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
select CPU_V7_HAS_NONSEC
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e6a495c..fac16cc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -13,7 +13,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
exynos5420-peach-pit.dtb \
- exynos5800-peach-pi.dtb
+ exynos5800-peach-pi.dtb \
+ exynos5422-odroidxu3.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts
new file mode 100644
index 0000000..cff32a9
--- /dev/null
+++ b/arch/arm/dts/exynos5422-odroidxu3.dts
@@ -0,0 +1,45 @@
+/*
+ * Odroid XU3 device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "exynos54xx.dtsi"
+
+/ {
+ model = "Odroid XU3 based on EXYNOS5422";
+ compatible = "samsung,odroidxu3", "samsung,exynos5";
+
+ aliases {
+ serial0 = "/serial@12C00000";
+ console = "/serial@12C20000";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000
+ 0x50000000 0x10000000
+ 0x60000000 0x10000000
+ 0x70000000 0x10000000
+ 0x80000000 0x10000000
+ 0x90000000 0x10000000
+ 0xa0000000 0x10000000
+ 0xb0000000 0xea00000>;
+ };
+
+ serial@12C20000 {
+ status="okay";
+ };
+
+ mmc@12200000 {
+ fifoth_val = <0x201f0020>;
+ };
+
+ mmc@12220000 {
+ fifoth_val = <0x201f0020>;
+ };
+};