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-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_power_init.c3
-rw-r--r--arch/arm/cpu/armv7/omap-common/abb.c6
2 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index d25019a..1c54ab7 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -1002,7 +1002,8 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
uint32_t powered_by_linreg = 0;
int adjust_up, tmp;
- new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
+ new_brownout = DIV_ROUND_CLOSEST(new_target - new_brownout,
+ cfg->step_mV);
cur_target = readl(cfg->reg);
cur_target &= cfg->trg_mask;
diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c
index 423aeb9..a0add66 100644
--- a/arch/arm/cpu/armv7/omap-common/abb.c
+++ b/arch/arm/cpu/armv7/omap-common/abb.c
@@ -48,9 +48,9 @@ static void abb_setup_timings(u32 setup)
*/
/* calculate SR2_WTCNT_VALUE */
- sys_rate = DIV_ROUND(V_OSCK, 1000000);
- clk_cycles = DIV_ROUND(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
- sr2_cnt = DIV_ROUND(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
+ sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000);
+ clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
+ sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
setbits_le32(setup,
sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1));