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-rw-r--r--arch/x86/include/asm/acpi.h24
-rw-r--r--arch/x86/include/asm/acpi/debug.asl136
-rw-r--r--arch/x86/include/asm/acpi/globutil.asl113
-rw-r--r--arch/x86/include/asm/acpi/statdef.asl82
-rw-r--r--arch/x86/include/asm/acpi_table.h446
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/gpio.asl95
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h111
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl493
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl48
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/irqroute.h27
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/lpc.asl181
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/platform.asl36
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl13
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl211
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/usb.asl34
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/xhci.asl31
-rw-r--r--arch/x86/include/asm/arch-baytrail/device.h74
-rw-r--r--arch/x86/include/asm/arch-baytrail/iomap.h70
-rw-r--r--arch/x86/include/asm/arch-baytrail/irq.h86
-rw-r--r--arch/x86/include/asm/coreboot_tables.h19
-rw-r--r--arch/x86/include/asm/fw_cfg.h157
-rw-r--r--arch/x86/include/asm/global_data.h4
-rw-r--r--arch/x86/include/asm/irq.h4
23 files changed, 2052 insertions, 443 deletions
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
deleted file mode 100644
index 4872b92..0000000
--- a/arch/x86/include/asm/acpi.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * From coreboot
- *
- * Copyright (C) 2004 SUSE LINUX AG
- * Copyright (C) 2004 Nick Barker
- * Copyright (C) 2008-2009 coresystems GmbH
- * (Written by Stefan Reinauer <stepan@coresystems.de>)
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef __ASM_ACPI_H
-#define __ASM_ACPI_H
-
-#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */
-#define ACPI_TABLE_CREATOR "U-BootAC" /* Must be exactly 8 bytes long! */
-#define OEM_ID "U-Boot" /* Must be exactly 6 bytes long! */
-#define ASLC "U-Bo" /* Must be exactly 4 bytes long! */
-
-/* 0 = S0, 1 = S1 ...*/
-int acpi_get_slp_type(void);
-void apci_set_slp_type(int type);
-
-#endif
diff --git a/arch/x86/include/asm/acpi/debug.asl b/arch/x86/include/asm/acpi/debug.asl
new file mode 100644
index 0000000..8e7b603
--- /dev/null
+++ b/arch/x86/include/asm/acpi/debug.asl
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/debug.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* POST register region */
+OperationRegion(X80, SystemIO, 0x80, 1)
+Field(X80, ByteAcc, NoLock, Preserve)
+{
+ P80, 8
+}
+
+/* Legacy serial port register region */
+OperationRegion(CREG, SystemIO, 0x3F8, 8)
+Field(CREG, ByteAcc, NoLock, Preserve)
+{
+ CDAT, 8,
+ CDLM, 8,
+ , 8,
+ CLCR, 8,
+ CMCR, 8,
+ CLSR, 8
+}
+
+/* DINI - Initialize the serial port to 115200 8-N-1 */
+Method(DINI)
+{
+ Store(0x83, CLCR)
+ Store(0x01, CDAT) /* 115200 baud (low) */
+ Store(0x00, CDLM) /* 115200 baud (high) */
+ Store(0x03, CLCR) /* word=8 stop=1 parity=none */
+ Store(0x03, CMCR) /* DTR=1 RTS=1 out1/2=Off loop=Off */
+ Store(0x00, CDLM) /* turn off interrupts */
+}
+
+/* THRE - Wait for serial port transmitter holding register to go empty */
+Method(THRE)
+{
+ And(CLSR, 0x20, Local0)
+ While (LEqual(Local0, Zero)) {
+ And(CLSR, 0x20, Local0)
+ }
+}
+
+/* OUTX - Send a single raw character */
+Method(OUTX, 1)
+{
+ THRE()
+ Store(Arg0, CDAT)
+}
+
+/* OUTC - Send a single character, expanding LF into CR/LF */
+Method(OUTC, 1)
+{
+ If (LEqual(Arg0, 0x0a)) {
+ OUTX(0x0d)
+ }
+ OUTX(Arg0)
+}
+
+/* DBGN - Send a single hex nibble */
+Method(DBGN, 1)
+{
+ And(Arg0, 0x0f, Local0)
+ If (LLess(Local0, 10)) {
+ Add(Local0, 0x30, Local0)
+ } Else {
+ Add(Local0, 0x37, Local0)
+ }
+ OUTC(Local0)
+}
+
+/* DBGB - Send a hex byte */
+Method(DBGB, 1)
+{
+ ShiftRight(Arg0, 4, Local0)
+ DBGN(Local0)
+ DBGN(Arg0)
+}
+
+/* DBGW - Send a hex word */
+Method(DBGW, 1)
+{
+ ShiftRight(Arg0, 8, Local0)
+ DBGB(Local0)
+ DBGB(Arg0)
+}
+
+/* DBGD - Send a hex dword */
+Method(DBGD, 1)
+{
+ ShiftRight(Arg0, 16, Local0)
+ DBGW(Local0)
+ DBGW(Arg0)
+}
+
+/* Get a char from a string */
+Method(GETC, 2)
+{
+ CreateByteField(Arg0, Arg1, DBGC)
+ Return (DBGC)
+}
+
+/* DBGO - Send either a string or an integer */
+Method(DBGO, 1, Serialized)
+{
+ If (LEqual(ObjectType(Arg0), 1)) {
+ If (LGreater(Arg0, 0xffff)) {
+ DBGD(Arg0)
+ } Else {
+ If (LGreater(Arg0, 0xff)) {
+ DBGW(Arg0)
+ } Else {
+ DBGB(Arg0)
+ }
+ }
+ } Else {
+ Name(BDBG, Buffer(80) {})
+ Store(Arg0, BDBG)
+ Store(0, Local1)
+ While (One) {
+ Store(GETC(BDBG, Local1), Local0)
+ If (LEqual(Local0, 0)) {
+ Return (Zero)
+ }
+ OUTC(Local0)
+ Increment(Local1)
+ }
+ }
+
+ Return (Zero)
+}
diff --git a/arch/x86/include/asm/acpi/globutil.asl b/arch/x86/include/asm/acpi/globutil.asl
new file mode 100644
index 0000000..46381b6
--- /dev/null
+++ b/arch/x86/include/asm/acpi/globutil.asl
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/globutil.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Method(MIN, 2)
+{
+ If (LLess(Arg0, Arg1)) {
+ Return (Arg0)
+ } Else {
+ Return (Arg1)
+ }
+}
+
+Method(SLEN, 1)
+{
+ Store(Arg0, Local0)
+ Return (Sizeof(Local0))
+}
+
+Method(S2BF, 1, Serialized)
+{
+ Add(SLEN(Arg0), One, Local0)
+ Name(BUFF, Buffer(Local0) {})
+ Store(Arg0, BUFF)
+ Return (BUFF)
+}
+
+/*
+ * SCMP - Strong string compare
+ *
+ * Checks both length and content
+ */
+Method(SCMP, 2)
+{
+ Store(S2BF(Arg0), Local0)
+ Store(S2BF(Arg1), Local1)
+ Store(Zero, Local4)
+ Store(SLEN(Arg0), Local5)
+ Store(SLEN(Arg1), Local6)
+ Store(MIN(Local5, Local6), Local7)
+
+ While (LLess(Local4, Local7)) {
+ Store(Derefof(Index(Local0, Local4)), Local2)
+ Store(Derefof(Index(Local1, Local4)), Local3)
+ If (LGreater(Local2, Local3)) {
+ Return (One)
+ } Else {
+ If (LLess(Local2, Local3)) {
+ Return (Ones)
+ }
+ }
+ Increment(Local4)
+ }
+
+ If (LLess(Local4, Local5)) {
+ Return (One)
+ } Else {
+ If (LLess(Local4, Local6)) {
+ Return (Ones)
+ } Else {
+ Return (Zero)
+ }
+ }
+}
+
+/*
+ * WCMP - Weak string compare
+ *
+ * Checks to find Arg1 at beginning of Arg0.
+ * Fails if length(Arg0) < length(Arg1).
+ * Returns 0 on fail, 1 on pass.
+ */
+Method(WCMP, 2)
+{
+ Store(S2BF(Arg0), Local0)
+ Store(S2BF(Arg1), Local1)
+ If (LLess(SLEN(Arg0), SLEN(Arg1))) {
+ Return (Zero)
+ }
+ Store(Zero, Local2)
+ Store(SLEN(Arg1), Local3)
+
+ While (LLess(Local2, Local3)) {
+ If (LNotEqual(Derefof(Index(Local0, Local2)),
+ Derefof(Index(Local1, Local2)))) {
+ Return (Zero)
+ }
+ Increment(Local2)
+ }
+
+ Return (One)
+}
+
+/*
+ * I2BM - Returns Bit Map
+ *
+ * Arg0 = IRQ Number (0-15)
+ */
+Method(I2BM, 1)
+{
+ Store(0, Local0)
+ If (LNotEqual(Arg0, 0)) {
+ Store(1, Local1)
+ ShiftLeft(Local1, Arg0, Local0)
+ }
+
+ Return (Local0)
+}
diff --git a/arch/x86/include/asm/acpi/statdef.asl b/arch/x86/include/asm/acpi/statdef.asl
new file mode 100644
index 0000000..e8cff10
--- /dev/null
+++ b/arch/x86/include/asm/acpi/statdef.asl
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/statdef.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Status and notification definitions */
+
+#define STA_MISSING 0x00
+#define STA_PRESENT 0x01
+#define STA_ENABLED 0x03
+#define STA_DISABLED 0x09
+#define STA_INVISIBLE 0x0b
+#define STA_UNAVAILABLE 0x0d
+#define STA_VISIBLE 0x0f
+
+/* SMBus status codes */
+#define SMB_OK 0x00
+#define SMB_UNKNOWN_FAIL 0x07
+#define SMB_DEV_ADDR_NAK 0x10
+#define SMB_DEVICE_ERROR 0x11
+#define SMB_DEV_CMD_DENIED 0x12
+#define SMB_UNKNOWN_ERR 0x13
+#define SMB_DEV_ACC_DENIED 0x17
+#define SMB_TIMEOUT 0x18
+#define SMB_HST_UNSUPP_PROTOCOL 0x19
+#define SMB_BUSY 0x1a
+#define SMB_PKT_CHK_ERROR 0x1f
+
+/* Device Object Notification Values */
+#define NOTIFY_BUS_CHECK 0x00
+#define NOTIFY_DEVICE_CHECK 0x01
+#define NOTIFY_DEVICE_WAKE 0x02
+#define NOTIFY_EJECT_REQUEST 0x03
+#define NOTIFY_DEVICE_CHECK_JR 0x04
+#define NOTIFY_FREQUENCY_ERROR 0x05
+#define NOTIFY_BUS_MODE 0x06
+#define NOTIFY_POWER_FAULT 0x07
+#define NOTIFY_CAPABILITIES 0x08
+#define NOTIFY_PLD_CHECK 0x09
+#define NOTIFY_SLIT_UPDATE 0x0b
+#define NOTIFY_SRA_UPDATE 0x0d
+
+/* Battery Device Notification Values */
+#define NOTIFY_BAT_STATUSCHG 0x80
+#define NOTIFY_BAT_INFOCHG 0x81
+#define NOTIFY_BAT_MAINTDATA 0x82
+
+/* Power Source Object Notification Values */
+#define NOTIFY_PWR_STATUSCHG 0x80
+#define NOTIFY_PWR_INFOCHG 0x81
+
+/* Thermal Zone Object Notification Values */
+#define NOTIFY_TZ_STATUSCHG 0x80
+#define NOTIFY_TZ_TRIPPTCHG 0x81
+#define NOTIFY_TZ_DEVLISTCHG 0x82
+#define NOTIFY_TZ_RELTBLCHG 0x83
+
+/* Power Button Notification Values */
+#define NOTIFY_POWER_BUTTON 0x80
+
+/* Sleep Button Notification Values */
+#define NOTIFY_SLEEP_BUTTON 0x80
+
+/* Lid Notification Values */
+#define NOTIFY_LID_STATUSCHG 0x80
+
+/* Processor Device Notification Values */
+#define NOTIFY_CPU_PPCCHG 0x80
+#define NOTIFY_CPU_CSTATECHG 0x81
+#define NOTIFY_CPU_THROTLCHG 0x82
+
+/* User Presence Device Notification Values */
+#define NOTIFY_USR_PRESNCECHG 0x80
+
+/* Ambient Light Sensor Notification Values */
+#define NOTIFY_ALS_ILLUMCHG 0x80
+#define NOTIFY_ALS_COLORTMPCHG 0x81
+#define NOTIFY_ALS_RESPCHG 0x82
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 9856fa6..56aa282 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -2,83 +2,19 @@
* Based on acpi.c from coreboot
*
* Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
-#include <malloc.h>
-#include <asm/post.h>
-#include <linux/string.h>
-
-#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */
-#define ACPI_TABLE_CREATOR "UBOOT " /* Must be 8 bytes long! */
-#define OEM_ID "UBOOT " /* Must be 6 bytes long! */
-#define ASLC "INTL" /* Must be 4 bytes long! */
-
-#define OEM_REVISION 42
-#define ASL_COMPILER_REVISION 42
-
-/* IO ports to generate SMIs */
-#define APM_CNT 0xb2
-#define APM_CNT_CST_CONTROL 0x85
-#define APM_CNT_PST_CONTROL 0x80
-#define APM_CNT_ACPI_DISABLE 0x1e
-#define APM_CNT_ACPI_ENABLE 0xe1
-#define APM_CNT_MBI_UPDATE 0xeb
-#define APM_CNT_GNVS_UPDATE 0xea
-#define APM_CNT_FINALIZE 0xcb
-#define APM_CNT_LEGACY 0xcc
-#define APM_ST 0xb3
-
-/* Multiple Processor Interrupts */
-#define MP_IRQ_POLARITY_DEFAULT 0x0
-#define MP_IRQ_POLARITY_HIGH 0x1
-#define MP_IRQ_POLARITY_LOW 0x3
-#define MP_IRQ_POLARITY_MASK 0x3
-#define MP_IRQ_TRIGGER_DEFAULT 0x0
-#define MP_IRQ_TRIGGER_EDGE 0x4
-#define MP_IRQ_TRIGGER_LEVEL 0xc
-#define MP_IRQ_TRIGGER_MASK 0xc
-
-/*
- * Interrupt assigned for SCI in order to
- * create the ACPI MADT IRQ override entry
- */
-#define ACTL 0x00
-#define SCIS_MASK 0x07
-#define SCIS_IRQ9 0x00
-#define SCIS_IRQ10 0x01
-#define SCIS_IRQ11 0x02
-#define SCIS_IRQ20 0x04
-#define SCIS_IRQ21 0x05
-#define SCIS_IRQ22 0x06
-#define SCIS_IRQ23 0x07
-
-#define ACPI_REV_ACPI_1_0 1
-#define ACPI_REV_ACPI_2_0 1
-#define ACPI_REV_ACPI_3_0 2
-#define ACPI_REV_ACPI_4_0 3
-#define ACPI_REV_ACPI_5_0 5
+#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */
+#define OEM_ID "U-BOOT" /* U-Boot */
+#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */
+#define ASLC_ID "INTL" /* Intel ASL Compiler */
#define ACPI_RSDP_REV_ACPI_1_0 0
#define ACPI_RSDP_REV_ACPI_2_0 2
-typedef struct acpi_gen_regaddr {
- u8 space_id; /* Address space ID */
- u8 bit_width; /* Register size in bits */
- u8 bit_offset; /* Register bit offset */
- union {
- /* Reserved in ACPI 2.0 - 2.0b */
- u8 resv;
- /* Access size in ACPI 2.0c/3.0/4.0/5.0 */
- u8 access_size;
- };
- u32 addrl; /* Register address, low 32 bits */
- u32 addrh; /* Register address, high 32 bits */
-} acpi_addr_t;
-
-
/*
* RSDP (Root System Description Pointer)
* Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
@@ -87,7 +23,7 @@ struct acpi_rsdp {
char signature[8]; /* RSDP signature */
u8 checksum; /* Checksum of the first 20 bytes */
char oem_id[6]; /* OEM ID */
- u8 revision; /* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0 */
+ u8 revision; /* 0 for ACPI 1.0, others 2 */
u32 rsdt_address; /* Physical address of RSDT (32 bits) */
u32 length; /* Total RSDP length (incl. extended part) */
u64 xsdt_address; /* Physical address of XSDT (64 bits) */
@@ -95,35 +31,8 @@ struct acpi_rsdp {
u8 reserved[3];
};
-enum acpi_address_space_type {
- ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */
- ACPI_ADDRESS_SPACE_IO, /* System I/O */
- ACPI_ADDRESS_SPACE_PCI, /* PCI config space */
- ACPI_ADDRESS_SPACE_EC, /* Embedded controller */
- ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */
- ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */
- ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */
-};
-
-/* functional fixed hardware */
-#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */
-#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */
-#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */
-#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */
-#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */
-#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */
-
-/* Access size definitions for Generic address structure */
-enum acpi_address_space_size {
- ACPI_ACCESS_SIZE_UNDEFINED = 0, /* Undefined (legacy reasons) */
- ACPI_ACCESS_SIZE_BYTE_ACCESS = 1,
- ACPI_ACCESS_SIZE_WORD_ACCESS = 2,
- ACPI_ACCESS_SIZE_DWORD_ACCESS = 3,
- ACPI_ACCESS_SIZE_QWORD_ACCESS = 4
-};
-
/* Generic ACPI header, provided by (almost) all tables */
-typedef struct acpi_table_header {
+struct acpi_table_header {
char signature[4]; /* ACPI signature (4 ASCII characters) */
u32 length; /* Table length in bytes (incl. header) */
u8 revision; /* Table version (not ACPI version!) */
@@ -131,12 +40,12 @@ typedef struct acpi_table_header {
char oem_id[6]; /* OEM identification */
char oem_table_id[8]; /* OEM table identification */
u32 oem_revision; /* OEM revision number */
- char asl_compiler_id[4]; /* ASL compiler vendor ID */
- u32 asl_compiler_revision; /* ASL compiler revision number */
-} acpi_header_t;
+ char aslc_id[4]; /* ASL compiler vendor ID */
+ u32 aslc_revision; /* ASL compiler revision number */
+};
/* A maximum number of 32 ACPI tables ought to be enough for now */
-#define MAX_ACPI_TABLES 32
+#define MAX_ACPI_TABLES 32
/* RSDT (Root System Description Table) */
struct acpi_rsdt {
@@ -150,103 +59,80 @@ struct acpi_xsdt {
u64 entry[MAX_ACPI_TABLES];
};
-/* MCFG (PCI Express MMIO config space BAR description table) */
-struct acpi_mcfg {
- struct acpi_table_header header;
- u8 reserved[8];
-};
-
-struct acpi_mcfg_mmconfig {
- u32 base_address;
- u32 base_reserved;
- u16 pci_segment_group_number;
- u8 start_bus_number;
- u8 end_bus_number;
- u8 reserved[4];
-};
-
-/* MADT (Multiple APIC Description Table) */
-struct acpi_madt {
- struct acpi_table_header header;
- u32 lapic_addr; /* Local APIC address */
- u32 flags; /* Multiple APIC flags */
-} acpi_madt_t;
-
-enum dev_scope_type {
- SCOPE_PCI_ENDPOINT = 1,
- SCOPE_PCI_SUB = 2,
- SCOPE_IOAPIC = 3,
- SCOPE_MSI_HPET = 4
+/* FADT Preferred Power Management Profile */
+enum acpi_pm_profile {
+ ACPI_PM_UNSPECIFIED = 0,
+ ACPI_PM_DESKTOP,
+ ACPI_PM_MOBILE,
+ ACPI_PM_WORKSTATION,
+ ACPI_PM_ENTERPRISE_SERVER,
+ ACPI_PM_SOHO_SERVER,
+ ACPI_PM_APPLIANCE_PC,
+ ACPI_PM_PERFORMANCE_SERVER,
+ ACPI_PM_TABLET
};
-typedef struct dev_scope {
- u8 type;
- u8 length;
- u8 reserved[2];
- u8 enumeration;
- u8 start_bus;
- struct {
- u8 dev;
- u8 fn;
- } path[0];
-} __packed dev_scope_t;
-
-/* MADT: APIC Structure Type*/
-enum acpi_apic_types {
- LOCALAPIC = 0, /* Processor local APIC */
- IOAPIC, /* I/O APIC */
- IRQSOURCEOVERRIDE, /* Interrupt source override */
- NMITYPE, /* NMI source */
- LOCALNMITYPE, /* Local APIC NMI */
- LAPICADDRESSOVERRIDE, /* Local APIC address override */
- IOSAPIC, /* I/O SAPIC */
- LOCALSAPIC, /* Local SAPIC */
- PLATFORMIRQSOURCES, /* Platform interrupt sources */
- LOCALX2SAPIC, /* Processor local x2APIC */
- LOCALX2APICNMI, /* Local x2APIC NMI */
-};
+/* FADT flags for p_lvl2_lat and p_lvl3_lat */
+#define ACPI_FADT_C2_NOT_SUPPORTED 101
+#define ACPI_FADT_C3_NOT_SUPPORTED 1001
-/* MADT: Processor Local APIC Structure */
-struct acpi_madt_lapic {
- u8 type; /* Type (0) */
- u8 length; /* Length in bytes (8) */
- u8 processor_id; /* ACPI processor ID */
- u8 apic_id; /* Local APIC ID */
- u32 flags; /* Local APIC flags */
-};
+/* FADT Boot Architecture Flags */
+#define ACPI_FADT_LEGACY_FREE 0x00
+#define ACPI_FADT_LEGACY_DEVICES (1 << 0)
+#define ACPI_FADT_8042 (1 << 1)
+#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2)
+#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3)
+#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4)
-#define LOCAL_APIC_FLAG_ENABLED (1 << 0)
-/* bits 1-31: reserved */
-#define PCAT_COMPAT (1 << 0)
-/* bits 1-31: reserved */
+/* FADT Feature Flags */
+#define ACPI_FADT_WBINVD (1 << 0)
+#define ACPI_FADT_WBINVD_FLUSH (1 << 1)
+#define ACPI_FADT_C1_SUPPORTED (1 << 2)
+#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3)
+#define ACPI_FADT_POWER_BUTTON (1 << 4)
+#define ACPI_FADT_SLEEP_BUTTON (1 << 5)
+#define ACPI_FADT_FIXED_RTC (1 << 6)
+#define ACPI_FADT_S4_RTC_WAKE (1 << 7)
+#define ACPI_FADT_32BIT_TIMER (1 << 8)
+#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9)
+#define ACPI_FADT_RESET_REGISTER (1 << 10)
+#define ACPI_FADT_SEALED_CASE (1 << 11)
+#define ACPI_FADT_HEADLESS (1 << 12)
+#define ACPI_FADT_SLEEP_TYPE (1 << 13)
+#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14)
+#define ACPI_FADT_PLATFORM_CLOCK (1 << 15)
+#define ACPI_FADT_S4_RTC_VALID (1 << 16)
+#define ACPI_FADT_REMOTE_POWER_ON (1 << 17)
+#define ACPI_FADT_APIC_CLUSTER (1 << 18)
+#define ACPI_FADT_APIC_PHYSICAL (1 << 19)
+#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20)
+#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21)
-/* MADT: Local APIC NMI Structure */
-struct acpi_madt_lapic_nmi {
- u8 type; /* Type (4) */
- u8 length; /* Length in bytes (6) */
- u8 processor_id; /* ACPI processor ID */
- u16 flags; /* MPS INTI flags */
- u8 lint; /* Local APIC LINT# */
+enum acpi_address_space_type {
+ ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */
+ ACPI_ADDRESS_SPACE_IO, /* System I/O */
+ ACPI_ADDRESS_SPACE_PCI, /* PCI config space */
+ ACPI_ADDRESS_SPACE_EC, /* Embedded controller */
+ ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */
+ ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */
+ ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */
};
-/* MADT: I/O APIC Structure */
-struct acpi_madt_ioapic {
- u8 type; /* Type (1) */
- u8 length; /* Length in bytes (12) */
- u8 ioapic_id; /* I/O APIC ID */
- u8 reserved;
- u32 ioapic_addr; /* I/O APIC address */
- u32 gsi_base; /* Global system interrupt base */
+enum acpi_address_space_size {
+ ACPI_ACCESS_SIZE_UNDEFINED = 0,
+ ACPI_ACCESS_SIZE_BYTE_ACCESS,
+ ACPI_ACCESS_SIZE_WORD_ACCESS,
+ ACPI_ACCESS_SIZE_DWORD_ACCESS,
+ ACPI_ACCESS_SIZE_QWORD_ACCESS
};
-/* MADT: Interrupt Source Override Structure */
-struct acpi_madt_irqoverride {
- u8 type; /* Type (2) */
- u8 length; /* Length in bytes (10) */
- u8 bus; /* ISA (0) */
- u8 source; /* Bus-relative int. source (IRQ) */
- u32 gsirq; /* Global system interrupt */
- u16 flags; /* MPS INTI flags */
+struct acpi_gen_regaddr {
+ u8 space_id; /* Address space ID */
+ u8 bit_width; /* Register size in bits */
+ u8 bit_offset; /* Register bit offset */
+ u8 access_size; /* Access size */
+ u32 addrl; /* Register address, low 32 bits */
+ u32 addrh; /* Register address, high 32 bits */
};
/* FADT (Fixed ACPI Description Table) */
@@ -254,7 +140,7 @@ struct __packed acpi_fadt {
struct acpi_table_header header;
u32 firmware_ctrl;
u32 dsdt;
- u8 model;
+ u8 res1;
u8 preferred_pm_profile;
u16 sci_int;
u32 smi_cmd;
@@ -309,85 +195,121 @@ struct __packed acpi_fadt {
struct acpi_gen_regaddr x_gpe1_blk;
};
-/* Flags for p_lvl2_lat and p_lvl3_lat */
-#define ACPI_FADT_C2_NOT_SUPPORTED 101
-#define ACPI_FADT_C3_NOT_SUPPORTED 1001
+/* FACS flags */
+#define ACPI_FACS_S4BIOS_F (1 << 0)
+#define ACPI_FACS_64BIT_WAKE_F (1 << 1)
-/* FADT Feature Flags */
-#define ACPI_FADT_WBINVD (1 << 0)
-#define ACPI_FADT_WBINVD_FLUSH (1 << 1)
-#define ACPI_FADT_C1_SUPPORTED (1 << 2)
-#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3)
-#define ACPI_FADT_POWER_BUTTON (1 << 4)
-#define ACPI_FADT_SLEEP_BUTTON (1 << 5)
-#define ACPI_FADT_FIXED_RTC (1 << 6)
-#define ACPI_FADT_S4_RTC_WAKE (1 << 7)
-#define ACPI_FADT_32BIT_TIMER (1 << 8)
-#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9)
-#define ACPI_FADT_RESET_REGISTER (1 << 10)
-#define ACPI_FADT_SEALED_CASE (1 << 11)
-#define ACPI_FADT_HEADLESS (1 << 12)
-#define ACPI_FADT_SLEEP_TYPE (1 << 13)
-#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14)
-#define ACPI_FADT_PLATFORM_CLOCK (1 << 15)
-#define ACPI_FADT_S4_RTC_VALID (1 << 16)
-#define ACPI_FADT_REMOTE_POWER_ON (1 << 17)
-#define ACPI_FADT_APIC_CLUSTER (1 << 18)
-#define ACPI_FADT_APIC_PHYSICAL (1 << 19)
-/* Bits 20-31: reserved ACPI 3.0 & 4.0 */
-#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20)
-#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21)
-/* bits 22-31: reserved ACPI 5.0 */
+/* FACS (Firmware ACPI Control Structure) */
+struct acpi_facs {
+ char signature[4]; /* "FACS" */
+ u32 length; /* Length in bytes (>= 64) */
+ u32 hardware_signature; /* Hardware signature */
+ u32 firmware_waking_vector; /* Firmware waking vector */
+ u32 global_lock; /* Global lock */
+ u32 flags; /* FACS flags */
+ u32 x_firmware_waking_vector_l; /* X FW waking vector, low */
+ u32 x_firmware_waking_vector_h; /* X FW waking vector, high */
+ u8 version; /* Version 2 */
+ u8 res1[3];
+ u32 ospm_flags; /* OSPM enabled flags */
+ u8 res2[24];
+};
-/* FADT Boot Architecture Flags */
-#define ACPI_FADT_LEGACY_DEVICES (1 << 0)
-#define ACPI_FADT_8042 (1 << 1)
-#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2)
-#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3)
-#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4)
-/* No legacy devices (including 8042) */
-#define ACPI_FADT_LEGACY_FREE 0x00
+/* MADT flags */
+#define ACPI_MADT_PCAT_COMPAT (1 << 0)
-/* FADT Preferred Power Management Profile */
-#define PM_UNSPECIFIED 0
-#define PM_DESKTOP 1
-#define PM_MOBILE 2
-#define PM_WORKSTATION 3
-#define PM_ENTERPRISE_SERVER 4
-#define PM_SOHO_SERVER 5
-#define PM_APPLIANCE_PC 6
-#define PM_PERFORMANCE_SERVER 7
-#define PM_TABLET 8 /* ACPI 5.0 */
+/* MADT (Multiple APIC Description Table) */
+struct acpi_madt {
+ struct acpi_table_header header;
+ u32 lapic_addr; /* Local APIC address */
+ u32 flags; /* Multiple APIC flags */
+};
-/* FACS (Firmware ACPI Control Structure) */
-struct acpi_facs {
- char signature[4]; /* "FACS" */
- u32 length; /* Length in bytes (>= 64) */
- u32 hardware_signature; /* Hardware signature */
- u32 firmware_waking_vector; /* Firmware waking vector */
- u32 global_lock; /* Global lock */
- u32 flags; /* FACS flags */
- u32 x_firmware_waking_vector_l; /* X FW waking vector, low */
- u32 x_firmware_waking_vector_h; /* X FW waking vector, high */
- u8 version; /* ACPI 4.0: 2 */
- u8 resv[31]; /* FIXME: 4.0: ospm_flags */
+/* MADT: APIC Structure Type*/
+enum acpi_apic_types {
+ ACPI_APIC_LAPIC = 0, /* Processor local APIC */
+ ACPI_APIC_IOAPIC, /* I/O APIC */
+ ACPI_APIC_IRQ_SRC_OVERRIDE, /* Interrupt source override */
+ ACPI_APIC_NMI_SRC, /* NMI source */
+ ACPI_APIC_LAPIC_NMI, /* Local APIC NMI */
+ ACPI_APIC_LAPIC_ADDR_OVERRIDE, /* Local APIC address override */
+ ACPI_APIC_IOSAPIC, /* I/O SAPIC */
+ ACPI_APIC_LSAPIC, /* Local SAPIC */
+ ACPI_APIC_PLATFORM_IRQ_SRC, /* Platform interrupt sources */
+ ACPI_APIC_LX2APIC, /* Processor local x2APIC */
+ ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */
};
-/* FACS flags */
-#define ACPI_FACS_S4BIOS_F (1 << 0)
-#define ACPI_FACS_64BIT_WAKE_F (1 << 1)
-/* Bits 31..2: reserved */
+/* MADT: Processor Local APIC Structure */
+
+#define LOCAL_APIC_FLAG_ENABLED (1 << 0)
+
+struct acpi_madt_lapic {
+ u8 type; /* Type (0) */
+ u8 length; /* Length in bytes (8) */
+ u8 processor_id; /* ACPI processor ID */
+ u8 apic_id; /* Local APIC ID */
+ u32 flags; /* Local APIC flags */
+};
+
+/* MADT: I/O APIC Structure */
+struct acpi_madt_ioapic {
+ u8 type; /* Type (1) */
+ u8 length; /* Length in bytes (12) */
+ u8 ioapic_id; /* I/O APIC ID */
+ u8 reserved;
+ u32 ioapic_addr; /* I/O APIC address */
+ u32 gsi_base; /* Global system interrupt base */
+};
+
+/* MADT: Interrupt Source Override Structure */
+struct __packed acpi_madt_irqoverride {
+ u8 type; /* Type (2) */
+ u8 length; /* Length in bytes (10) */
+ u8 bus; /* ISA (0) */
+ u8 source; /* Bus-relative int. source (IRQ) */
+ u32 gsirq; /* Global system interrupt */
+ u16 flags; /* MPS INTI flags */
+};
+
+/* MADT: Local APIC NMI Structure */
+struct __packed acpi_madt_lapic_nmi {
+ u8 type; /* Type (4) */
+ u8 length; /* Length in bytes (6) */
+ u8 processor_id; /* ACPI processor ID */
+ u16 flags; /* MPS INTI flags */
+ u8 lint; /* Local APIC LINT# */
+};
+
+/* MCFG (PCI Express MMIO config space BAR description table) */
+struct acpi_mcfg {
+ struct acpi_table_header header;
+ u8 reserved[8];
+};
+
+struct acpi_mcfg_mmconfig {
+ u32 base_address_l;
+ u32 base_address_h;
+ u16 pci_segment_group_number;
+ u8 start_bus_number;
+ u8 end_bus_number;
+ u8 reserved[4];
+};
+
+/* PM1_CNT bit defines */
+#define PM1_CNT_SCI_EN (1 << 0)
/* These can be used by the target port */
-unsigned long acpi_create_madt_lapics(unsigned long current);
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
- u32 gsi_base);
-int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
- u8 bus, u8 source, u32 gsirq, u16 flags);
-unsigned long acpi_fill_madt(unsigned long current);
+void acpi_fill_header(struct acpi_table_header *header, char *signature);
void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
- void *dsdt);
-int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu,
- u16 flags, u8 lint);
+ void *dsdt);
+int acpi_create_madt_lapics(u32 current);
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+ u32 addr, u32 gsi_base);
+int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
+ u8 bus, u8 source, u32 gsirq, u16 flags);
+int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
+ u8 cpu, u16 flags, u8 lint);
+u32 acpi_fill_madt(u32 current);
u32 write_acpi_tables(u32 start);
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
new file mode 100644
index 0000000..ef340f3
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* SouthCluster GPIO */
+Device (GPSC)
+{
+ Name(_HID, "INT33FC")
+ Name(_CID, "INT33FC")
+ Name(_UID, 1)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+ {
+ GPIO_SC_IRQ
+ }
+ })
+
+ Method(_CRS)
+ {
+ CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+ Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
+ Return (^RBUF)
+ }
+
+ Method(_STA)
+ {
+ Return (STA_VISIBLE)
+ }
+}
+
+/* NorthCluster GPIO */
+Device (GPNC)
+{
+ Name(_HID, "INT33FC")
+ Name(_CID, "INT33FC")
+ Name(_UID, 2)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+ {
+ GPIO_NC_IRQ
+ }
+ })
+
+ Method(_CRS)
+ {
+ CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+ Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
+ Return (^RBUF)
+ }
+
+ Method(_STA)
+ {
+ Return (STA_VISIBLE)
+ }
+}
+
+/* SUS GPIO */
+Device (GPSS)
+{
+ Name(_HID, "INT33FC")
+ Name(_CID, "INT33FC")
+ Name(_UID, 3)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+ {
+ GPIO_SUS_IRQ
+ }
+ })
+
+ Method(_CRS)
+ {
+ CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+ Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
+ Return (^RBUF)
+ }
+
+ Method(_STA)
+ {
+ Return (STA_VISIBLE)
+ }
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
new file mode 100644
index 0000000..2c3585a
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronics Engineering, LLC.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This file intentionally gets included multiple times, to set pic and apic
+ * modes, so should not have guard statements added.
+ */
+
+/*
+ * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
+ * routing for the platform being compiled.
+ *
+ * This method uses #defines in irqroute.h along with the macros contained
+ * in this file to generate an IRQ routing for each PCI device in the system.
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef PCI_DEV_PIRQ_ROUTE
+#undef ACPI_DEV_IRQ
+#undef PCIE_BRIDGE_DEV
+#undef RP_IRQ_ROUTES
+#undef ROOTPORT_METHODS
+#undef ROOTPORT_IRQ_ROUTES
+#undef RP_METHOD
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+ Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## P, Package() \
+{ \
+ ACPI_DEV_IRQ(0x0000, 0, a_), \
+ ACPI_DEV_IRQ(0x0000, 1, b_), \
+ ACPI_DEV_IRQ(0x0000, 2, c_), \
+ ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+/* define as blank so ROOTPORT_METHODS only gets inserted once */
+#define ROOTPORT_METHODS(prefix_, dev_)
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+ Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## A, Package() \
+{ \
+ ACPI_DEV_IRQ(0x0000, 0, a_), \
+ ACPI_DEV_IRQ(0x0000, 1, b_), \
+ ACPI_DEV_IRQ(0x0000, 2, c_), \
+ ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+#define ROOTPORT_METHODS(prefix_, dev_) \
+ RP_METHOD(prefix_, dev_, 0) \
+ RP_METHOD(prefix_, dev_, 1) \
+ RP_METHOD(prefix_, dev_, 2) \
+ RP_METHOD(prefix_, dev_, 3) \
+ RP_METHOD(prefix_, dev_, 4) \
+ RP_METHOD(prefix_, dev_, 5) \
+ RP_METHOD(prefix_, dev_, 6) \
+ RP_METHOD(prefix_, dev_, 7)
+
+#endif /* defined(PIC_MODE) */
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+ ACPI_DEV_IRQ(dev_, 0, a_), \
+ ACPI_DEV_IRQ(dev_, 1, b_), \
+ ACPI_DEV_IRQ(dev_, 2, c_), \
+ ACPI_DEV_IRQ(dev_, 3, d_)
+
+#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
+ ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+ ROOTPORT_METHODS(prefix_, dev_)
+
+#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+ RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
+ RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
+ RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
+ RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
+ RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
+ RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
+ RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
+ RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
+
+#define RP_METHOD(prefix_, dev_, func_)\
+Device (prefix_ ## 0 ## func_) \
+{ \
+ Name(_ADR, dev_ ## 000 ## func_) \
+ Name(_PRW, Package() { 0, 0 }) \
+ Method(_PRT) { \
+ If (PICM) { \
+ Return (prefix_ ## func_ ## A) \
+ } Else { \
+ Return (prefix_ ## func_ ## P) \
+ } \
+ } \
+}
+
+/* SoC specific PIRQ route configuration */
+#include "irqroute.h"
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
new file mode 100644
index 0000000..0affa23
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
@@ -0,0 +1,493 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Scope (\)
+{
+ /* Intel Legacy Block */
+ OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+ Field(ILBS, AnyAcc, NoLock, Preserve) {
+ Offset (0x8),
+ PRTA, 8,
+ PRTB, 8,
+ PRTC, 8,
+ PRTD, 8,
+ PRTE, 8,
+ PRTF, 8,
+ PRTG, 8,
+ PRTH, 8,
+ Offset (0x88),
+ , 3,
+ UI3E, 1,
+ UI4E, 1
+ }
+}
+
+Device (LNKA)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTA)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLA, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLA, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTA */
+ ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+ Return (RTLA)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTA)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTA, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKB)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTB)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLB, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLB, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTB */
+ ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+ Return (RTLB)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTB)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTB, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKC)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTC)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLC, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLC, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTC */
+ ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+ Return (RTLC)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTC)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTC, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKD)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTD)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLD, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLD, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTD */
+ ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+ Return (RTLD)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTD)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTD, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKE)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTE)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLE, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLE, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTE */
+ ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+ Return (RTLE)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTE)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTE, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKF)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTF)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLF, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLF, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTF */
+ ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+ Return (RTLF)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTF)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTF, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKG)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTG)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLG, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLG, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTG */
+ ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+ Return (RTLG)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTG)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTG, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKH)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTH)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLH, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLH, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTH */
+ ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+ Return (RTLH)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTH)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTH, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
new file mode 100644
index 0000000..64d3820
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Name(\PICM, 0)
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local APIC/IOAPIC configuration.
+ */
+Method(\_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice */
+ Store(Arg0, PICM)
+}
+
+/* PCI interrupt routing */
+Method(_PRT) {
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include "irq_helper.h"
+ PCI_DEV_PIRQ_ROUTES
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include "irq_helper.h"
+ PCI_DEV_PIRQ_ROUTES
+ })
+ }
+
+}
+
+/* PCIe downstream ports interrupt routing */
+PCIE_BRIDGE_IRQ_ROUTES
+#undef PIC_MODE
+#include "irq_helper.h"
+PCIE_BRIDGE_IRQ_ROUTES
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
new file mode 100644
index 0000000..d746314
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(EMMC_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SD_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(MMC45_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+ PCIE_BRIDGE_DEV(RP, PCIE_DEV, A, B, C, D)
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
new file mode 100644
index 0000000..385671c
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+ Name(_ADR, 0x001f0000)
+
+ OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+ Field(LPC0, AnyAcc, NoLock, Preserve) {
+ Offset(0x08),
+ SRID, 8,
+ Offset(0x80),
+ C1EN, 1,
+ Offset(0x84)
+ }
+
+ #include "irqlinks.asl"
+
+ /* Firmware Hub */
+ Device (FWH)
+ {
+ Name(_HID, EISAID("INT0800"))
+ Name(_CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+ })
+ }
+
+ /* 8259 Interrupt Controller */
+ Device (PIC)
+ {
+ Name(_HID, EISAID("PNP0000"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+ IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+ IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+ IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+ IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+ IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+ IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+ IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+ IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+ IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+ IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+ IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+ IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+ IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+ IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+ IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+ IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+ IRQNoFlags () { 2 }
+ })
+ }
+
+ /* 8254 timer */
+ Device (TIMR)
+ {
+ Name(_HID, EISAID("PNP0100"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+ IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+ IRQNoFlags() { 0 }
+ })
+ }
+
+ /* HPET */
+ Device (HPET)
+ {
+ Name(_HID, EISAID("PNP0103"))
+ Name(_CID, 0x010CD041)
+ Name(_CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+ })
+
+ Method(_STA)
+ {
+ Return (STA_VISIBLE)
+ }
+ }
+
+ /* Internal UART */
+ Device (IURT)
+ {
+ Name(_HID, EISAID("PNP0501"))
+ Name(_UID, 1)
+
+ Method(_STA, 0, Serialized)
+ {
+ /*
+ * TODO:
+ *
+ * Need to hide the internal UART depending on whether
+ * internal UART is enabled or not so that external
+ * SuperIO UART can be exposed to system.
+ */
+ Store(1, UI3E)
+ Store(1, UI4E)
+ Store(1, C1EN)
+ Return (STA_VISIBLE)
+
+ }
+
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0, UI3E)
+ Store(0, UI4E)
+ Store(0, C1EN)
+ }
+
+ Method(_CRS, 0, Serialized)
+ {
+ Name(BUF0, ResourceTemplate()
+ {
+ IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+ IRQNoFlags() { 3 }
+ })
+
+ Name(BUF1, ResourceTemplate()
+ {
+ IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+ IRQNoFlags() { 4 }
+ })
+
+ If (LLessEqual(SRID, 0x04)) {
+ Return (BUF0)
+ } Else {
+ Return (BUF1)
+ }
+ }
+ }
+
+ /* Real Time Clock */
+ Device (RTC)
+ {
+ Name(_HID, EISAID("PNP0B00"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x70, 0x70, 1, 8)
+ /*
+ * Disable as Windows doesn't like it, and systems
+ * don't seem to use it
+ */
+ /* IRQNoFlags() { 8 } */
+ })
+ }
+
+ /* LPC device: Resource consumption */
+ Device (LDRC)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_UID, 2)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+ IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+ IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+ })
+
+ Method(_CRS, 0, NotSerialized)
+ {
+ Return (RBUF)
+ }
+ }
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
new file mode 100644
index 0000000..6bc82ec
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+ Return (Package() {0, 0})
+}
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+ #include "southcluster.asl"
+
+ /* ACPI devices */
+ #include "gpio.asl"
+}
+
+/* Chipset specific sleep states */
+#include "sleepstates.asl"
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
new file mode 100644
index 0000000..eb5ae76
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
new file mode 100644
index 0000000..34d3951
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Device (PCI0)
+{
+ Name(_HID, EISAID("PNP0A08")) /* PCIe */
+ Name(_CID, EISAID("PNP0A03")) /* PCI */
+
+ Name(_ADR, 0)
+ Name(_BBN, 0)
+
+ Name(MCRS, ResourceTemplate()
+ {
+ /* Bus Numbers */
+ WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+ /* IO Region 0 */
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+ /* PCI Config Space */
+ IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ /* IO Region 1 */
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+ /* VGA memory (0xa0000-0xbffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000, , , ASEG)
+
+ /* OPROM reserved (0xc0000-0xc3fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+ 0x00004000, , , OPR0)
+
+ /* OPROM reserved (0xc4000-0xc7fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+ 0x00004000, , , OPR1)
+
+ /* OPROM reserved (0xc8000-0xcbfff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+ 0x00004000, , , OPR2)
+
+ /* OPROM reserved (0xcc000-0xcffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+ 0x00004000, , , OPR3)
+
+ /* OPROM reserved (0xd0000-0xd3fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+ 0x00004000, , , OPR4)
+
+ /* OPROM reserved (0xd4000-0xd7fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+ 0x00004000, , , OPR5)
+
+ /* OPROM reserved (0xd8000-0xdbfff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+ 0x00004000, , , OPR6)
+
+ /* OPROM reserved (0xdc000-0xdffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+ 0x00004000, , , OPR7)
+
+ /* BIOS Extension (0xe0000-0xe3fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+ 0x00004000, , , ESG0)
+
+ /* BIOS Extension (0xe4000-0xe7fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+ 0x00004000, , , ESG1)
+
+ /* BIOS Extension (0xe8000-0xebfff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+ 0x00004000, , , ESG2)
+
+ /* BIOS Extension (0xec000-0xeffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+ 0x00004000, , , ESG3)
+
+ /* System BIOS (0xf0000-0xfffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+ 0x00010000, , , FSEG)
+
+ /* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, , , PMEM)
+
+ /* High PCI Memory Region */
+ QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, , , UMEM)
+ })
+
+ Method(_CRS, 0, Serialized)
+ {
+ /* Update PCI resource area */
+ CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+ CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+ CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+ /*
+ * Hardcode TOLM to 2GB for now as BayTrail FSP uses this value.
+ *
+ * TODO: for generic usage, read TOLM value from register, or
+ * from global NVS (not implemented by U-Boot yet).
+ */
+ Store(0x80000000, PMIN)
+ Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+ Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+ /* Update High PCI resource area */
+ CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
+ CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
+ CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
+
+ /* Set base address to 48GB and allocate 16GB for PCI space */
+ Store(0xc00000000, UMIN)
+ Store(0x400000000, ULEN)
+ Add(UMIN, Subtract(ULEN, 1), UMAX)
+
+ Return (MCRS)
+ }
+
+ /* Device Resource Consumption */
+ Device (PDRC)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_UID, 1)
+
+ Name(PDRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+ Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
+ Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
+ Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
+ Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
+ Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+ Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+ Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
+ })
+
+ /* Current Resource Settings */
+ Method(_CRS, 0, Serialized)
+ {
+ Return (PDRS)
+ }
+ }
+
+ Method(_OSC, 4)
+ {
+ /* Check for proper GUID */
+ If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ /* Let OS control everything */
+ Return (Arg3)
+ } Else {
+ /* Unrecognized UUID */
+ CreateDWordField(Arg3, 0, CDW1)
+ Or(CDW1, 4, CDW1)
+ Return (Arg3)
+ }
+ }
+
+ /* LPC Bridge 0:1f.0 */
+ #include "lpc.asl"
+
+ /* USB EHCI 0:1d.0 */
+ #include "usb.asl"
+
+ /* USB XHCI 0:14.0 */
+ #include "xhci.asl"
+
+ /* IRQ routing for each PCI device */
+ #include "irqroute.asl"
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/usb.asl b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
new file mode 100644
index 0000000..311f471
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* EHCI Controller 0:1d.0 */
+
+Device (EHC1)
+{
+ Name(_ADR, 0x001d0000)
+
+ /* Power Resources for Wake */
+ Name(_PRW, Package() { 13, 4 })
+
+ /* Highest D state in S3 state */
+ Name(_S3D, 2)
+
+ /* Highest D state in S4 state */
+ Name(_S4D, 2)
+
+ Device (HUB7)
+ {
+ Name(_ADR, 0x00000000)
+
+ Device(PRT1) { Name(_ADR, 1) } /* USB Port 0 */
+ Device(PRT2) { Name(_ADR, 2) } /* USB Port 1 */
+ Device(PRT3) { Name(_ADR, 3) } /* USB Port 2 */
+ Device(PRT4) { Name(_ADR, 4) } /* USB Port 3 */
+ }
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
new file mode 100644
index 0000000..a5a4404
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+ Name(_ADR, 0x00140000)
+
+ /* Power Resources for Wake */
+ Name(_PRW, Package() { 13, 3 })
+
+ /* Highest D state in S3 state */
+ Name(_S3D, 3)
+
+ Device (RHUB)
+ {
+ Name(_ADR, 0x00000000)
+
+ Device (PRT1) { Name(_ADR, 1) } /* USB Port 0 */
+ Device (PRT2) { Name(_ADR, 2) } /* USB Port 1 */
+ Device (PRT3) { Name(_ADR, 3) } /* USB Port 2 */
+ Device (PRT4) { Name(_ADR, 4) } /* USB Port 3 */
+ }
+}
diff --git a/arch/x86/include/asm/arch-baytrail/device.h b/arch/x86/include/asm/arch-baytrail/device.h
new file mode 100644
index 0000000..798d35b
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/device.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DEVICE_H_
+#define _DEVICE_H_
+
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
+
+/* SoC transaction router */
+#define SOC_DEV 0x00
+
+/* Graphics and Display */
+#define GFX_DEV 0x02
+
+/* MIPI */
+#define MIPI_DEV 0x03
+
+/* EMMC Port */
+#define EMMC_DEV 0x10
+
+/* SDIO Port */
+#define SDIO_DEV 0x11
+
+/* SD Port */
+#define SD_DEV 0x12
+
+/* SATA */
+#define SATA_DEV 0x13
+
+/* xHCI */
+#define XHCI_DEV 0x14
+
+/* LPE Audio */
+#define LPE_DEV 0x15
+
+/* OTG */
+#define OTG_DEV 0x16
+
+/* MMC45 Port */
+#define MMC45_DEV 0x17
+
+/* Serial IO 1 */
+#define SIO1_DEV 0x18
+
+/* Trusted Execution Engine */
+#define TXE_DEV 0x1a
+
+/* HD Audio */
+#define HDA_DEV 0x1b
+
+/* PCIe Ports */
+#define PCIE_DEV 0x1c
+
+/* EHCI */
+#define EHCI_DEV 0x1d
+
+/* Serial IO 2 */
+#define SIO2_DEV 0x1e
+
+/* Platform Controller Unit */
+#define PCU_DEV 0x1f
+
+#endif /* _DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/iomap.h b/arch/x86/include/asm/arch-baytrail/iomap.h
new file mode 100644
index 0000000..62a9105
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/iomap.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IOMAP_H_
+#define _BAYTRAIL_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE 0x10000000
+
+/* Temporary Base Address */
+#define TEMP_BASE_ADDRESS 0xfd000000
+
+/* Transactions in this range will abort */
+#define ABORT_BASE_ADDRESS 0xfeb00000
+#define ABORT_BASE_SIZE 0x00100000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS 0xfed00000
+#define HPET_BASE_SIZE 0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS 0xfed01000
+#define SPI_BASE_SIZE 0x400
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS 0xfed03000
+#define PMC_BASE_SIZE 0x400
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS 0xfed05000
+#define PUNIT_BASE_SIZE 0x800
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS 0xfed08000
+#define ILB_BASE_SIZE 0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS 0xfed0c000
+#define IO_BASE_OFFSET_GPSCORE 0x0000
+#define IO_BASE_OFFSET_GPNCORE 0x1000
+#define IO_BASE_OFFSET_GPSSUS 0x2000
+#define IO_BASE_SIZE 0x4000
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS 0xfed1c000
+#define RCBA_BASE_SIZE 0x400
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS 0xfef00000
+#define MPHY_BASE_SIZE 0x100000
+
+/* IO Port bases */
+#define ACPI_BASE_ADDRESS 0x0400
+#define ACPI_BASE_SIZE 0x80
+
+#define GPIO_BASE_ADDRESS 0x0500
+#define GPIO_BASE_SIZE 0x100
+
+#define SMBUS_BASE_ADDRESS 0xefa0
+
+#endif /* _BAYTRAIL_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/irq.h b/arch/x86/include/asm/arch-baytrail/irq.h
new file mode 100644
index 0000000..cd66f83
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/irq.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IRQ_H_
+#define _BAYTRAIL_IRQ_H_
+
+#define PIRQA_APIC_IRQ 16
+#define PIRQB_APIC_IRQ 17
+#define PIRQC_APIC_IRQ 18
+#define PIRQD_APIC_IRQ 19
+#define PIRQE_APIC_IRQ 20
+#define PIRQF_APIC_IRQ 21
+#define PIRQG_APIC_IRQ 22
+#define PIRQH_APIC_IRQ 23
+
+/* The below IRQs are for when devices are in ACPI mode */
+#define LPE_DMA0_IRQ 24
+#define LPE_DMA1_IRQ 25
+#define LPE_SSP0_IRQ 26
+#define LPE_SSP1_IRQ 27
+#define LPE_SSP2_IRQ 28
+#define LPE_IPC2HOST_IRQ 29
+#define LPSS_I2C1_IRQ 32
+#define LPSS_I2C2_IRQ 33
+#define LPSS_I2C3_IRQ 34
+#define LPSS_I2C4_IRQ 35
+#define LPSS_I2C5_IRQ 36
+#define LPSS_I2C6_IRQ 37
+#define LPSS_I2C7_IRQ 38
+#define LPSS_HSUART1_IRQ 39
+#define LPSS_HSUART2_IRQ 40
+#define LPSS_SPI_IRQ 41
+#define LPSS_DMA1_IRQ 42
+#define LPSS_DMA2_IRQ 43
+#define SCC_EMMC_IRQ 44
+#define SCC_SDIO_IRQ 46
+#define SCC_SD_IRQ 47
+#define GPIO_NC_IRQ 48
+#define GPIO_SC_IRQ 49
+#define GPIO_SUS_IRQ 50
+/* GPIO direct / dedicated IRQs */
+#define GPIO_S0_DED_IRQ_0 51
+#define GPIO_S0_DED_IRQ_1 52
+#define GPIO_S0_DED_IRQ_2 53
+#define GPIO_S0_DED_IRQ_3 54
+#define GPIO_S0_DED_IRQ_4 55
+#define GPIO_S0_DED_IRQ_5 56
+#define GPIO_S0_DED_IRQ_6 57
+#define GPIO_S0_DED_IRQ_7 58
+#define GPIO_S0_DED_IRQ_8 59
+#define GPIO_S0_DED_IRQ_9 60
+#define GPIO_S0_DED_IRQ_10 61
+#define GPIO_S0_DED_IRQ_11 62
+#define GPIO_S0_DED_IRQ_12 63
+#define GPIO_S0_DED_IRQ_13 64
+#define GPIO_S0_DED_IRQ_14 65
+#define GPIO_S0_DED_IRQ_15 66
+#define GPIO_S5_DED_IRQ_0 67
+#define GPIO_S5_DED_IRQ_1 68
+#define GPIO_S5_DED_IRQ_2 69
+#define GPIO_S5_DED_IRQ_3 70
+#define GPIO_S5_DED_IRQ_4 71
+#define GPIO_S5_DED_IRQ_5 72
+#define GPIO_S5_DED_IRQ_6 73
+#define GPIO_S5_DED_IRQ_7 74
+#define GPIO_S5_DED_IRQ_8 75
+#define GPIO_S5_DED_IRQ_9 76
+#define GPIO_S5_DED_IRQ_10 77
+#define GPIO_S5_DED_IRQ_11 78
+#define GPIO_S5_DED_IRQ_12 79
+#define GPIO_S5_DED_IRQ_13 80
+#define GPIO_S5_DED_IRQ_14 81
+#define GPIO_S5_DED_IRQ_15 82
+/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
+#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot
+#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot
+#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot)
+#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot)
+
+#endif /* _BAYTRAIL_IRQ_H_ */
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
index 15ccf9b..e036f74 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -295,6 +295,25 @@ struct cbmem_entry {
#define CBMEM_ID_NONE 0x00000000
/**
+ * high_table_reserve() - reserve configuration table in high memory
+ *
+ * This reserves configuration table in high memory.
+ *
+ * @return: always 0
+ */
+int high_table_reserve(void);
+
+/**
+ * high_table_malloc() - allocate configuration table in high memory
+ *
+ * This allocates configuration table in high memory.
+ *
+ * @bytes: size of configuration table to be allocated
+ * @return: pointer to configuration table in high memory
+ */
+void *high_table_malloc(size_t bytes);
+
+/**
* write_coreboot_table() - write coreboot table
*
* This writes coreboot table at a given address.
diff --git a/arch/x86/include/asm/fw_cfg.h b/arch/x86/include/asm/fw_cfg.h
deleted file mode 100644
index e9450c6..0000000
--- a/arch/x86/include/asm/fw_cfg.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __FW_CFG__
-#define __FW_CFG__
-
-#define FW_CONTROL_PORT 0x510
-#define FW_DATA_PORT 0x511
-#define FW_DMA_PORT_LOW 0x514
-#define FW_DMA_PORT_HIGH 0x518
-
-#include <linux/list.h>
-
-enum qemu_fwcfg_items {
- FW_CFG_SIGNATURE = 0x00,
- FW_CFG_ID = 0x01,
- FW_CFG_UUID = 0x02,
- FW_CFG_RAM_SIZE = 0x03,
- FW_CFG_NOGRAPHIC = 0x04,
- FW_CFG_NB_CPUS = 0x05,
- FW_CFG_MACHINE_ID = 0x06,
- FW_CFG_KERNEL_ADDR = 0x07,
- FW_CFG_KERNEL_SIZE = 0x08,
- FW_CFG_KERNEL_CMDLINE = 0x09,
- FW_CFG_INITRD_ADDR = 0x0a,
- FW_CFG_INITRD_SIZE = 0x0b,
- FW_CFG_BOOT_DEVICE = 0x0c,
- FW_CFG_NUMA = 0x0d,
- FW_CFG_BOOT_MENU = 0x0e,
- FW_CFG_MAX_CPUS = 0x0f,
- FW_CFG_KERNEL_ENTRY = 0x10,
- FW_CFG_KERNEL_DATA = 0x11,
- FW_CFG_INITRD_DATA = 0x12,
- FW_CFG_CMDLINE_ADDR = 0x13,
- FW_CFG_CMDLINE_SIZE = 0x14,
- FW_CFG_CMDLINE_DATA = 0x15,
- FW_CFG_SETUP_ADDR = 0x16,
- FW_CFG_SETUP_SIZE = 0x17,
- FW_CFG_SETUP_DATA = 0x18,
- FW_CFG_FILE_DIR = 0x19,
- FW_CFG_FILE_FIRST = 0x20,
- FW_CFG_WRITE_CHANNEL = 0x4000,
- FW_CFG_ARCH_LOCAL = 0x8000,
- FW_CFG_INVALID = 0xffff,
-};
-
-enum {
- BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1,
- BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2,
- BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3,
-};
-
-enum {
- BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1,
- BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2,
-};
-
-#define FW_CFG_FILE_SLOTS 0x10
-#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS)
-#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
-
-#define FW_CFG_MAX_FILE_PATH 56
-#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
-
-#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U')
-
-#define FW_CFG_DMA_ERROR (1 << 0)
-#define FW_CFG_DMA_READ (1 << 1)
-#define FW_CFG_DMA_SKIP (1 << 2)
-#define FW_CFG_DMA_SELECT (1 << 3)
-
-#define FW_CFG_DMA_ENABLED (1 << 1)
-
-struct fw_cfg_file {
- __be32 size;
- __be16 select;
- __be16 reserved;
- char name[FW_CFG_MAX_FILE_PATH];
-};
-
-struct fw_file {
- struct fw_cfg_file cfg; /* firmware file information */
- unsigned long addr; /* firmware file in-memory address */
- struct list_head list; /* list node to link to fw_list */
-};
-
-struct fw_cfg_dma_access {
- __be32 control;
- __be32 length;
- __be64 address;
-};
-
-struct bios_linker_entry {
- __le32 command;
- union {
- /*
- * COMMAND_ALLOCATE - allocate a table from @alloc.file
- * subject to @alloc.align alignment (must be power of 2)
- * and @alloc.zone (can be HIGH or FSEG) requirements.
- *
- * Must appear exactly once for each file, and before
- * this file is referenced by any other command.
- */
- struct {
- char file[BIOS_LINKER_LOADER_FILESZ];
- __le32 align;
- uint8_t zone;
- } alloc;
-
- /*
- * COMMAND_ADD_POINTER - patch the table (originating from
- * @dest_file) at @pointer.offset, by adding a pointer to the
- * table originating from @src_file. 1,2,4 or 8 byte unsigned
- * addition is used depending on @pointer.size.
- */
- struct {
- char dest_file[BIOS_LINKER_LOADER_FILESZ];
- char src_file[BIOS_LINKER_LOADER_FILESZ];
- __le32 offset;
- uint8_t size;
- } pointer;
-
- /*
- * COMMAND_ADD_CHECKSUM - calculate checksum of the range
- * specified by @cksum_start and @cksum_length fields,
- * and then add the value at @cksum.offset.
- * Checksum simply sums -X for each byte X in the range
- * using 8-bit math.
- */
- struct {
- char file[BIOS_LINKER_LOADER_FILESZ];
- __le32 offset;
- __le32 start;
- __le32 length;
- } cksum;
-
- /* padding */
- char pad[124];
- };
-} __packed;
-
-/**
- * Initialize QEMU fw_cfg interface
- */
-void qemu_fwcfg_init(void);
-
-/**
- * Get system cpu number
- *
- * @return: cpu number in system
- */
-int qemu_fwcfg_online_cpus(void);
-
-#endif
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 3bc2ac2..7434f77 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -93,6 +93,10 @@ struct arch_global_data {
char *mrc_output;
unsigned int mrc_output_len;
ulong table; /* Table pointer from previous loader */
+#ifdef CONFIG_SEABIOS
+ u32 high_table_ptr;
+ u32 high_table_limit;
+#endif
};
#endif
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 5b9e673..ddb529e 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -34,6 +34,8 @@ enum pirq_config {
* IRQ N is available to be routed
* @lb_bdf: irq router's PCI bus/device/function number encoding
* @ibase: IBASE register block base address
+ * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset)
+ * @actl_addr: ACTL register offset
*/
struct irq_router {
int config;
@@ -41,6 +43,8 @@ struct irq_router {
u16 irq_mask;
u32 bdf;
u32 ibase;
+ bool actl_8bit;
+ int actl_addr;
};
struct pirq_routing {