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-rw-r--r--arch/x86/include/asm/arch-ivybridge/sandybridge.h3
-rw-r--r--arch/x86/include/asm/intel_regs.h15
2 files changed, 15 insertions, 3 deletions
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index d137d67..59b05cc 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -38,7 +38,6 @@
#define IED_SIZE 0x400000
/* Northbridge BARs */
-#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#define DEFAULT_RCBABASE 0xfed1c000
@@ -97,8 +96,6 @@
/*
* MCHBAR
*/
-#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg))
-
#define SSKPD 0x5d14 /* 16bit (scratchpad) */
#define BIOS_RESET_CPL 0x5da8 /* 8bit */
diff --git a/arch/x86/include/asm/intel_regs.h b/arch/x86/include/asm/intel_regs.h
new file mode 100644
index 0000000..9725738
--- /dev/null
+++ b/arch/x86/include/asm/intel_regs.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_INTEL_REGS_H
+#define __ASM_INTEL_REGS_H
+
+/* Access the memory-controller hub */
+#define MCH_BASE_ADDRESS 0xfed10000
+#define MCH_BASE_SIZE 0x8000
+#define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg))
+
+#endif