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-rw-r--r--arch/x86/cpu/baytrail/fsp_configs.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
index 9810921..d49b8d2 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -125,13 +125,19 @@ const struct pch_azalia_config azalia_config = {
* If the device tree does not specify an integer setting, use the default
* provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file.
*/
-void update_fsp_configs(struct fsp_config_data *config)
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf)
{
struct upd_region *fsp_upd = &config->fsp_upd;
struct memory_down_data *mem;
const void *blob = gd->fdt_blob;
int node;
+ /* Initialize runtime buffer for fsp_init() */
+ rt_buf->common.stack_top = config->common.stack_top - 32;
+ rt_buf->common.boot_mode = config->common.boot_mode;
+ rt_buf->common.upd_data = &config->fsp_upd;
+
fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);