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-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile3
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c22
-rw-r--r--arch/powerpc/cpu/mpc85xx/ddr-gen3.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/portals.c36
-rw-r--r--arch/powerpc/cpu/mpc85xx/release.S14
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c12
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S102
-rw-r--r--arch/powerpc/cpu/mpc85xx/t4240_serdes.c150
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c1
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/main.c26
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h36
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h66
-rw-r--r--arch/powerpc/include/asm/processor.h11
14 files changed, 376 insertions, 107 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 6776c85..6e5aec2 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -83,6 +83,7 @@ COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_T4160) += ddr-gen3.o
COBJS-$(CONFIG_PPC_B4420) += ddr-gen3.o
COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
@@ -102,6 +103,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
+COBJS-$(CONFIG_PPC_T4160) += t4240_ids.o
COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o
COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
@@ -137,6 +139,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
+COBJS-$(CONFIG_PPC_T4160) += t4240_serdes.o
COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 53713e3..48e6a05 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -637,6 +637,28 @@ skip_l2:
}
#endif
+#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
+ ccsr_usb_phy_t *usb_phy =
+ (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+ setbits_be32(&usb_phy->pllprg[1],
+ CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
+ CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
+ CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
+ CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+ setbits_be32(&usb_phy->port1.ctrl,
+ CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+ setbits_be32(&usb_phy->port1.drvvbuscfg,
+ CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+ setbits_be32(&usb_phy->port1.pwrfltcfg,
+ CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+ setbits_be32(&usb_phy->port2.ctrl,
+ CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+ setbits_be32(&usb_phy->port2.drvvbuscfg,
+ CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+ setbits_be32(&usb_phy->port2.pwrfltcfg,
+ CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+#endif
+
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index ef0dd1d..c5b4720 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -142,7 +142,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
}
}
#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
- out_be32(&ddr->debug[28], 0x00003000);
+ out_be32(&ddr->debug[28], 0x30003000);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 01dcdf6..93eca76 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -164,7 +164,7 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
}
cfg >>= sd_prctl_shift;
- printf("Using SERDES%d Protocol: 0x%x\n", sd + 1, cfg);
+ printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
if (!is_serdes_prtcl_valid(sd, cfg))
printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index d529095..672edde 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -128,24 +128,32 @@ static int fdt_qportal(void *blob, int off, int id, char *name,
childoff = fdt_subnode_offset(blob, off, name);
if (create) {
- if (childoff <= 0)
- childoff = fdt_add_subnode(blob, off, name);
+ char handle[64], *p;
- if (childoff > 0) {
- char handle[64], *p;
+ strncpy(handle, name, sizeof(handle));
+ p = strchr(handle, '@');
+ if (!strncmp(name, "fman", 4)) {
+ *p = *(p + 1);
+ p++;
+ }
+ *p = '\0';
- strncpy(handle, name, sizeof(handle));
- p = strchr(handle, '@');
- if (!strncmp(name, "fman", 4)) {
- *p = *(p + 1);
- p++;
- }
- *p = '\0';
+ dev_off = fdt_path_offset(blob, handle);
+ /* skip this node if alias is not found */
+ if (dev_off == -FDT_ERR_BADPATH)
+ return 0;
+ if (dev_off < 0)
+ return dev_off;
- dev_off = fdt_path_offset(blob, handle);
- if (dev_off < 0)
- return dev_off;
+ if (childoff <= 0)
+ childoff = fdt_add_subnode(blob, off, name);
+ /* need to update the dev_off after adding a subnode */
+ dev_off = fdt_path_offset(blob, handle);
+ if (dev_off < 0)
+ return dev_off;
+
+ if (childoff > 0) {
dev_handle = fdt_get_phandle(blob, dev_off);
if (dev_handle <= 0) {
dev_handle = fdt_alloc_phandle(blob);
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 5c4b1e3..467ea10 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -69,9 +69,9 @@ __secondary_start_page:
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
- mfspr r3,977
+ mfspr r3,SPRN_HDBCR1
oris r3,r3,0x0100
- mtspr 977,r3
+ mtspr SPRN_HDBCR1,r3
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
@@ -93,10 +93,10 @@ __secondary_start_page:
1: /* Erratum says set bits 55:60 to 001001 */
msync
isync
- mfspr r3,976
+ mfspr r3,SPRN_HDBCR0
li r4,0x48
rlwimi r3,r4,0,0x1f8
- mtspr 976,r3
+ mtspr SPRN_HDBCR0,r3
isync
2:
#endif
@@ -159,9 +159,9 @@ __secondary_start_page:
* we cannot access it yet before setting up a new TLB
*/
mfspr r0,SPRN_PIR
-#if defined(CONFIG_E6500)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
/*
- * PIR definition for E6500
+ * PIR definition for Chassis 2
* 0-17 Reserved (logic 0s)
* 8-19 CHIP_ID, 2'b00 - SoC 1
* all others - reserved
@@ -187,7 +187,7 @@ __secondary_start_page:
slwi r8,r4,6 /* spin table is padded to 64 byte */
add r10,r3,r8
-#ifdef CONFIG_E6500
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
mfspr r0,SPRN_PIR
/*
* core 0 thread 0: pir reset value 0x00, new pir 0
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 297f2ed..f00b1ab 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -132,10 +132,15 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqProcessor[cpu] =
freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
}
+#ifdef CONFIG_PPC_B4860
+#define FM1_CLK_SEL 0xe0000000
+#define FM1_CLK_SHIFT 29
+#else
#define PME_CLK_SEL 0xe0000000
#define PME_CLK_SHIFT 29
#define FM1_CLK_SEL 0x1c000000
#define FM1_CLK_SHIFT 26
+#endif
rcw_tmp = in_be32(&gur->rcwsr[7]);
#ifdef CONFIG_SYS_DPAA_PME
@@ -185,6 +190,9 @@ void get_sys_info (sys_info_t * sysInfo)
case 4:
sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
break;
+ case 5:
+ sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
+ break;
case 6:
sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
break;
@@ -285,6 +293,10 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
+#endif
+
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#else /* CONFIG_FSL_CORENET */
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 3f76ee6..5542d0a 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -116,10 +116,10 @@ _start_e500:
/* Erratum says set bits 55:60 to 001001 */
msync
isync
- mfspr r3,976
+ mfspr r3,SPRN_HDBCR0
li r4,0x48
rlwimi r3,r4,0,0x1f8
- mtspr 976,r3
+ mtspr SPRN_HDBCR0,r3
isync
2:
#endif
@@ -173,52 +173,6 @@ l2_disabled:
mfspr r1,DBSR
mtspr DBSR,r1 /* Clear all valid bits */
- /*
- * Enable L1 Caches early
- *
- */
-
-#ifdef CONFIG_SYS_CACHE_STASHING
- /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
- li r2,(32 + 0)
- mtspr L1CSR2,r2
-#endif
-
- /* Enable/invalidate the I-Cache */
- lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
- ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
- mtspr SPRN_L1CSR1,r2
-1:
- mfspr r3,SPRN_L1CSR1
- and. r1,r3,r2
- bne 1b
-
- lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
- ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
- mtspr SPRN_L1CSR1,r3
- isync
-2:
- mfspr r3,SPRN_L1CSR1
- andi. r1,r3,L1CSR1_ICE@l
- beq 2b
-
- /* Enable/invalidate the D-Cache */
- lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
- ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
- mtspr SPRN_L1CSR0,r2
-1:
- mfspr r3,SPRN_L1CSR0
- and. r1,r3,r2
- bne 1b
-
- lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
- ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
- mtspr SPRN_L1CSR0,r3
- isync
-2:
- mfspr r3,SPRN_L1CSR0
- andi. r1,r3,L1CSR0_DCE@l
- beq 2b
.macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
@@ -372,9 +326,9 @@ l2_disabled:
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
- mfspr r3,977
+ mfspr r3,SPRN_HDBCR1
oris r3,r3,0x0100
- mtspr 977,r3
+ mtspr SPRN_HDBCR1,r3
#endif
/* Enable Branch Prediction */
@@ -782,11 +736,57 @@ enable_l2_cluster_l2:
bne 1b
lis r4, L2CSR0_L2E@h
sync
- stw r4, 0(r3) /* eanble L2 */
+ stw r4, 0(r3) /* enable L2 */
delete_ccsr_l2_tlb:
delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
#endif
+ /*
+ * Enable the L1. On e6500, this has to be done
+ * after the L2 is up.
+ */
+
+#ifdef CONFIG_SYS_CACHE_STASHING
+ /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+ li r2,(32 + 0)
+ mtspr L1CSR2,r2
+#endif
+
+ /* Enable/invalidate the I-Cache */
+ lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
+ ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
+ mtspr SPRN_L1CSR1,r2
+1:
+ mfspr r3,SPRN_L1CSR1
+ and. r1,r3,r2
+ bne 1b
+
+ lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
+ ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
+ mtspr SPRN_L1CSR1,r3
+ isync
+2:
+ mfspr r3,SPRN_L1CSR1
+ andi. r1,r3,L1CSR1_ICE@l
+ beq 2b
+
+ /* Enable/invalidate the D-Cache */
+ lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
+ ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
+ mtspr SPRN_L1CSR0,r2
+1:
+ mfspr r3,SPRN_L1CSR0
+ and. r1,r3,r2
+ bne 1b
+
+ lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
+ ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
+ mtspr SPRN_L1CSR0,r3
+ isync
+2:
+ mfspr r3,SPRN_L1CSR0
+ andi. r1,r3,L1CSR0_DCE@l
+ beq 2b
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
#define LAW_SIZE_1M 0x13
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 102defa..c001780 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -31,7 +31,8 @@ struct serdes_config {
u8 lanes[SRDS_MAX_LANES];
};
-static struct serdes_config serdes1_cfg_tbl[] = {
+#ifdef CONFIG_PPC_T4240
+static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
XAUI_FM1_MAC9, XAUI_FM1_MAC9,
@@ -66,7 +67,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
NONE, NONE, QSGMII_FM1_A, NONE}},
{}
};
-static struct serdes_config serdes2_cfg_tbl[] = {
+static const struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
{1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
@@ -150,7 +151,7 @@ static struct serdes_config serdes2_cfg_tbl[] = {
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
{}
};
-static struct serdes_config serdes3_cfg_tbl[] = {
+static const struct serdes_config serdes3_cfg_tbl[] = {
/* SerDes 3 */
{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
@@ -174,20 +175,151 @@ static struct serdes_config serdes3_cfg_tbl[] = {
SRIO1, SRIO1, SRIO1, SRIO1}},
{}
};
-static struct serdes_config serdes4_cfg_tbl[] = {
+static const struct serdes_config serdes4_cfg_tbl[] = {
/* SerDes 4 */
{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
- {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA1}},
- {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA1}},
+ {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
+ {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
-static struct serdes_config *serdes_cfg_tbl[] = {
+#elif defined(CONFIG_PPC_T4160)
+static const struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
+ {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+ HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+ {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+ HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+ {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+ {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+ {38, {NONE, NONE, QSGMII_FM1_B, NONE,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
+ {}
+};
+static const struct serdes_config serdes2_cfg_tbl[] = {
+ /* SerDes 2 */
+ {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ NONE, NONE} },
+ {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {38, {NONE, NONE, QSGMII_FM2_B, NONE,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
+ {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
+ {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
+ {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
+ {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ NONE, NONE, NONE, NONE} },
+ {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, NONE, NONE} },
+ {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, NONE, NONE} },
+ {56, {NONE, XFI_FM1_MAC10,
+ XFI_FM2_MAC10, NONE,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {57, {NONE, XFI_FM1_MAC10,
+ XFI_FM2_MAC10, NONE,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ NONE, NONE} },
+ {}
+};
+static const struct serdes_config serdes3_cfg_tbl[] = {
+ /* SerDes 3 */
+ {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+ {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+ {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
+ {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+ {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+ {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
+ {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
+ {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
+ {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
+ {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
+ {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ NONE, NONE, NONE, NONE} },
+ {}
+};
+static const struct serdes_config serdes4_cfg_tbl[] = {
+ /* SerDes 4 */
+ {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
+ {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
+ {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
+ {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
+ {}
+}
+;
+#else
+#error "Need to define SerDes protocol"
+#endif
+static const struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
serdes2_cfg_tbl,
serdes3_cfg_tbl,
@@ -196,7 +328,7 @@ static struct serdes_config *serdes_cfg_tbl[] = {
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
{
- struct serdes_config *ptr;
+ const struct serdes_config *ptr;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
@@ -213,7 +345,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
{
int i;
- struct serdes_config *ptr;
+ const struct serdes_config *ptr;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 39525fb..0087cd0 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -77,6 +77,7 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(P5040, P5040, 4),
CPU_TYPE_ENTRY(T4240, T4240, 0),
CPU_TYPE_ENTRY(T4120, T4120, 0),
+ CPU_TYPE_ENTRY(T4160, T4160, 0),
CPU_TYPE_ENTRY(B4860, B4860, 0),
CPU_TYPE_ENTRY(G4860, G4860, 0),
CPU_TYPE_ENTRY(G4060, G4060, 0),
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 5311a26..7a8636d 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -186,7 +186,7 @@ const char * step_to_string(unsigned int step) {
return step_string_tbl[s];
}
-unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
+static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
unsigned int dbw_cap_adj[])
{
int i, j;
@@ -354,6 +354,11 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
return total_mem;
}
+/* Use weak function to allow board file to override the address assignment */
+__attribute__((weak, alias("__step_assign_addresses")))
+unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
+ unsigned int dbw_cap_adj[]);
+
unsigned long long
fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
unsigned int size_only)
@@ -541,14 +546,17 @@ phys_size_t fsl_ddr_sdram(void)
total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
/* setup 3-way interleaving before enabling DDRC */
- switch (info.memctl_opts[0].memctl_interleaving_mode) {
- case FSL_DDR_3WAY_1KB_INTERLEAVING:
- case FSL_DDR_3WAY_4KB_INTERLEAVING:
- case FSL_DDR_3WAY_8KB_INTERLEAVING:
- fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode);
- break;
- default:
- break;
+ if (info.memctl_opts[0].memctl_interleaving) {
+ switch (info.memctl_opts[0].memctl_interleaving_mode) {
+ case FSL_DDR_3WAY_1KB_INTERLEAVING:
+ case FSL_DDR_3WAY_4KB_INTERLEAVING:
+ case FSL_DDR_3WAY_8KB_INTERLEAVING:
+ fsl_ddr_set_intl3r(
+ info.memctl_opts[0].memctl_interleaving_mode);
+ break;
+ default:
+ break;
+ }
}
/* Program configuration registers. */
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 7267611..7571941 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -537,13 +537,45 @@
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A004468
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+
+#elif defined(CONFIG_PPC_T4160)
+#define CONFIG_SYS_PPC64 /* 64-bit core */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_MAX_CPUS 8
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SRDS_3
+#define CONFIG_SYS_FSL_SRDS_4
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 2
+#define CONFIG_SYS_NUM_FM1_DTSEC 7
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_SYS_NUM_FM2_DTSEC 7
+#define CONFIG_SYS_NUM_FM2_10GEC 1
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_A004468
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_PCI_VER_3_X
#elif defined(CONFIG_PPC_B4420)
#define CONFIG_SYS_PPC64 /* 64-bit core */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index baaa9fe..28fe1d2 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1676,18 +1676,17 @@ typedef struct cpc_corenet {
/* Global Utilities Block */
#ifdef CONFIG_FSL_CORENET
typedef struct ccsr_gur {
- u32 porsr1; /* POR status */
- u8 res1[28];
+ u32 porsr1; /* POR status 1 */
+ u32 porsr2; /* POR status 2 */
+ u8 res_008[0x20-0x8];
u32 gpporcr1; /* General-purpose POR configuration */
- u8 res2[12];
- u32 gpiocr; /* GPIO control */
- u8 res3[12];
- u32 gpoutdr; /* General-purpose output data */
- u8 res4[12];
- u32 gpindr; /* General-purpose input data */
- u8 res5[12];
- u32 alt_pmuxcr; /* Alt function signal multiplex control */
- u8 res6[12];
+ u32 gpporcr2; /* General-purpose POR configuration 2 */
+ u32 dcfg_fusesr; /* Fuse status register */
+#define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
+#define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
+#define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
+#define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
+ u8 res_02c[0x70-0x2c];
u32 devdisr; /* Device disable control */
u32 devdisr2; /* Device disable control 2 */
u32 devdisr3; /* Device disable control 3 */
@@ -1831,7 +1830,7 @@ typedef struct ccsr_gur {
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
-#if defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
@@ -1899,7 +1898,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
@@ -2829,12 +2828,53 @@ typedef struct ccsr_pme {
u8 res4[0x400];
} ccsr_pme_t;
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+struct ccsr_usb_port_ctrl {
+ u32 ctrl;
+ u32 drvvbuscfg;
+ u32 pwrfltcfg;
+ u32 sts;
+ u8 res_14[0xc];
+ u32 bistcfg;
+ u32 biststs;
+ u32 abistcfg;
+ u32 abiststs;
+ u8 res_30[0x10];
+ u32 xcvrprg;
+ u32 anaprg;
+ u32 anadrv;
+ u32 anasts;
+};
+
+typedef struct ccsr_usb_phy {
+ u32 id;
+ struct ccsr_usb_port_ctrl port1;
+ u8 res_50[0xc];
+ u32 tvr;
+ u32 pllprg[4];
+ u8 res_70[0x4];
+ u32 anaccfg;
+ u32 dbg;
+ u8 res_7c[0x4];
+ struct ccsr_usb_port_ctrl port2;
+ u8 res_dc[0x334];
+} ccsr_usb_phy_t;
+
+#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
+#else
typedef struct ccsr_usb_phy {
u8 res0[0x18];
u32 usb_enable_override;
u8 res[0xe4];
} ccsr_usb_phy_t;
#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#endif
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
struct ccsr_raide {
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 8c91f08..5c0c438 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -575,6 +575,16 @@
#define SPRN_MSSSR0 0x3f7
#endif
+#define SPRN_HDBCR0 0x3d0
+#define SPRN_HDBCR1 0x3d1
+#define SPRN_HDBCR2 0x3d2
+#define SPRN_HDBCR3 0x3d3
+#define SPRN_HDBCR4 0x3d4
+#define SPRN_HDBCR5 0x3d5
+#define SPRN_HDBCR6 0x3d6
+#define SPRN_HDBCR7 0x277
+#define SPRN_HDBCR8 0x278
+
/* Short-hand versions for a number of the above SPRNs */
#define CTR SPRN_CTR /* Counter Register */
@@ -1099,6 +1109,7 @@
#define SVR_P5040 0x820400
#define SVR_T4240 0x824000
#define SVR_T4120 0x824001
+#define SVR_T4160 0x824100
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
#define SVR_G4060 0x868003
generated by cgit v1.1 at 2024-12-26 14:17:44 +0000