diff options
Diffstat (limited to 'arch/powerpc/include/asm')
-rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 54 | ||||
-rw-r--r-- | arch/powerpc/include/asm/processor.h | 8 |
2 files changed, 62 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 9437301..040e71b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -92,20 +92,27 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +/* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +/* P1012 is single core version of P1021 */ #elif defined(CONFIG_P1012) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +/* P1013 is single core version of P1022 */ #elif defined(CONFIG_P1013) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -121,6 +128,27 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +/* P1015 is single core version of P1024 */ +#elif defined(CONFIG_P1015) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1016 is single core version of P1025 */ +#elif defined(CONFIG_P1016) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -137,6 +165,8 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS 2 @@ -144,6 +174,8 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_P1022) #define CONFIG_MAX_CPUS 2 @@ -164,6 +196,27 @@ #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 +/* P1024 is lower end variant of P1020 */ +#elif defined(CONFIG_P1024) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1025 is lower end variant of P1021 */ +#elif defined(CONFIG_P1025) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P2010 is single core version of P2020 */ #elif defined(CONFIG_P2010) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -220,6 +273,7 @@ #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 +/* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 32 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index d8b8f34..f5bf4dd 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1048,6 +1048,10 @@ #define SVR_P1013_E 0x80EF00 #define SVR_P1014 0x80F101 #define SVR_P1014_E 0x80F901 +#define SVR_P1015 0x80E502 +#define SVR_P1015_E 0x80ED02 +#define SVR_P1016 0x80E503 +#define SVR_P1016_E 0x80ED03 #define SVR_P1017 0x80F700 #define SVR_P1017_E 0x80FF00 #define SVR_P1020 0x80E400 @@ -1058,6 +1062,10 @@ #define SVR_P1022_E 0x80EE00 #define SVR_P1023 0x80F600 #define SVR_P1023_E 0x80FE00 +#define SVR_P1024 0x80E402 +#define SVR_P1024_E 0x80EC02 +#define SVR_P1025 0x80E403 +#define SVR_P1025_E 0x80EC03 #define SVR_P2010 0x80E300 #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 |