summaryrefslogtreecommitdiff
path: root/arch/powerpc/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'arch/powerpc/cpu')
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S11
-rw-r--r--arch/powerpc/cpu/mpc85xx/t1024_ids.c3
-rw-r--r--arch/powerpc/cpu/mpc85xx/t4240_serdes.c103
3 files changed, 60 insertions, 57 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index e61d8e0..a70fb71 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1052,6 +1052,17 @@ create_init_ram_area:
CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
+
+#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT)
+ /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
+ * to L3 Address configured by PBL for ISBC code
+ */
+ create_tlb1_entry 15, \
+ 1, BOOKE_PAGESZ_1M, \
+ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+ CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
+
#else
/*
* create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c
index 132689b..8a1092e 100644
--- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c
@@ -51,11 +51,10 @@ int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN
struct liodn_id_table fman1_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(1, 0, 88),
+ SET_FMAN_RX_10G_TYPE2_LIODN(1, 0, 88),
SET_FMAN_RX_1G_LIODN(1, 1, 89),
SET_FMAN_RX_1G_LIODN(1, 2, 90),
SET_FMAN_RX_1G_LIODN(1, 3, 91),
- SET_FMAN_RX_10G_LIODN(1, 0, 94),
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 74c4c81..7b43b28 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -214,8 +214,8 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
- {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
- {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
+ {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -266,37 +266,30 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
- {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
- XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ {1, {NONE, NONE, NONE, NONE,
XAUI_FM1_MAC10, XAUI_FM1_MAC10,
XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
- {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
- HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ {2, {NONE, NONE, NONE, NONE,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
- {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
- HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ {4, {NONE, NONE, NONE, NONE,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
- {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
- SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ {27, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
- SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ {28, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
- SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ {35, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
- SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ {36, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+ {37, {NONE, NONE, NONE, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },
- {38, {NONE, NONE, QSGMII_FM1_B, NONE,
+ {38, {NONE, NONE, NONE, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },
{}
};
@@ -363,45 +356,45 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{37, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{55, {NONE, XFI_FM1_MAC10,
XFI_FM2_MAC10, NONE,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -424,51 +417,51 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
- {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
+ {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
- {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ {11, {NONE, NONE, NONE, NONE,
PCIE2, PCIE2, PCIE2, PCIE2} },
- {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ {12, {NONE, NONE, NONE, NONE,
PCIE2, PCIE2, PCIE2, PCIE2} },
{13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2} },
{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2} },
- {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ {15, {NONE, NONE, NONE, NONE,
SRIO1, SRIO1, SRIO1, SRIO1} },
- {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ {16, {NONE, NONE, NONE, NONE,
SRIO1, SRIO1, SRIO1, SRIO1} },
- {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ {17, {NONE, NONE, NONE, NONE,
SRIO1, SRIO1, SRIO1, SRIO1} },
{18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- NONE, NONE, NONE, NONE} },
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{}
};
static const struct serdes_config serdes4_cfg_tbl[] = {
/* SerDes 4 */
- {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
- {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
- {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
- {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
- {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
- {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
- {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
- {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
- {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
- {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
- {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
- {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
- {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
- {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
- {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
+ {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
+ {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
+ {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
+ {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
+ {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
+ {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
+ {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+ {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+ {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+ {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+ {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} },
{}
}
;
generated by cgit v1.1 at 2024-09-17 22:36:52 +0000