diff options
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 114 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 14 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 12 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/ddr-gen1.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/ddr-gen2.c | 9 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 14 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 20 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 35 |
8 files changed, 192 insertions, 30 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 2be192d..e5ecf5d 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -24,6 +24,109 @@ #include <command.h> #include <linux/compiler.h> #include <asm/processor.h> +#include "fsl_corenet_serdes.h" + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004849 +/* + * This work-around is implemented in PBI, so just check to see if the + * work-around was actually applied. To do this, we check for specific data + * at specific addresses in DCSR. + * + * Array offsets[] contains a list of offsets within DCSR. According to the + * erratum document, the value at each offset should be 2. + */ +static void check_erratum_a4849(uint32_t svr) +{ + void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; + unsigned int i; + +#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) + static const uint8_t offsets[] = { + 0x50, 0x54, 0x58, 0x90, 0x94, 0x98 + }; +#endif +#ifdef CONFIG_PPC_P4080 + static const uint8_t offsets[] = { + 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac + }; +#endif + uint32_t x108; /* The value that should be at offset 0x108 */ + + for (i = 0; i < ARRAY_SIZE(offsets); i++) { + if (in_be32(dcsr + offsets[i]) != 2) { + printf("Work-around for Erratum A004849 is not enabled\n"); + return; + } + } + +#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) + x108 = 0x12; +#endif + +#ifdef CONFIG_PPC_P4080 + /* + * For P4080, the erratum document says that the value at offset 0x108 + * should be 0x12 on rev2, or 0x1c on rev3. + */ + if (SVR_MAJ(svr) == 2) + x108 = 0x12; + if (SVR_MAJ(svr) == 3) + x108 = 0x1c; +#endif + + if (in_be32(dcsr + 0x108) != x108) { + printf("Work-around for Erratum A004849 is not enabled\n"); + return; + } + + /* Everything matches, so the erratum work-around was applied */ + + printf("Work-around for Erratum A004849 enabled\n"); +} +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004580 +/* + * This work-around is implemented in PBI, so just check to see if the + * work-around was actually applied. To do this, we check for specific data + * at specific addresses in the SerDes register block. + * + * The work-around says that for each SerDes lane, write BnTTLCRy0 = + * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000. + + */ +static void check_erratum_a4580(uint32_t svr) +{ + const serdes_corenet_t __iomem *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + unsigned int lane; + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + if (serdes_lane_enabled(lane)) { + const struct serdes_lane __iomem *srds_lane = + &srds_regs->lane[serdes_get_lane_idx(lane)]; + + /* + * Verify that the values we were supposed to write in + * the PBI are actually there. Also, the lower 15 + * bits of res4[3] should be the same as the upper 15 + * bits of res4[1]. + */ + if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) || + (in_be32(&srds_lane->res4[1]) != 0x880000) || + (in_be32(&srds_lane->res4[3]) != 0x40000044)) { + printf("Work-around for Erratum A004580 is " + "not enabled\n"); + return; + } + } + } + + /* Everything matches, so the erratum work-around was applied */ + + printf("Work-around for Erratum A004580 enabled\n"); +} +#endif static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -137,6 +240,17 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 puts("Work-around for Erratum A004934 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004849 + /* This work-around is implemented in PBI, so just check for it */ + check_erratum_a4849(svr); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004580 + /* This work-around is implemented in PBI, so just check for it */ + check_erratum_a4580(svr); +#endif +#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 + puts("Work-around for Erratum PCIe-A003 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 78486aa..9b9832c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -451,21 +451,21 @@ static void dump_spd_ddr_reg(void) for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { switch (i) { case 0: - ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; + ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; break; -#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: - ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; + ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) case 2: - ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR; + ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) case 3: - ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR; + ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR; break; #endif default: diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 705c16c..d1155e8 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -350,6 +350,10 @@ int cpu_init_r(void) #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) + extern int spin_table_compat; + const char *spin; +#endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) @@ -395,6 +399,14 @@ int cpu_init_r(void) } #endif +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) + spin = getenv("spin_table_compat"); + if (spin && (*spin == 'n')) + spin_table_compat = 0; + else + spin_table_compat = 1; +#endif + puts ("L2: "); #if defined(CONFIG_L2_CACHE) diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c index 54437dd..8a86819 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c @@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num) { unsigned int i; - volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; + volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; if (ctrl_num != 0) { printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); @@ -73,7 +73,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, void ddr_enable_ecc(unsigned int dram_size) { - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c index 49000a1..a705862 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c @@ -19,15 +19,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num) { unsigned int i; -#ifdef CONFIG_MPC83xx - ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR; -#else - ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; -#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 + ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + +#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint svr; #endif -#endif if (ctrl_num) { printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index f118dd5..ef0dd1d 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -32,21 +32,21 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, switch (ctrl_num) { case 0: - ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; + ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; break; -#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: - ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; + ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) case 2: - ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR; + ddr = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) case 3: - ddr = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR; + ddr = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR; break; #endif default: diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 7f466ac..5495dc5 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -714,9 +714,13 @@ void fsl_serdes_init(void) #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 /* - * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for - * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or - * AURORA before the device is initialized. + * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1 + * for each of the SerDes lanes selected as SGMII, XAUI, SRIO, + * or AURORA before the device is initialized. + * + * Note that this part of the SERDES-9 work-around is + * redundant if the work-around for A-4580 has already been + * applied via PBI. */ switch (lane_prtcl) { case SGMII_FM1_DTSEC1: @@ -733,10 +737,12 @@ void fsl_serdes_init(void) case SRIO1: case SRIO2: case AURORA: - clrsetbits_be32(&srds_regs->lane[idx].ttlcr0, - SRDS_TTLCR0_FLT_SEL_MASK, - SRDS_TTLCR0_FLT_SEL_750PPM | - SRDS_TTLCR0_PM_DIS); + out_be32(&srds_regs->lane[idx].ttlcr0, + SRDS_TTLCR0_FLT_SEL_KFR_26 | + SRDS_TTLCR0_FLT_SEL_KPH_28 | + SRDS_TTLCR0_FLT_SEL_750PPM | + SRDS_TTLCR0_FREQOVD_EN); + break; default: break; } diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 4ba44a9..1f76925 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -351,6 +351,13 @@ __secondary_reset_vector: .align L1_CACHE_SHIFT .global __second_half_boot_page __second_half_boot_page: +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE + lis r3,(spin_table_compat - __second_half_boot_page)@h + ori r3,r3,(spin_table_compat - __second_half_boot_page)@l + add r3,r3,r11 /* r11 has the address of __second_half_boot_page */ + lwz r14,0(r3) +#endif + #define EPAPR_MAGIC 0x45504150 #define ENTRY_ADDR_UPPER 0 #define ENTRY_ADDR_LOWER 4 @@ -383,7 +390,24 @@ __second_half_boot_page: stw r8,ENTRY_ADDR_LOWER(r10) /* spin waiting for addr */ -3: lwz r4,ENTRY_ADDR_LOWER(r10) +3: +/* + * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled + * memory. Old OS may not work with this change. A patch is waiting to be + * accepted for Linux kernel. Other OS needs similar fix to spin table. + * For OSes with old spin table code, we can enable this temporary fix by + * setting environmental variable "spin_table_compat". For new OSes, set + * "spin_table_compat=no". After Linux is fixed, we can remove this macro + * and related code. For now, it is enabled by default. + */ +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE + cmpwi r14,0 + beq 4f + dcbf 0, r10 + sync +4: +#endif + lwz r4,ENTRY_ADDR_LOWER(r10) andi. r11,r4,1 bne 3b isync @@ -460,5 +484,14 @@ __second_half_boot_page: .globl __spin_table __spin_table: .space CONFIG_MAX_CPUS*ENTRY_SIZE + +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE + .align L1_CACHE_SHIFT + .global spin_table_compat +spin_table_compat: + .long 1 + +#endif + __spin_table_end: .space 4096 - (__spin_table_end - __spin_table) |