diff options
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/t4240_serdes.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 132 |
1 files changed, 132 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index 1316ed9..c001780 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -31,6 +31,7 @@ struct serdes_config { u8 lanes[SRDS_MAX_LANES]; }; +#ifdef CONFIG_PPC_T4240 static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, @@ -187,6 +188,137 @@ static const struct serdes_config serdes4_cfg_tbl[] = { {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} }; +#elif defined(CONFIG_PPC_T4160) +static const struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10} }, + {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, + {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, + {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, + {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, + {38, {NONE, NONE, QSGMII_FM1_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE} }, + {} +}; +static const struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + NONE, NONE} }, + {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {38, {NONE, NONE, QSGMII_FM2_B, NONE, + NONE, QSGMII_FM1_A, NONE, NONE} }, + {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, + {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, + {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, + {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + NONE, NONE, NONE, NONE} }, + {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, NONE, NONE} }, + {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, NONE, NONE} }, + {56, {NONE, XFI_FM1_MAC10, + XFI_FM2_MAC10, NONE, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {57, {NONE, XFI_FM1_MAC10, + XFI_FM2_MAC10, NONE, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + NONE, NONE} }, + {} +}; +static const struct serdes_config serdes3_cfg_tbl[] = { + /* SerDes 3 */ + {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, + {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, + {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, + {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, + {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, + {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, + {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, + {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, + {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, + {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, + {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + NONE, NONE, NONE, NONE} }, + {} +}; +static const struct serdes_config serdes4_cfg_tbl[] = { + /* SerDes 4 */ + {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, + {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, + {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, + {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} }, + {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} }, + {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, + {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, + {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} }, + {} +} +; +#else +#error "Need to define SerDes protocol" +#endif static const struct serdes_config *serdes_cfg_tbl[] = { serdes1_cfg_tbl, serdes2_cfg_tbl, |