diff options
Diffstat (limited to 'arch/mips/lib/cache.c')
| -rw-r--r-- | arch/mips/lib/cache.c | 101 |
1 files changed, 84 insertions, 17 deletions
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index db81953..bd14ba6 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -7,34 +7,85 @@ #include <common.h> #include <asm/cacheops.h> +#include <asm/cm.h> #include <asm/mipsregs.h> -static inline unsigned long icache_line_size(void) +DECLARE_GLOBAL_DATA_PTR; + +static void probe_l2(void) { - unsigned long conf1, il; +#ifdef CONFIG_MIPS_L2_CACHE + unsigned long conf2, sl; + bool l2c = false; + + if (!(read_c0_config1() & MIPS_CONF_M)) + return; - if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO)) - return CONFIG_SYS_ICACHE_LINE_SIZE; + conf2 = read_c0_config2(); + + if (__mips_isa_rev >= 6) { + l2c = conf2 & MIPS_CONF_M; + if (l2c) + l2c = read_c0_config3() & MIPS_CONF_M; + if (l2c) + l2c = read_c0_config4() & MIPS_CONF_M; + if (l2c) + l2c = read_c0_config5() & MIPS_CONF5_L2C; + } + + if (l2c && config_enabled(CONFIG_MIPS_CM)) { + gd->arch.l2_line_size = mips_cm_l2_line_size(); + } else if (l2c) { + /* We don't know how to retrieve L2 config on this system */ + BUG(); + } else { + sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF; + gd->arch.l2_line_size = sl ? (2 << sl) : 0; + } +#endif +} + +void mips_cache_probe(void) +{ +#ifdef CONFIG_SYS_CACHE_SIZE_AUTO + unsigned long conf1, il, dl; conf1 = read_c0_config1(); + il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF; - if (!il) - return 0; - return 2 << il; + dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF; + + gd->arch.l1i_line_size = il ? (2 << il) : 0; + gd->arch.l1d_line_size = dl ? (2 << dl) : 0; +#endif + probe_l2(); } -static inline unsigned long dcache_line_size(void) +static inline unsigned long icache_line_size(void) { - unsigned long conf1, dl; +#ifdef CONFIG_SYS_CACHE_SIZE_AUTO + return gd->arch.l1i_line_size; +#else + return CONFIG_SYS_ICACHE_LINE_SIZE; +#endif +} - if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO)) - return CONFIG_SYS_DCACHE_LINE_SIZE; +static inline unsigned long dcache_line_size(void) +{ +#ifdef CONFIG_SYS_CACHE_SIZE_AUTO + return gd->arch.l1d_line_size; +#else + return CONFIG_SYS_DCACHE_LINE_SIZE; +#endif +} - conf1 = read_c0_config1(); - dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF; - if (!dl) - return 0; - return 2 << dl; +static inline unsigned long scache_line_size(void) +{ +#ifdef CONFIG_MIPS_L2_CACHE + return gd->arch.l2_line_size; +#else + return 0; +#endif } #define cache_loop(start, end, lsize, ops...) do { \ @@ -53,12 +104,13 @@ void flush_cache(ulong start_addr, ulong size) { unsigned long ilsize = icache_line_size(); unsigned long dlsize = dcache_line_size(); + unsigned long slsize = scache_line_size(); /* aend will be miscalculated when size is zero, so we return here */ if (size == 0) return; - if (ilsize == dlsize) { + if ((ilsize == dlsize) && !slsize) { /* flush I-cache & D-cache simultaneously */ cache_loop(start_addr, start_addr + size, ilsize, HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I); @@ -68,6 +120,11 @@ void flush_cache(ulong start_addr, ulong size) /* flush D-cache */ cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D); + /* flush L2 cache */ + if (slsize) + cache_loop(start_addr, start_addr + size, slsize, + HIT_WRITEBACK_INV_SD); + /* flush I-cache */ cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); } @@ -75,21 +132,31 @@ void flush_cache(ulong start_addr, ulong size) void flush_dcache_range(ulong start_addr, ulong stop) { unsigned long lsize = dcache_line_size(); + unsigned long slsize = scache_line_size(); /* aend will be miscalculated when size is zero, so we return here */ if (start_addr == stop) return; cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D); + + /* flush L2 cache */ + if (slsize) + cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); } void invalidate_dcache_range(ulong start_addr, ulong stop) { unsigned long lsize = dcache_line_size(); + unsigned long slsize = scache_line_size(); /* aend will be miscalculated when size is zero, so we return here */ if (start_addr == stop) return; + /* invalidate L2 cache */ + if (slsize) + cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); + cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); } |