14 files changed, 6 insertions, 5230 deletions

diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
index f65b439..5381bf0 100644
--- a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
@@ -6,1499 +6,988 @@
 #ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__
 #define __BFIN_CDEF_ADSP_EDN_BF52x_extended__
 
-#define pSIC_RVECT                     ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
 #define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
 #define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
-#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* Interrupt Mask Register */
 #define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
 #define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
 #define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
 #define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
 #define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
 #define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
 #define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
 #define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
 #define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
 #define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* Interrupt Status Register */
 #define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
 #define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* Interrupt Wakeup Register */
 #define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
 #define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* Interrupt Mask register of SIC2 */
 #define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
 #define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* Interrupt Assignment register4 */
 #define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
 #define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* Interrupt Assignment register5 */
 #define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
 #define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* Interrupt Assignment register6 */
 #define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
 #define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* Interrupt Assignment register7 */
 #define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
 #define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* Interrupt Status register */
 #define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
 #define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* Interrupt Wakeup register */
 #define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
 #define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
 #define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
 #define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
 #define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
 #define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
 #define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
 #define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
 #define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
 #define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
 #define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
 #define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
 #define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
 #define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
 #define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
 #define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */
 #define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
 #define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
 #define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
 #define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */
 #define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
 #define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */
 #define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
 #define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */
 #define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
 #define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define pUART0_IER                     ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */
 #define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
 #define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
-#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */
 #define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
 #define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define pUART0_IIR                     ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */
 #define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
 #define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
-#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
 #define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
 #define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
 #define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
 #define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
 #define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
 #define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
 #define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
 #define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */
 #define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
 #define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
 #define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
 #define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */
 #define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
 #define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
-#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */
 #define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
 #define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
-#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT) /* SPI Status register */
 #define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
 #define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
-#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */
 #define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
 #define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
-#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */
 #define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
 #define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
-#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */
 #define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
 #define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
-#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */
 #define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
 #define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
-#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
 #define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
 #define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
 #define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
 #define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
 #define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
 #define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
 #define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
 #define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
 #define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
 #define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
 #define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
 #define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
 #define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
 #define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
 #define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
 #define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
 #define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
 #define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
 #define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
 #define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
 #define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
 #define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
 #define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
 #define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
 #define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
 #define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
 #define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
 #define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
 #define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
 #define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
 #define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
 #define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
 #define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
 #define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
 #define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
 #define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
 #define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
 #define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
 #define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
 #define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
 #define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
 #define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
 #define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
 #define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
 #define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
 #define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
 #define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */
 #define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
 #define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
 #define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
 #define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
 #define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
 #define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
 #define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
 #define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
 #define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER_ENABLE                  ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */
 #define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
 #define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define pTIMER_DISABLE                 ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */
 #define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
 #define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define pTIMER_STATUS                  ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */
 #define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
 #define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
-#define pPORTFIO                       ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */
 #define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
 #define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
-#define pPORTFIO_CLEAR                 ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */
 #define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
 #define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
-#define pPORTFIO_SET                   ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */
 #define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
 #define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
-#define pPORTFIO_TOGGLE                ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */
 #define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
 #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define pPORTFIO_MASKA                 ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */
 #define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
 #define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
-#define pPORTFIO_MASKA_CLEAR           ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */
 #define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
 #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define pPORTFIO_MASKA_SET             ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */
 #define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
 #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define pPORTFIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */
 #define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
 #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define pPORTFIO_MASKB                 ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */
 #define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
 #define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
-#define pPORTFIO_MASKB_CLEAR           ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */
 #define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
 #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define pPORTFIO_MASKB_SET             ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */
 #define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
 #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define pPORTFIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */
 #define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
 #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define pPORTFIO_DIR                   ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */
 #define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
 #define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
-#define pPORTFIO_POLAR                 ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */
 #define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
 #define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
-#define pPORTFIO_EDGE                  ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */
 #define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
 #define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
-#define pPORTFIO_BOTH                  ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */
 #define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
 #define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
-#define pPORTFIO_INEN                  ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register  */
 #define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
 #define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
-#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
 #define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
 #define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
 #define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
 #define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
 #define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
 #define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
 #define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
 #define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
 #define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
 #define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
 #define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
 #define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
 #define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
 #define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
 #define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
 #define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
 #define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
 #define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
 #define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
 #define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
 #define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
 #define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
 #define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
 #define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
 #define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */
 #define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
 #define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */
 #define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
 #define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */
 #define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
 #define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */
 #define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
 #define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */
 #define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
 #define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */
 #define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
 #define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */
 #define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
 #define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */
 #define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
 #define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
 #define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
 #define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
 #define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
 #define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 #define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
 #define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
 #define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
 #define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
 #define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
 #define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
 #define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
 #define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
 #define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
 #define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
 #define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
 #define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
 #define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
 #define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
 #define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
 #define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
 #define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */
 #define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
 #define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */
 #define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
 #define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */
 #define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
 #define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */
 #define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
 #define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */
 #define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
 #define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */
 #define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
 #define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */
 #define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
 #define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */
 #define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
 #define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
 #define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
 #define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */
 #define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
 #define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */
 #define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
 #define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */
 #define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
 #define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define pEBIU_SDBCTL                   ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */
 #define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
 #define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */
 #define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
 #define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */
 #define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
 #define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
 #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
 #define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
 #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
 #define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
 #define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
 #define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
 #define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
 #define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
 #define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
 #define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
 #define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
 #define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
 #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
 #define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
 #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
 #define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
 #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
 #define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
 #define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
 #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
 #define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
 #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
 #define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
 #define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
 #define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
 #define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
 #define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
 #define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
 #define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
 #define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
 #define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
 #define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
 #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
 #define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
 #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
 #define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
 #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
 #define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
 #define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
 #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
 #define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
 #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
 #define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
 #define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
 #define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
 #define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
 #define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
 #define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
 #define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
 #define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
 #define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
 #define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
 #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
 #define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
 #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
 #define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
 #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
 #define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
 #define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
 #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
 #define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
 #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
 #define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
 #define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
 #define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
 #define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
 #define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
 #define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
 #define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
 #define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
 #define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
 #define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
 #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
 #define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
 #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
 #define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
 #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
 #define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
 #define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
 #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
 #define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
 #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
 #define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
 #define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
 #define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
 #define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
 #define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
 #define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
 #define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
 #define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
 #define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
 #define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
 #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
 #define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
 #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
 #define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
 #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
 #define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
 #define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
 #define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
 #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
 #define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
 #define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
 #define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
 #define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
 #define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
 #define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
 #define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
 #define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
 #define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
 #define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
 #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
 #define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
 #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
 #define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
 #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
 #define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
 #define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR            ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
 #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
 #define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
 #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
 #define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
 #define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
 #define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
 #define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
 #define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
 #define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
 #define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
 #define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
 #define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
 #define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
 #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
 #define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
 #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
 #define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
 #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
 #define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
 #define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
 #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
 #define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
 #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
 #define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
 #define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
 #define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
 #define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
 #define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
 #define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
 #define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
 #define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
 #define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
 #define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
 #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
 #define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
 #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
 #define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
 #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
 #define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
 #define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
 #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
 #define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
 #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
 #define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
 #define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
 #define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
 #define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
 #define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
 #define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
 #define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
 #define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
 #define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
 #define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
 #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
 #define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
 #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
 #define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
 #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
 #define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
 #define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
 #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
 #define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
 #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
 #define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
 #define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
 #define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
 #define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
 #define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
 #define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
 #define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
 #define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
 #define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
 #define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
 #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
 #define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
 #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
 #define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
 #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
 #define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
 #define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
 #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
 #define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
 #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
 #define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
 #define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
 #define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
 #define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
 #define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
 #define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
 #define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
 #define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
 #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
 #define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
 #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
 #define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
 #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
 #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
 #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
 #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
 #define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
 #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
 #define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
 #define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
 #define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
 #define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
 #define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
 #define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
 #define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
 #define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
 #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
 #define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
 #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
 #define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
 #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
 #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
 #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */
 #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */
 #define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */
 #define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */
 #define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */
 #define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */
 #define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */
 #define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */
 #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */
 #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */
 #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */
 #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */
 #define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */
 #define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */
 #define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */
 #define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */
 #define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */
 #define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */
 #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */
 #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */
 #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */
 #define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */
 #define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */
 #define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */
 #define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */
 #define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */
 #define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */
 #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */
 #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */
 #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */
 #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
 #define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */
 #define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */
 #define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */
 #define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */
 #define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */
 #define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */
 #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */
 #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pPPI_CONTROL                   ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */
 #define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
 #define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define pPPI_STATUS                    ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */
 #define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
 #define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define pPPI_COUNT                     ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */
 #define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
 #define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define pPPI_DELAY                     ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */
 #define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
 #define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define pPPI_FRAME                     ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */
 #define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
 #define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define pTWI_CLKDIV                    ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */
 #define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
 #define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
-#define pTWI_CONTROL                   ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */
 #define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
 #define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
-#define pTWI_SLAVE_CTL                 ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */
 #define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
 #define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
-#define pTWI_SLAVE_STAT                ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */
 #define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
 #define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define pTWI_SLAVE_ADDR                ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */
 #define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
 #define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define pTWI_MASTER_CTL                ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */
 #define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
 #define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define pTWI_MASTER_STAT               ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */
 #define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
 #define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define pTWI_MASTER_ADDR               ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */
 #define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
 #define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define pTWI_INT_STAT                  ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */
 #define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
 #define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
-#define pTWI_INT_MASK                  ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */
 #define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
 #define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
-#define pTWI_FIFO_CTL                  ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */
 #define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
 #define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
-#define pTWI_FIFO_STAT                 ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */
 #define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
 #define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
-#define pTWI_XMT_DATA8                 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */
 #define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
 #define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
-#define pTWI_XMT_DATA16                ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */
 #define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
 #define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define pTWI_RCV_DATA8                 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */
 #define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
 #define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
-#define pTWI_RCV_DATA16                ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */
 #define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
 #define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define pPORTGIO                       ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */
 #define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
 #define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
-#define pPORTGIO_CLEAR                 ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */
 #define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
 #define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
-#define pPORTGIO_SET                   ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */
 #define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
 #define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
-#define pPORTGIO_TOGGLE                ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */
 #define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
 #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define pPORTGIO_MASKA                 ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */
 #define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
 #define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
-#define pPORTGIO_MASKA_CLEAR           ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */
 #define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
 #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define pPORTGIO_MASKA_SET             ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */
 #define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
 #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define pPORTGIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */
 #define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
 #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define pPORTGIO_MASKB                 ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */
 #define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
 #define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
-#define pPORTGIO_MASKB_CLEAR           ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */
 #define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
 #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define pPORTGIO_MASKB_SET             ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */
 #define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
 #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define pPORTGIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */
 #define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
 #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define pPORTGIO_DIR                   ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */
 #define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
 #define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
-#define pPORTGIO_POLAR                 ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */
 #define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
 #define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
-#define pPORTGIO_EDGE                  ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */
 #define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
 #define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
-#define pPORTGIO_BOTH                  ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */
 #define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
 #define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
-#define pPORTGIO_INEN                  ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */
 #define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
 #define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
-#define pPORTHIO                       ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */
 #define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
 #define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
-#define pPORTHIO_CLEAR                 ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */
 #define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
 #define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
-#define pPORTHIO_SET                   ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */
 #define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
 #define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
-#define pPORTHIO_TOGGLE                ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */
 #define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
 #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define pPORTHIO_MASKA                 ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */
 #define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
 #define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
-#define pPORTHIO_MASKA_CLEAR           ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */
 #define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
 #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define pPORTHIO_MASKA_SET             ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */
 #define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
 #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define pPORTHIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */
 #define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
 #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define pPORTHIO_MASKB                 ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */
 #define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
 #define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
-#define pPORTHIO_MASKB_CLEAR           ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */
 #define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
 #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define pPORTHIO_MASKB_SET             ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */
 #define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
 #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define pPORTHIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */
 #define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
 #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define pPORTHIO_DIR                   ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */
 #define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
 #define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
-#define pPORTHIO_POLAR                 ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */
 #define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
 #define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
-#define pPORTHIO_EDGE                  ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */
 #define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
 #define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
-#define pPORTHIO_BOTH                  ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */
 #define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
 #define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
-#define pPORTHIO_INEN                  ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */
 #define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
 #define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
-#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */
 #define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
 #define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */
 #define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
 #define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */
 #define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
 #define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define pUART1_IER                     ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */
 #define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
 #define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
-#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */
 #define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
 #define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define pUART1_IIR                     ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */
 #define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
 #define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
-#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
 #define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
 #define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
 #define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
 #define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
 #define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
 #define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
 #define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
 #define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */
 #define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
 #define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
 #define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
 #define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */
 #define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
 #define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */
 #define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
 #define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */
 #define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
 #define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
 #define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */
 #define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
 #define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */
 #define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
 #define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */
 #define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
 #define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */
 #define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
 #define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
 #define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */
 #define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
 #define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */
 #define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
 #define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */
 #define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
 #define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */
 #define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
 #define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define pPORTF_MUX                     ((uint16_t volatile *)PORTF_MUX) /* Port F mux control */
 #define bfin_read_PORTF_MUX()          bfin_read16(PORTF_MUX)
 #define bfin_write_PORTF_MUX(val)      bfin_write16(PORTF_MUX, val)
-#define pPORTG_MUX                     ((uint16_t volatile *)PORTG_MUX) /* Port G mux control */
 #define bfin_read_PORTG_MUX()          bfin_read16(PORTG_MUX)
 #define bfin_write_PORTG_MUX(val)      bfin_write16(PORTG_MUX, val)
-#define pPORTH_MUX                     ((uint16_t volatile *)PORTH_MUX) /* Port H mux control */
 #define bfin_read_PORTH_MUX()          bfin_read16(PORTH_MUX)
 #define bfin_write_PORTH_MUX(val)      bfin_write16(PORTH_MUX, val)
-#define pPORTF_DRIVE                   ((uint16_t volatile *)PORTF_DRIVE) /* Port F drive strength control */
 #define bfin_read_PORTF_DRIVE()        bfin_read16(PORTF_DRIVE)
 #define bfin_write_PORTF_DRIVE(val)    bfin_write16(PORTF_DRIVE, val)
-#define pPORTG_DRIVE                   ((uint16_t volatile *)PORTG_DRIVE) /* Port G drive strength control */
 #define bfin_read_PORTG_DRIVE()        bfin_read16(PORTG_DRIVE)
 #define bfin_write_PORTG_DRIVE(val)    bfin_write16(PORTG_DRIVE, val)
-#define pPORTH_DRIVE                   ((uint16_t volatile *)PORTH_DRIVE) /* Port H drive strength control */
 #define bfin_read_PORTH_DRIVE()        bfin_read16(PORTH_DRIVE)
 #define bfin_write_PORTH_DRIVE(val)    bfin_write16(PORTH_DRIVE, val)
-#define pPORTF_SLEW                    ((uint16_t volatile *)PORTF_SLEW) /* Port F slew control */
 #define bfin_read_PORTF_SLEW()         bfin_read16(PORTF_SLEW)
 #define bfin_write_PORTF_SLEW(val)     bfin_write16(PORTF_SLEW, val)
-#define pPORTG_SLEW                    ((uint16_t volatile *)PORTG_SLEW) /* Port G slew control */
 #define bfin_read_PORTG_SLEW()         bfin_read16(PORTG_SLEW)
 #define bfin_write_PORTG_SLEW(val)     bfin_write16(PORTG_SLEW, val)
-#define pPORTH_SLEW                    ((uint16_t volatile *)PORTH_SLEW) /* Port H slew control */
 #define bfin_read_PORTH_SLEW()         bfin_read16(PORTH_SLEW)
 #define bfin_write_PORTH_SLEW(val)     bfin_write16(PORTH_SLEW, val)
-#define pPORTF_HYSTERESIS              ((uint16_t volatile *)PORTF_HYSTERESIS) /* Port F Schmitt trigger control */
 #define bfin_read_PORTF_HYSTERESIS()   bfin_read16(PORTF_HYSTERESIS)
 #define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define pPORTG_HYSTERESIS              ((uint16_t volatile *)PORTG_HYSTERESIS) /* Port G Schmitt trigger control */
 #define bfin_read_PORTG_HYSTERESIS()   bfin_read16(PORTG_HYSTERESIS)
 #define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define pPORTH_HYSTERESIS              ((uint16_t volatile *)PORTH_HYSTERESIS) /* Port H Schmitt trigger control */
 #define bfin_read_PORTH_HYSTERESIS()   bfin_read16(PORTH_HYSTERESIS)
 #define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define pNONGPIO_DRIVE                 ((uint16_t volatile *)NONGPIO_DRIVE) /* Non-GPIO Port drive strength control */
 #define bfin_read_NONGPIO_DRIVE()      bfin_read16(NONGPIO_DRIVE)
 #define bfin_write_NONGPIO_DRIVE(val)  bfin_write16(NONGPIO_DRIVE, val)
-#define pNONGPIO_SLEW                  ((uint16_t volatile *)NONGPIO_SLEW) /* Non-GPIO Port slew control */
 #define bfin_read_NONGPIO_SLEW()       bfin_read16(NONGPIO_SLEW)
 #define bfin_write_NONGPIO_SLEW(val)   bfin_write16(NONGPIO_SLEW, val)
-#define pNONGPIO_HYSTERESIS            ((uint16_t volatile *)NONGPIO_HYSTERESIS) /* Non-GPIO Port Schmitt trigger control */
 #define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
 #define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
-#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOST Control Register */
 #define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
 #define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
-#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOST Status Register */
 #define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
 #define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
-#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOST Acknowledge Mode Timeout Register */
 #define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
 #define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
-#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration/Control Register */
 #define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
 #define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
 #define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
 #define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register */
 #define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
 #define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
 #define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
 #define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Prescaler Register */
 #define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
 #define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
 #define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
 #define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Boundary Value Register */
 #define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
 #define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Boundary Value Register */
 #define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
 #define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
 #define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
 #define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
 #define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
 #define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
 #define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
 #define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
 #define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
 #define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
 #define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
 #define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
 #define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
 #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
 #define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
 #define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
 #define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
 #define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
 #define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
 #define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
 #define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
 #define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
 #define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
 #define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
 #define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
 #define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
 #define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
 #define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
 #define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
 #define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
 #define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
 #define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
 #define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
 #define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
 #define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
 #define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
 #define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
 #define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
 #define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
 #define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
 #define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
 #define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
 #define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
 #define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
 #define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
 #define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
 #define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
 #define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
 #define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
 #define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
 #define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
 #define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
-#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
-#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
-#define bfin_read_TBUF()               bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
-#define pPFCTL                         ((uint32_t volatile *)PFCTL)
-#define bfin_read_PFCTL()              bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
-#define pPFCNTR0                       ((uint32_t volatile *)PFCNTR0)
-#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
-#define pPFCNTR1                       ((uint32_t volatile *)PFCNTR1)
-#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
-#define pDMA_TC_CNT                    ((uint16_t volatile *)DMA_TC_CNT)
 #define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
 #define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
-#define pDMA_TC_PER                    ((uint16_t volatile *)DMA_TC_PER)
 #define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
 #define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h
index 0b38480..7b97aee 100644
--- a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h
+++ b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h
@@ -497,12 +497,6 @@
 #define NFC_CMD                        0xFFC03744 /* NAND Command Register */
 #define NFC_DATA_WR                    0xFFC03748 /* NAND Data Write Register */
 #define NFC_DATA_RD                    0xFFC0374C /* NAND Data Read Register */
-#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF                           0xFFE06100 /* Trace Buffer */
-#define PFCTL                          0xFFE08000
-#define PFCNTR0                        0xFFE08100
-#define PFCNTR1                        0xFFE08104
 #define DMA_TC_CNT                     0xFFC00B0C
 #define DMA_TC_PER                     0xFFC00B10
 
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
index 987cc86..9ce41b1 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
@@ -10,332 +10,21 @@
 
 #include "ADSP-EDN-BF52x-extended_cdef.h"
 
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0()               bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1()               bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2()               bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3()               bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4()               bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5()               bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6()               bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7()               bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8()               bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9()               bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10()              bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11()              bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12()              bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13()              bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14()              bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15()              bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT()               bfin_read32(ILAT)
-#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK()              bfin_read32(IMASK)
-#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND()              bfin_read32(IPEND)
-#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO()              bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL()              bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE()             bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
 
 #endif /* __BFIN_CDEF_ADSP_BF522_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_def.h b/arch/blackfin/include/asm/mach-bf527/BF522_def.h
index bc05029..a6b0787 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF522_def.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF522_def.h
@@ -18,106 +18,5 @@
 #define CHIPID                         0xFFC00014
 #define SWRST                          0xFFC00100 /* Software Reset Register */
 #define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
-#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
-#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
-#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
-#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
 
 #endif /* __BFIN_DEF_ADSP_BF522_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
index 390f3dc..593330e 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
@@ -1,341 +1 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF523_proc__
-#define __BFIN_CDEF_ADSP_BF523_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF52x-extended_cdef.h"
-
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0()               bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1()               bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2()               bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3()               bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4()               bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5()               bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6()               bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7()               bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8()               bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9()               bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10()              bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11()              bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12()              bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13()              bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14()              bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15()              bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT()               bfin_read32(ILAT)
-#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK()              bfin_read32(IMASK)
-#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND()              bfin_read32(IPEND)
-#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO()              bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL()              bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE()             bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF523_proc__ */
+#include "BF522_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_def.h b/arch/blackfin/include/asm/mach-bf527/BF523_def.h
index c27fd64..e88a450 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF523_def.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF523_def.h
@@ -1,123 +1 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF523_proc__
-#define __BFIN_DEF_ADSP_BF523_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF52x-extended_def.h"
-
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
-#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
-#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
-#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
-#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
-
-#endif /* __BFIN_DEF_ADSP_BF523_proc__ */
+#include "BF522_def.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
index 9ec89c6..25612bf 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
@@ -10,838 +10,358 @@
 
 #include "ADSP-EDN-BF52x-extended_cdef.h"
 
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0()               bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1()               bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2()               bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3()               bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4()               bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5()               bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6()               bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7()               bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8()               bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9()               bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10()              bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11()              bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12()              bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13()              bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14()              bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15()              bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT()               bfin_read32(ILAT)
-#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK()              bfin_read32(IMASK)
-#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND()              bfin_read32(IPEND)
-#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO()              bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL()              bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE()             bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
 #define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
 #define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 #define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
 #define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
 #define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
 #define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
 #define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
 #define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
 #define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
 #define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
 #define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
 #define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
 #define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
 #define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
 #define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
 #define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
 #define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
 #define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
 #define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
 #define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 #define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
 #define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
 #define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
 #define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
 #define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
 #define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
 #define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
 #define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
 #define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
 #define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
 #define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 #define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
 #define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
 #define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 #define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
 #define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 #define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
 #define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
 #define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
 #define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
 #define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
 #define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
 #define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
 #define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
 #define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
 #define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
 #define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
 #define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
 #define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
 #define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
 #define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
 #define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
 #define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
 #define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
 #define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
 #define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
 #define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
 #define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
 #define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
 #define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
 #define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
 #define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
 #define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
 #define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
 #define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
 #define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
 #define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
 #define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
 #define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
 #define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 #define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
 #define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
 #define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
 #define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
 #define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
 #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
 #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
 #define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
 #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
 #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
 #define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
 #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
 #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
 #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
 #define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
 #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
 #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
 #define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
 #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
 #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
 #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
 #define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
 #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
 #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
 #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
 #define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
 #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
 #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
 #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
 #define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
 #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
 #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
 #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
 #define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
 #define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
 #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
 #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
 #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
 #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
 #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
 #define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
 #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
 #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
 #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
 #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
 #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
 #define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
 #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
 #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
 #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
 #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
 #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
 #define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
 #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
 #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
 #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
 #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
 #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
 #define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
 #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
 #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
 #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
 #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
 #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
 #define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
 #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
 #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
 #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
 #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
 #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
 #define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
 #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
 #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
 #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
 #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
 #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
 #define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
 #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
 #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
 #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
 #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
 #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_def.h b/arch/blackfin/include/asm/mach-bf527/BF524_def.h
index bd6aa8f..0a0056a 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF524_def.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF524_def.h
@@ -18,107 +18,6 @@
 #define CHIPID                         0xFFC00014
 #define SWRST                          0xFFC00100 /* Software Reset Register */
 #define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
-#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
-#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
-#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
-#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
 #define USB_FADDR                      0xFFC03800 /* Function address register */
 #define USB_POWER                      0xFFC03804 /* Power management register */
 #define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
index 8fe29db..415eb07 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
@@ -1,848 +1 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF525_proc__
-#define __BFIN_CDEF_ADSP_BF525_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF52x-extended_cdef.h"
-
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0()               bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1()               bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2()               bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3()               bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4()               bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5()               bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6()               bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7()               bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8()               bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9()               bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10()              bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11()              bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12()              bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13()              bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14()              bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15()              bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT()               bfin_read32(ILAT)
-#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK()              bfin_read32(IMASK)
-#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND()              bfin_read32(IPEND)
-#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO()              bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL()              bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE()             bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
-#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
-#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
-#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
-#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
-#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
-#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
-#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
-#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
-#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
-#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
-#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
-#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
-#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
-#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
-#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
-#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
-#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
-#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
-#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
-#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
-#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
-#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
-#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
-#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
-#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
-#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
-#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
-#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
-#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
-#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
-#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
-#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
-#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
-#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
-#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
-#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
-#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
-#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
-#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
-#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
-#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
-#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
-#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
-#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
-#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
-#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
-#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
-#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
-#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
-#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
-#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
-#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
-#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
-#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
-#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
-#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
-#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
-#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
-#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF525_proc__ */
+#include "BF524_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF525_def.h b/arch/blackfin/include/asm/mach-bf527/BF525_def.h
index 5e88b3b..930cb59 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF525_def.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF525_def.h
@@ -1,292 +1 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF525_proc__
-#define __BFIN_DEF_ADSP_BF525_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF52x-extended_def.h"
-
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
-#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
-#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
-#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
-#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
-#define USB_FADDR                      0xFFC03800 /* Function address register */
-#define USB_POWER                      0xFFC03804 /* Power management register */
-#define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX                     0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE                    0xFFC03810 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE                    0xFFC03814 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB                    0xFFC03818 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE                   0xFFC0381C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME                      0xFFC03820 /* USB frame number */
-#define USB_INDEX                      0xFFC03824 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE                   0xFFC03828 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR                   0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL                 0xFFC03830 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET              0xFFC03840 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0                       0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR                      0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET              0xFFC03848 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR                      0xFFC0384C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0                     0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT                    0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE                     0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0                  0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL                 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE                     0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL                 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT                    0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO                   0xFFC03880 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO                   0xFFC03888 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO                   0xFFC03890 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO                   0xFFC03898 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO                   0xFFC038A0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO                   0xFFC038A8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO                   0xFFC038B0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO                   0xFFC038B8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL                0xFFC03900 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ               0xFFC03904 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK              0xFFC03908 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO                   0xFFC03948 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN                      0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1                    0xFFC03950 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1                    0xFFC03954 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1                    0xFFC03958 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL                 0xFFC039E0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB                 0xFFC039E4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2                0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST                   0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL                0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV                 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP              0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR               0xFFC03A04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP              0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR               0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT             0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE              0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL          0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE              0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL          0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT             0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP              0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR               0xFFC03A44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP              0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR               0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT             0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE              0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL          0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE              0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL          0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT             0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP              0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR               0xFFC03A84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP              0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR               0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT             0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE              0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL          0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE              0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL          0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT             0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP              0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR               0xFFC03AC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP              0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR               0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT             0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE              0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL          0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE              0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL          0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT             0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP              0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR               0xFFC03B04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP              0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR               0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT             0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE              0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL          0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE              0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL          0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT             0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP              0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR               0xFFC03B44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP              0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR               0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT             0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE              0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL          0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE              0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL          0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT             0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP              0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR               0xFFC03B84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP              0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR               0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT             0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE              0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL          0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE              0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL          0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT             0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP              0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR               0xFFC03BC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP              0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR               0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT             0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE              0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL          0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE              0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL          0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT             0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT              0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL               0xFFC03C04 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW               0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH              0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW              0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH             0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL               0xFFC03C24 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW               0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH              0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW              0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH             0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL               0xFFC03C44 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW               0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH              0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW              0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH             0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL               0xFFC03C64 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW               0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH              0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW              0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH             0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL               0xFFC03C84 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW               0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH              0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW              0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH             0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL               0xFFC03CA4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW               0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH              0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW              0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH             0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL               0xFFC03CC4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW               0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH              0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW              0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH             0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL               0xFFC03CE4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW               0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH              0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW              0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH             0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_BF525_proc__ */
+#include "BF524_def.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
index 9438862..aa320ac 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
@@ -10,1075 +10,516 @@
 
 #include "ADSP-EDN-BF52x-extended_cdef.h"
 
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0()               bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1()               bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2()               bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3()               bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4()               bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5()               bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6()               bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7()               bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8()               bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9()               bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10()              bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11()              bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12()              bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13()              bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14()              bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15()              bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT()               bfin_read32(ILAT)
-#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK()              bfin_read32(IMASK)
-#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND()              bfin_read32(IPEND)
-#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO()              bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL()              bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE()             bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
 #define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
 #define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
-#define pEMAC_ADDRLO                   ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
 #define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
 #define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
-#define pEMAC_ADDRHI                   ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
 #define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
 #define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
-#define pEMAC_HASHLO                   ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
 #define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
 #define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
-#define pEMAC_HASHHI                   ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
 #define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
 #define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
-#define pEMAC_STAADD                   ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
 #define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
 #define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
-#define pEMAC_STADAT                   ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
 #define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
 #define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
-#define pEMAC_FLC                      ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
 #define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
 #define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
-#define pEMAC_VLAN1                    ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
 #define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
 #define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
-#define pEMAC_VLAN2                    ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
 #define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
 #define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
-#define pEMAC_WKUP_CTL                 ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
 #define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
 #define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
-#define pEMAC_WKUP_FFMSK0              ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
 #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define pEMAC_WKUP_FFMSK1              ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
 #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define pEMAC_WKUP_FFMSK2              ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
 #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define pEMAC_WKUP_FFMSK3              ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
 #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define pEMAC_WKUP_FFCMD               ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
 #define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
 #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define pEMAC_WKUP_FFOFF               ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
 #define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
 #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define pEMAC_WKUP_FFCRC0              ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
 #define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
 #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define pEMAC_WKUP_FFCRC1              ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
 #define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
 #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define pEMAC_SYSCTL                   ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
 #define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
 #define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
-#define pEMAC_SYSTAT                   ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
 #define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
 #define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
-#define pEMAC_RX_STAT                  ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
 #define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
 #define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
-#define pEMAC_RX_STKY                  ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
 #define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
 #define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
-#define pEMAC_RX_IRQE                  ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
 #define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
 #define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
-#define pEMAC_TX_STAT                  ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
 #define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
 #define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
-#define pEMAC_TX_STKY                  ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
 #define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
 #define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
-#define pEMAC_TX_IRQE                  ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
 #define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
 #define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
-#define pEMAC_MMC_CTL                  ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
 #define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
 #define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
-#define pEMAC_MMC_RIRQS                ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
 #define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
 #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define pEMAC_MMC_RIRQE                ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
 #define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
 #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define pEMAC_MMC_TIRQS                ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
 #define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define pEMAC_MMC_TIRQE                ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
 #define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
 #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define pEMAC_RXC_OK                   ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
 #define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
 #define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
-#define pEMAC_RXC_FCS                  ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
 #define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
 #define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
-#define pEMAC_RXC_ALIGN                ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
 #define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
 #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define pEMAC_RXC_OCTET                ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
 #define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
 #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define pEMAC_RXC_DMAOVF               ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
 #define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
 #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define pEMAC_RXC_UNICST               ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
 #define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
 #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define pEMAC_RXC_MULTI                ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
 #define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
 #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define pEMAC_RXC_BROAD                ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
 #define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
 #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define pEMAC_RXC_LNERRI               ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
 #define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
 #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define pEMAC_RXC_LNERRO               ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
 #define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
 #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define pEMAC_RXC_LONG                 ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
 #define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
 #define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
-#define pEMAC_RXC_MACCTL               ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
 #define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
 #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define pEMAC_RXC_OPCODE               ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
 #define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
 #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define pEMAC_RXC_PAUSE                ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
 #define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
 #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define pEMAC_RXC_ALLFRM               ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
 #define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
 #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define pEMAC_RXC_ALLOCT               ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
 #define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
 #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define pEMAC_RXC_TYPED                ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count  */
 #define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
 #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define pEMAC_RXC_SHORT                ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
 #define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
 #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define pEMAC_RXC_EQ64                 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
 #define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
 #define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
-#define pEMAC_RXC_LT128                ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count  64 <= x < 128 */
 #define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
 #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define pEMAC_RXC_LT256                ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
 #define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
 #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define pEMAC_RXC_LT512                ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
 #define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
 #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define pEMAC_RXC_LT1024               ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
 #define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
 #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define pEMAC_RXC_GE1024               ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
 #define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
 #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define pEMAC_TXC_OK                   ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
 #define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
 #define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
-#define pEMAC_TXC_1COL                 ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
 #define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
 #define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
-#define pEMAC_TXC_GT1COL               ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
 #define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
 #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define pEMAC_TXC_OCTET                ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
 #define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
 #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define pEMAC_TXC_DEFER                ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
 #define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
 #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define pEMAC_TXC_LATECL               ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
 #define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
 #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define pEMAC_TXC_XS_COL               ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
 #define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
 #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define pEMAC_TXC_DMAUND               ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
 #define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
 #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define pEMAC_TXC_CRSERR               ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
 #define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
 #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define pEMAC_TXC_UNICST               ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
 #define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
 #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define pEMAC_TXC_MULTI                ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
 #define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
 #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define pEMAC_TXC_BROAD                ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
 #define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
 #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define pEMAC_TXC_XS_DFR               ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
 #define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
 #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define pEMAC_TXC_MACCTL               ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
 #define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
 #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define pEMAC_TXC_ALLFRM               ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
 #define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
 #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define pEMAC_TXC_ALLOCT               ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
 #define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
 #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define pEMAC_TXC_EQ64                 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
 #define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
 #define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
-#define pEMAC_TXC_LT128                ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count  64 <= x < 128 */
 #define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
 #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define pEMAC_TXC_LT256                ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
 #define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
 #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define pEMAC_TXC_LT512                ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
 #define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
 #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define pEMAC_TXC_LT1024               ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
 #define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
 #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define pEMAC_TXC_GE1024               ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
 #define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
 #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define pEMAC_TXC_ABORT                ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
 #define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
 #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
 #define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
 #define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 #define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
 #define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
 #define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
 #define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
 #define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
 #define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
 #define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
 #define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
 #define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
 #define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
 #define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
 #define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
 #define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
 #define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
 #define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
 #define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
 #define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
 #define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 #define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
 #define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
 #define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
 #define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
 #define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
 #define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
 #define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
 #define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
 #define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
 #define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
 #define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 #define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
 #define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
 #define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 #define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
 #define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 #define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
 #define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
 #define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
 #define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
 #define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
 #define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
 #define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
 #define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
 #define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
 #define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
 #define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
 #define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
 #define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
 #define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
 #define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
 #define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
 #define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
 #define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
 #define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
 #define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
 #define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
 #define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
 #define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
 #define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
 #define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
 #define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
 #define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
 #define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
 #define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
 #define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
 #define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
 #define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
 #define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
 #define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 #define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
 #define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
 #define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
 #define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
 #define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
 #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
 #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
 #define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
 #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
 #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
 #define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
 #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
 #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
 #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
 #define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
 #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
 #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
 #define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
 #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
 #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
 #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
 #define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
 #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
 #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
 #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
 #define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
 #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
 #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
 #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
 #define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
 #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
 #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
 #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
 #define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
 #define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
 #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
 #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
 #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
 #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
 #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
 #define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
 #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
 #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
 #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
 #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
 #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
 #define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
 #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
 #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
 #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
 #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
 #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
 #define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
 #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
 #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
 #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
 #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
 #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
 #define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
 #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
 #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
 #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
 #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
 #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
 #define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
 #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
 #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
 #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
 #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
 #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
 #define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
 #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
 #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
 #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
 #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
 #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
 #define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
 #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
 #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
 #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
 #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
 #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_def.h b/arch/blackfin/include/asm/mach-bf527/BF526_def.h
index 2644abf..935d11e 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF526_def.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF526_def.h
@@ -18,107 +18,6 @@
 #define CHIPID                         0xFFC00014
 #define SWRST                          0xFFC00100 /* Software Reset Register */
 #define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
-#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
-#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
-#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
-#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
 #define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
 #define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
 #define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
index fb9b307..c5abe62 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
@@ -1,1085 +1 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF527_proc__
-#define __BFIN_CDEF_ADSP_BF527_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF52x-extended_cdef.h"
-
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
-#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
-#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
-#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
-#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
-#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
-#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
-#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
-#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
-#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
-#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
-#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
-#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
-#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
-#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
-#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
-#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
-#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
-#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
-#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
-#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
-#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
-#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
-#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
-#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
-#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
-#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
-#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
-#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
-#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
-#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
-#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
-#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
-#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
-#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
-#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
-#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
-#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
-#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
-#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
-#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
-#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
-#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
-#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
-#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
-#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
-#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
-#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
-#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
-#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
-#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
-#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
-#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
-#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
-#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
-#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
-#define bfin_read_EVT0()               bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
-#define bfin_read_EVT1()               bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
-#define bfin_read_EVT2()               bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
-#define bfin_read_EVT3()               bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
-#define bfin_read_EVT4()               bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
-#define bfin_read_EVT5()               bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
-#define bfin_read_EVT6()               bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
-#define bfin_read_EVT7()               bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
-#define bfin_read_EVT8()               bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
-#define bfin_read_EVT9()               bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
-#define bfin_read_EVT10()              bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
-#define bfin_read_EVT11()              bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
-#define bfin_read_EVT12()              bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
-#define bfin_read_EVT13()              bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
-#define bfin_read_EVT14()              bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
-#define bfin_read_EVT15()              bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
-#define bfin_read_ILAT()               bfin_read32(ILAT)
-#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
-#define bfin_read_IMASK()              bfin_read32(IMASK)
-#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
-#define bfin_read_IPEND()              bfin_read32(IPEND)
-#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
-#define bfin_read_IPRIO()              bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
-#define bfin_read_TCNTL()              bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
-#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
-#define bfin_read_TSCALE()             bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
-#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
-#define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
-#define pEMAC_ADDRLO                   ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
-#define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
-#define pEMAC_ADDRHI                   ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
-#define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
-#define pEMAC_HASHLO                   ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
-#define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
-#define pEMAC_HASHHI                   ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
-#define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
-#define pEMAC_STAADD                   ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
-#define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
-#define pEMAC_STADAT                   ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
-#define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
-#define pEMAC_FLC                      ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
-#define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
-#define pEMAC_VLAN1                    ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
-#define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
-#define pEMAC_VLAN2                    ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
-#define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
-#define pEMAC_WKUP_CTL                 ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
-#define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
-#define pEMAC_WKUP_FFMSK0              ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define pEMAC_WKUP_FFMSK1              ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define pEMAC_WKUP_FFMSK2              ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define pEMAC_WKUP_FFMSK3              ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define pEMAC_WKUP_FFCMD               ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
-#define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define pEMAC_WKUP_FFOFF               ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
-#define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define pEMAC_WKUP_FFCRC0              ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define pEMAC_WKUP_FFCRC1              ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define pEMAC_SYSCTL                   ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
-#define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
-#define pEMAC_SYSTAT                   ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
-#define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
-#define pEMAC_RX_STAT                  ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
-#define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
-#define pEMAC_RX_STKY                  ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
-#define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
-#define pEMAC_RX_IRQE                  ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
-#define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
-#define pEMAC_TX_STAT                  ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
-#define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
-#define pEMAC_TX_STKY                  ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
-#define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
-#define pEMAC_TX_IRQE                  ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
-#define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
-#define pEMAC_MMC_CTL                  ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
-#define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
-#define pEMAC_MMC_RIRQS                ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
-#define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define pEMAC_MMC_RIRQE                ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
-#define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define pEMAC_MMC_TIRQS                ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
-#define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define pEMAC_MMC_TIRQE                ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
-#define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define pEMAC_RXC_OK                   ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
-#define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
-#define pEMAC_RXC_FCS                  ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
-#define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
-#define pEMAC_RXC_ALIGN                ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
-#define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define pEMAC_RXC_OCTET                ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
-#define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define pEMAC_RXC_DMAOVF               ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
-#define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define pEMAC_RXC_UNICST               ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
-#define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define pEMAC_RXC_MULTI                ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
-#define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define pEMAC_RXC_BROAD                ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
-#define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define pEMAC_RXC_LNERRI               ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
-#define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define pEMAC_RXC_LNERRO               ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
-#define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define pEMAC_RXC_LONG                 ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
-#define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
-#define pEMAC_RXC_MACCTL               ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
-#define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define pEMAC_RXC_OPCODE               ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
-#define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define pEMAC_RXC_PAUSE                ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
-#define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define pEMAC_RXC_ALLFRM               ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
-#define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define pEMAC_RXC_ALLOCT               ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
-#define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define pEMAC_RXC_TYPED                ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count  */
-#define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define pEMAC_RXC_SHORT                ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
-#define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define pEMAC_RXC_EQ64                 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
-#define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
-#define pEMAC_RXC_LT128                ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count  64 <= x < 128 */
-#define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define pEMAC_RXC_LT256                ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define pEMAC_RXC_LT512                ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define pEMAC_RXC_LT1024               ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define pEMAC_RXC_GE1024               ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
-#define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define pEMAC_TXC_OK                   ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
-#define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
-#define pEMAC_TXC_1COL                 ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
-#define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
-#define pEMAC_TXC_GT1COL               ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
-#define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define pEMAC_TXC_OCTET                ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
-#define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define pEMAC_TXC_DEFER                ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
-#define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define pEMAC_TXC_LATECL               ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
-#define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define pEMAC_TXC_XS_COL               ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
-#define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define pEMAC_TXC_DMAUND               ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
-#define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define pEMAC_TXC_CRSERR               ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
-#define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define pEMAC_TXC_UNICST               ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
-#define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define pEMAC_TXC_MULTI                ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
-#define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define pEMAC_TXC_BROAD                ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
-#define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define pEMAC_TXC_XS_DFR               ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
-#define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define pEMAC_TXC_MACCTL               ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
-#define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define pEMAC_TXC_ALLFRM               ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
-#define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define pEMAC_TXC_ALLOCT               ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
-#define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define pEMAC_TXC_EQ64                 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
-#define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
-#define pEMAC_TXC_LT128                ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count  64 <= x < 128 */
-#define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define pEMAC_TXC_LT256                ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define pEMAC_TXC_LT512                ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define pEMAC_TXC_LT1024               ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define pEMAC_TXC_GE1024               ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
-#define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define pEMAC_TXC_ABORT                ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
-#define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
-#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
-#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
-#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
-#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
-#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
-#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
-#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
-#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
-#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
-#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
-#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
-#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
-#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
-#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
-#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
-#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
-#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
-#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
-#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
-#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
-#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
-#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
-#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
-#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
-#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
-#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
-#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
-#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
-#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
-#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
-#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
-#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
-#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
-#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
-#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
-#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
-#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
-#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
-#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
-#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
-#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
-#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
-#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
-#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
-#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
-#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
-#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
-#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
-#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
-#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
-#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
-#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
-#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
-#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
-#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
-#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
-#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
-#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
-#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF527_proc__ */
+#include "BF526_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF527_def.h b/arch/blackfin/include/asm/mach-bf527/BF527_def.h
index c46c2b0..9541674 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF527_def.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF527_def.h
@@ -1,371 +1 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF527_proc__
-#define __BFIN_DEF_ADSP_BF527_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF52x-extended_def.h"
-
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
-#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
-#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
-#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
-#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
-#define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO                    0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI                    0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD                    0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT                    0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC                       0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1                     0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2                     0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL                  0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0               0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1               0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2               0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3               0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD                0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF                0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0               0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1               0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define EMAC_SYSCTL                    0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT                    0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT                   0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY                   0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE                   0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT                   0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY                   0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE                   0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-#define EMAC_MMC_CTL                   0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS                 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE                 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS                 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE                 0xFFC03090 /* MMC TX Interrupt Enables Register */
-#define EMAC_RXC_OK                    0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS                   0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN                 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET                 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF                0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST                0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI                 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD                 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI                0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO                0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG                  0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL                0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE                0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE                 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM                0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT                0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED                 0xFFC03140 /* Type/Length Consistent RX Frame Count  */
-#define EMAC_RXC_SHORT                 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64                  0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128                 0xFFC0314C /* Good RX Frame Count - Byte Count  64 <= x < 128 */
-#define EMAC_RXC_LT256                 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512                 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024                0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024                0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_OK                    0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL                  0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL                0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET                 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER                 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL                0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL                0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND                0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR                0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST                0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI                 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD                 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR                0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL                0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM                0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT                0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64                  0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128                 0xFFC031C4 /* Good TX Frame Count - Byte Count  64 <= x < 128 */
-#define EMAC_TXC_LT256                 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512                 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024                0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024                0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT                 0xFFC031D8 /* Total TX Frames Aborted Count */
-#define USB_FADDR                      0xFFC03800 /* Function address register */
-#define USB_POWER                      0xFFC03804 /* Power management register */
-#define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX                     0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE                    0xFFC03810 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE                    0xFFC03814 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB                    0xFFC03818 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE                   0xFFC0381C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME                      0xFFC03820 /* USB frame number */
-#define USB_INDEX                      0xFFC03824 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE                   0xFFC03828 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR                   0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL                 0xFFC03830 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET              0xFFC03840 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0                       0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR                      0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET              0xFFC03848 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR                      0xFFC0384C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0                     0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT                    0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE                     0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0                  0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL                 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE                     0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL                 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT                    0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO                   0xFFC03880 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO                   0xFFC03888 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO                   0xFFC03890 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO                   0xFFC03898 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO                   0xFFC038A0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO                   0xFFC038A8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO                   0xFFC038B0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO                   0xFFC038B8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL                0xFFC03900 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ               0xFFC03904 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK              0xFFC03908 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO                   0xFFC03948 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN                      0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1                    0xFFC03950 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1                    0xFFC03954 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1                    0xFFC03958 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL                 0xFFC039E0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB                 0xFFC039E4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2                0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST                   0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL                0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV                 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP              0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR               0xFFC03A04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP              0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR               0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT             0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE              0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL          0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE              0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL          0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT             0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP              0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR               0xFFC03A44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP              0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR               0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT             0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE              0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL          0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE              0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL          0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT             0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP              0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR               0xFFC03A84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP              0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR               0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT             0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE              0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL          0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE              0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL          0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT             0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP              0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR               0xFFC03AC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP              0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR               0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT             0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE              0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL          0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE              0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL          0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT             0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP              0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR               0xFFC03B04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP              0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR               0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT             0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE              0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL          0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE              0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL          0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT             0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP              0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR               0xFFC03B44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP              0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR               0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT             0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE              0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL          0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE              0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL          0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT             0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP              0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR               0xFFC03B84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP              0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR               0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT             0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE              0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL          0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE              0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL          0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT             0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP              0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR               0xFFC03BC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP              0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR               0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT             0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE              0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL          0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE              0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL          0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT             0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT              0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL               0xFFC03C04 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW               0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH              0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW              0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH             0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL               0xFFC03C24 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW               0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH              0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW              0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH             0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL               0xFFC03C44 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW               0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH              0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW              0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH             0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL               0xFFC03C64 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW               0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH              0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW              0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH             0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL               0xFFC03C84 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW               0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH              0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW              0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH             0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL               0xFFC03CA4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW               0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH              0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW              0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH             0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL               0xFFC03CC4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW               0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH              0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW              0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH             0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL               0xFFC03CE4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW               0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH              0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW              0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH             0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_BF527_proc__ */
+#include "BF526_def.h"