diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/Kconfig | 47 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 57 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 |
4 files changed, 14 insertions, 95 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 698370b..52a9f39 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -770,6 +770,7 @@ config TARGET_LS1021AQDS select ARCH_LS1021A select ARCH_SUPPORT_PSCI select LS1_DEEP_SLEEP + select SYS_FSL_DDR config TARGET_LS1021ATWR bool "Support ls1021atwr" diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index d154f7b..eca1d06 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -3,8 +3,10 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A010315 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES - select SYS_FSL_DDR_BE - select SYS_FSL_DDR_VER_50 + select SYS_FSL_DDR_BE if SYS_FSL_DDR + select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR + select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR + select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE @@ -49,47 +51,6 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool -config SYS_FSL_DDR - bool "Freescale DDR driver" - help - Select Freescale General DDR driver, shared between most Freescale - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- - based Layerscape SoCs (such as ls2080a). - -config SYS_FSL_DDR_BE - bool - default y - help - Access DDR registers in big-endian. - -config SYS_FSL_DDR_VER - int - default 50 if SYS_FSL_DDR_VER_50 - -config SYS_FSL_DDR_VER_50 - bool - -config SYS_FSL_DDRC_ARM_GEN3 - bool - -config SYS_FSL_DDRC_GEN4 - bool - -config SYS_FSL_DDR3 - bool "Freescale DDR3 controller" - depends on !SYS_FSL_DDR4 - select SYS_FSL_DDR - select SYS_FSL_DDRC_ARM_GEN3 - help - Enable Freescale DDR3 controller on ARM-based SoCs. - -config SYS_FSL_DDR4 - bool "Freescale DDR4 controller" - select SYS_FSL_DDR - select SYS_FSL_DDRC_GEN4 - help - Enable Freescale DDR4 controller. - config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a1f781e..bee7d15 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -8,28 +8,33 @@ config ARCH_LS1012A config ARCH_LS1043A bool select FSL_LSCH2 + select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4 config ARCH_LS1046A bool select FSL_LSCH2 + select SYS_FSL_DDR select SYS_FSL_DDR_BE - select SYS_FSL_DDR4 select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 config ARCH_LS2080A bool select FSL_LSCH3 - select SYS_FSL_DDR4 + select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 select SYS_FSL_HAS_DP_DDR select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_DDR4 select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2 @@ -71,9 +76,6 @@ config FSL_PPA_ARMV8_PSCI implemented under the common ARMv8 PSCI framework. endmenu -config SYS_FSL_MMDC - bool - config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" @@ -129,49 +131,4 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool -config SYS_FSL_DDR - bool "Freescale DDR driver" - help - Select Freescale General DDR driver, shared between most Freescale - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- - based Layerscape SoCs (such as ls2080a). - -config SYS_FSL_DDR_BE - bool - help - Access DDR registers in big-endian. - -config SYS_FSL_DDR_LE - bool - help - Access DDR registers in little-endian. - -config SYS_FSL_DDR_VER - int - default 50 if SYS_FSL_DDR_VER_50 - -config SYS_FSL_DDR_VER_50 - bool - -config SYS_FSL_DDRC_ARM_GEN3 - bool - -config SYS_FSL_DDRC_GEN4 - bool - -config SYS_FSL_DDR3 - bool "Freescale DDR3 controller" - depends on !SYS_FSL_DDR4 - select SYS_FSL_DDR - select SYS_FSL_DDRC_ARM_GEN3 - help - Enable Freescale DDR3 controller on ARM-based SoCs. - -config SYS_FSL_DDR4 - bool "Freescale DDR4 controller" - select SYS_FSL_DDR - select SYS_FSL_DDRC_GEN4 - help - Enable Freescale DDR4 controller. - endmenu diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 29fc33d..db40669 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -175,11 +175,11 @@ #define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_ERRATUM_A009660 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -#elif defined(CONFIG_ARCH_LS1012A) -#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 +#elif defined(CONFIG_ARCH_LS1012A) #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 + #elif defined(CONFIG_ARCH_LS1046A) #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 |